Fundamental ofComputer Architecture

By Panyayot Chaikanpanyayot@coe.psu.ac.th

240-208

November 01, 2003

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 2

Chapter5ระบบอินพุตเอาต์พุตและระบบ

บสัInput/Output and

system bus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 3

เน้ือหา

นิยาม และคำาศัพท์ที่ควรรูเ้ก่ียวกับไมโคร โพรเซสเซอรแ์ละ ไมโครคอมพวิเตอร์

ประวติัความเป็นมาของไมโครโพรเซสเซอร์ขอ้ดีขอ้เสยีของไมโครโพรเซสเซอร์ขอ้พจิารณาในการเลือกใชไ้มโครโพรเซสเซอร์

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 4

รูปแบบของการอินพุตเอาต์พุต เมื่อมองจากชุดคำาสัง่ แบง่ออกได้ 2 ประเภท

Isolated I/O ไมโครโพรเซสเซอรจ์ะมคีำาสัง่ใน การจดัการอุปกรณ์อินพุตเอาต์พุตโดยเฉพาะ เชน่

คำาสัง่ IN คำาสัง่ OUT เป็นต้นเชน่ Z80, 80x86 เป็นต้น

Memory-Mapped I/O ไมโครโพรเซสเซอร์ จะไมม่คีำาสัง่ท่ีอ้างอิงอุปกรณ์ I/O โดยเฉพาะ แต่

จะสงวนหน่วยความจำาไวบ้างตำาแหน่งสำาหรบัอ้างอิง I/O devices เชน่ MCS-51, 68000 เป็นต้น

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 5

I/O interface for an input device

Input device

Addressdecoder Control C ircu it

Data andstatus

registers

A ddress linesC on tro l lines

D a ta lines

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 6

Parallel vs Serial

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 7

วธิกีารในการติดต่ออินพุต/เอาต์พุต

แบง่ได้ 3 รูปแบบหลักๆ ได้แก่ Polling Interrupt DMA

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 8

Polling ซพียูีต้องคอยวนลปูตรวจสอบความ

พรอ้มการติดต่อของอุปกรณ์ตลอดเวลา

เมื่อซพียูีถามมา หากอุปกรณ์ไม่ต้องการรบัสง่ขอ้มูลก็จะบอกให้ซพียูี

ได้รบัทราบ เสยีเวลาในการทำางานของซพียูีโดย

เปล่าประโยชน์

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 9

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 10

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 11

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 12

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 13

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 14

Polling

CPU M em ory I/O 1 I/O 2

Databus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 15

Interrupt ซพียูีไมต้่องคอยวนลปูถามความ

พรอ้มสง่ขอ้มูลของอุปกรณ์แต่ละตัว อุปกรณ์ใดพรอ้มสง่ขอ้มูลก็จะสง่

สญัญาณ อินเตอรร์พัต์ไปให้ซพียูี ซพียูีจะหยุดทำางานเดิมแล้วหันมาให้

บรกิารอุปกรณ์ท่ีสง่ขออินเตอรร์พัต์ เมื่อบรกิารอินเตอรร์พัต์เสรจ็ซพียูีจะ

กลับไปทำางานเดิมท่ีค้างไวต่้อไป

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 16

Interrupt

CPU M em ory I/O 1 I/O 2

INT

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 17

Interrupt service routine

ISR : interrupt service routine โปรแกรมบรกิารอินเตอรร์พัต์

เป็นโปรแกรมท่ีถกูเรยีกขึน้มาเมื่อเกิดสญัญาณอินเตอรร์พัต์

ISR จะต้องเก็บอยูใ่นหน่วยความจำาหลัก ISR อาจมไีด้หลายตัว เชน่ ISR สำาหรบั

คียบ์อรด์, ISR สำาหรบัเมาส ์เป็นต้น

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 18

Interrupt : Example

C P U

activeprogram

KeyboardISR

M em ory

in terrupt

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 19

Interrupt : Centralized arbitration

D evice1 D evice1 D evice1

Prio

rity

arbi

tratio

nci

rcui

t

C P U

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 20

Interrupt : Daisy chain

C P U

D evice1 D evice1 D evice1IN TA

IN T

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 21

DMA เป็นการรบัสง่ขอ้มูลโดยตรง

ระหวา่งอุปกรณ์ I/O กับหน่วย ความจำา โดยไมผ่่านซพียูี

ใชใ้นการสง่ขอ้มูลปรมิาณมากๆ เหมาะสำาหรบัการสง่ขอ้มูลไปยงั

หน่วยความจำาตำาแหน่งท่ีอยูติ่ดๆกัน

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 22

DMA

CPU M em ory I/O 1 I/O 2

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 23

Computer bus :A single bus structure

CPU Mem ory

I/O device 1 I/O device 2 I/O device n

bus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 24

Mezzanine busCPU Mem ory

I/O device 1 I/O device 2 I/O device n

sys tem bus

Expansion businterface

expans ion bus

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 25

PCI bus : feature Industry standard Processor independent Bus Speed 33, 66 MHz Transfer rate

133 Mbyte/S at 32 bit 266 Mbyte/S at 64 bit

Auto configuration Synchronous bus with

multiplexed Address/Data

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 26

PCI bus slots

From http://usa.asus.com/products/mb/socket754/k8v-d/overview.htm

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 27

Typical PCI connection for PC

P rocessor

B ridge/m em ory

contro lle r

cache

D R AM

Audio

P C I bus

LAN SC SI Expansionbus bridge

E xpansion bus

G raph ics

M otionV ideo

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 28Sing

le D

ata

read

: no

w

ait

stat

eCLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TR DY#

DEVSEL#

GNT#

data

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 29

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

T arget notReady

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 30

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

TRDY#

DEVSEL#

GNT#

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 31

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 32

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 33

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 34

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

byteenable

T arget notReady

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 35

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 36

Sing

le D

ata

read

: 1

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I RDY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 37

Burs

t re

ad :

no w

ait

stat

eCLOCK

FR AME#

AD[31:0]

C/ BE# [3:0]

I R DY#

ReadCommand

address

TR DY#

DEVSEL#

GNT#

data2

byteenable

data1

byteenable

data3

byteenable

data4

byteenable

data5

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 38Burs

t re

ad :

wit

h w

ait

stat

eCLOCK

FR AME#

AD[31:0]

C/ BE# [3:0]

I R DY#

ReadCommand

address

TRDY#

DEVSEL#

GNT#

data2

byteenable

data1

byteenable

data3

byteenable

data4

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 39

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

TRDY#

DEVSEL#

GNT#

Sing

le D

ata

Wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 40

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

Sing

le D

ata

Wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 41

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

Sing

le D

ata

Wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 42

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

Sing

le D

ata

wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 43

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

Sing

le D

ata

wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 44

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

Sing

le D

ata

wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 45

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

Sing

le D

ata

wri

te :

no

wai

t st

ate

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 46Sing

le d

ata

wri

te :

no

wai

t st

ate

CLOCK

FR AME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TRDY#

DEVSEL#

GNT#

data

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 47Burs

t w

rite

: no

wai

t st

ate

CLOCK

FRAME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TR DY#

DEVSEL#

GNT#

data2data1

byteenable

data3

byteenable

data4

byteenable

data5

byteenable

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 48Burs

t w

rite

: w

ith

wai

t st

ate

CLOCK

FR AME#

AD[31:0]

C/ BE# [3:0]

I R DY#

W riteCommand

address

TR DY#

DEVSEL#

GNT#

data2data1

byteenable

data3

byteenable

data4

byteenable

byteenable

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 49

Serial port Interfacing

RS-232C standard – defined by EIA

Full duplex Widely Used in

PCFrom http://www.packetradio.com/conns/db9pc.gif

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 50

UART: Universal Asynchronous

receiver/transmitter

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 51

Parallel-to-serial conversion

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 52

Asynchronous Serial data communication

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 53

Parallel port interfacing :

Keyboard

Processor

DATAIN

S in

inp u tin te rface

da ta

add ress

R /W

M aste r read y

S lave ready

Encoderand

debouncingcircuit

Keyboardswitches

da ta

va lid

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 54

Parallel port interfacing : Printer

Processor Sout

O utpu tin te rface

da ta

address

R /W

M aste r ready

S lave ready

Printer

da ta

Id le

V a lid

da taou t

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 55

PC I/

O

Exam

ple

From

http

://ww

w.vi

a.co

m.tw

/en/

p4-s

erie

s/pt

800.

jsp

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 56

PC I/O example

From http://www.sis.com/products/chipsets/oa/socketa/748.htm

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 57

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 58

USB Plug and Play capability Speed from 1.5 Mbps to 12

480Mbps( Mbps in USB2.0)

Hot Swap capability Low cost Up to 1 2 7 devices can be

ccccccccc cc ccc ccc

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 59

USB hub

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 60

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 61

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 62

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 63

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 64

USB vs Parallel/Serialport

FeatureUSB Serial Paralle l

Industry Standard Yes Yes No

115 KBps

EPP/ECP - 3 MBps

Number of Devices 127 devices on a single USB bus Limited to the number of ports available on the computer.

Limited to the number of ports available on the

computer.Bus Power Yes, can provide up to 500 mA at

5VNo No

Cable Length Limit 5 m / 16.4 ft 3 m / 10 ft 1.8 m / 6 ft

Plug'n'Play Yes No No

Hot Swapable Yes No No

Bandwidth 12 Mbps 115 Kbps

240-208 Fundamental of Computer Architecture Chapter 5 – Input/Output and system bus 65

จบ บทท่ี 5