Chapter 5 Synchronous Sequential Logic 授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.) E-mail: [email protected]@yuntech.edu.tw Tel: (05)5342601 ext

Chapter 5

Synchronous Sequential Logic

授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.)E-mail: [email protected]: (05)5342601 ext. 4337Office: EB212

5-2Digital Circuits

5-1 Introduction

Combinational circuits contains no memory elements the outputs depends on the inputs

5-3Digital Circuits

5-2 Sequential Circuits

■ Sequential circuits Sequential circuits consist of a feedback path The binary information stored in these elements at any given

time defines the state of the sequential circuit (inputs, current state) (outputs, next state) synchronous: the transition happens at discrete instants of time asynchronous: at any instant of time

5-4Digital Circuits

Synchronous sequential circuits a master-clock generator to generate a periodic

train of clock pulses the clock pulses are distributed throughout the

system Also called clocked sequential circuits

most commonly used no instability problems the memory elements: flip-flops

binary cells capable of storing one bit of information two outputs: one for the normal value and one for the

complement value maintain a binary state indefinitely until directed by an

input signal to switch states

5-2 Sequential Circuits (cont.)

5-5Digital Circuits

Fig. 5.2Synchronous clocked sequential circuit

5-2 Sequential Circuits (cont.)

多了時脈訊號

5-6Digital Circuits

5-3 Latches

Latches Storage elements that operate with single level. level sensitive devices

Flip-Flops Controlled by a clock transition. Edge sensitive devices

5-7Digital Circuits

5-3 Latches Basic flip-flop circuit

two NOR gates

more complicated types can be built upon it directed-coupled RS flip-flop: the cross-coupled connection an asynchronous sequential circuit (S,R)= (0,0): no operation (S,R)=(0,1): reset (Q=0, the clear state) (S,R)=(1,0): set (Q=1, the set state) (S,R)=(1,1): indeterminate state (Q=Q'=0)

5-8Digital Circuits

SR latch with NAND gates

Fig. 5.4SR latch with NAND gates

5-3 Latches (cont.)

5-9Digital Circuits

SR latch with control input En=0, no change En=1, information from the S or R input is allowed

to affect the latch.

Fig. 5.5 SR latch with control input

5-3 Latches (cont.)

The set state is reached with En=1, S=1, R=0To change to the reset state, En=1, S=0, R=1When En=0, the circuit remains in its current state.An indeterminate condition occurs when all three inputs are equal to 1

S-

R-

5-10Digital Circuits

D Latch eliminate the undesirable conditions of the

indeterminate state in the RS flip-flop D: data gated D-latch D Q when En=1; no change when En=0

Fig. 5.6D latch

S_

R_

0/1

1/D'

1/D

5-3 Latches (cont.)


Fig. 5.7 Graphic symbols for latches

5-3 Latches (cont.)

當 NAND gate 的輸入端為 1 時，輸出的狀態由另一個輸入端決定。

當 NAND gate 的輸入端為 0 時，輸出端必為 1 。因此， NAND gate 屬於低態動作 (active low) 。所以在輸入

端加上小圈圈。

NOR 組成之 RS Flip-FlopNAND 組成之 RS Flip-Flop


5-4 Flip-Flops A trigger

The state of a latch or flip-flop is switched by a change of the control input

Level triggered – latches Edge triggered – flip-flops

Fig. 5.8Clock response in latch and flip-flop


If level-triggered flip-flops are used the feedback path may cause instability problem

To solve the instability problem Master-Slave Flip-Flops Edge-triggered flip-flops

the state transition happens only at the edge eliminate the multiple-transition problem

5-4 Flip-Flops (cont.)


Edge-triggered D flip-flop

Master-slave D flip-flop two separate flip-flops a master flip-flop (positive-level triggered) a slave flip-flop (negative-level triggered)

Fig. 5.9Master-slave D flip-flop

Clk=0, slave D latch Enable, Q=Y master D latch DisableClk=1, master D latch Enable, Y=D slave D latch Disable, Q=YClk=0, slave D latch Enable, Q=D master D latch disable


CP = 1: (S,R) (Y,Y'); (Q,Q') holds CP = 0: (Y,Y') holds; (Y,Y') (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negative-edge

transition of CP

第三版內容，參考用 !


Edge-triggered flip-flops the state changes during a clock-pulse transition

A D-type positive-edge-triggered flip-flop

Fig. 5.10D-type positive-edge-triggered flip-flop

When Clk=0, S and R are maintainedat the logic-1 level.=> 輸出維持現態。

Clk=1, D=0 => R=0, => Q=0


three basic flip-flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided

Fig. 5.10D-type positive-edge-triggered flip-flop


1 0 1

第三版內容，參考用 !


The setup time D input must be maintained at a constant value prior to the

application of the positive Clk pulse = the propagation delay through gates 4 and 1 data to the internal latches

The hold time D input must not changes after the application of the positive

Clk pulse = the propagation delay of gate 3 clock to the internal latch

The propagation delay time The interval between the trigger edge and the stabilization of

the output to a new state.


Summary Clk=0: (S,R) = (1,1), no state change Clk=: state change once Clk=1: state holds eliminate the feedback problems in sequential

circuits All flip-flops must make their transition at the

same time


Other Flip-Flops

The edge-triggered D flip-flops The most economical and efficient Positive-edge and negative-edge

Fig. 5.11Graphic symbols for edge-triggered D flip-flop


JK flip-flop

D=JQ'+K'Q J=0, K=0: D=Q, no change J=0, K=1: D=0 Q =0 J=1, K=0: D=1 Q =1 J=1, K=1: D=Q' Q =Q'

Fig. 5.12JK flip-flop


T flip-flop

D = T Q = TQ'+T'Q⊕ T=0: D=Q, no change T=1: D=Q' Q=Q'

Fig. 5.13T flip-flop


Characteristic tables


Characteristic equations D flip-flop

Q(t+1) = D JK flip-flop

Q(t+1) = JQ'+K'Q T flop-flop

Q(t+1) = T⊕Q


Direct inputs asynchronous set and/or asynchronous reset

S_

reset_ Fig. 5.14D flip-flop with asynchronous reset


5-5 Analysis of Clocked Sequential Circuits

A sequential circuit Clocked sequential circuit (inputs, current state) (output, next state) 推得 a state transition table or state transition

diagram

Fig. 5.15Example of sequential circuit


State equations

A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A'(t)x(t)

A compact form A(t+1) = Ax + Bx B(t+1) = A’x

The output equation y(t) = (A(t)+B(t))x'(t) y = (A+B)x'


State table State transition table

= state equations


State equation

A(t + 1) =Ax + BxB(t + 1) = Axy = Ax + Bx

由 Table 5.2 ，以卡諾圖畫簡可得 state equation

State Table 也可表示成下表


State diagram State transition diagram

a circle: a state a directed lines connecting the circles: the

transition between the states Each directed line is labeled 'inputs/outputs‘

a logic diagram a state table a state diagram

Fig. 5.16State diagram of the circuit of Fig. 5.15


Flip-flop input equations

Flip-flop input equation The part of circuit that generates the inputs to flip-

flops Also called excitation functions DA = Ax +Bx

DB = A'x

The output equations The part of the combinational circuit that

generates external outputs is described algebraically by a set of Boolean functions

to fully describe the sequential circuit y = (A+B)x'


Analysis with D flip-flops The input equation

DA=A⊕x⊕y The state equation

A(t+1)=A⊕x⊕y

Fig. 5.17Sequential circuit with D flip-flop


Analysis with JK flip-flops Determine the flip-flop input function in terms of

the present state and input variables Used the corresponding flip-flop characteristic

table to determine the next state

Fig. 5.18Sequential circuit with JK flip-flop


JA = B, KA= Bx' JB = x', KB = A'x + Ax’ derive the state table

Or, derive the state equations using characteristic eq.

Analysis with JK flip-flops (cont.)


State transition diagram

Fig. 5.19State diagram of the circuit of Fig. 5.18

( 1)

( 1)

A t JA K A

B t JB K B

State equation for A and B:

( 1) ( )A t BA Bx A A B AB Ax

( 1) ( )B t x B A x B B x ABx A Bx

Analysis with JK flip-flops (cont.)


Analysis with T flip-flops The characteristic equation

Q(t+1)= T⊕Q = TQ'+T'Q

Fig. 5.20Sequential circuit with T flip-flop


Analysis with T flip-flops (cont.)

The input and output functions TA=Bx

TB= x y = AB

The state equations A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx B(t+1) = x⊕B


State Table

Analysis with T flip-flops (cont.)


Mealy and Moore models

The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15) the outputs may change if the inputs change

during the clock pulse period the outputs may have momentary false values unless the

inputs are synchronized with the clocks

The Moore model: the outputs are functions of the present state only (Fig. 5-18, 5-20) The outputs are synchronous with the clocks


Mealy and Moore models (cont.)

Fig. 5.21Block diagram of Mealy and Moore state machine


5-7 State Reduction and Assignment

State Reduction reductions on the number of flip-flops and the

number of gates a reduction in the number of states may result in a

reduction in the number of flip-flops a example state diagram

Fig. 5.25 State diagram


state a a b c d e f f g f g a input0 1 0 1 0 1 1 0 1 0 0

output 0 0 0 0 0 1 1 0 1 0 0 only the input-output sequences are important two circuits are equivalent

have identical outputs for all input sequences the number of states is not important

Fig. 5.25 State diagram


Equivalent states Two states are said to be equivalent

for each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state

one of them can be removed


Reducing the state table e=g d=?

( 狀態 g 已經被狀態 e 所取代 )


the reduced finite state machine

state a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0

( 狀態 f 已經被狀態 d 所取代 )


the checking of each pair of states for possible equivalence can be done systematically (9-5)

the unused states are treated as don't-care condition fewer combinational gates

Fig. 5.26 Reduced State diagram


State assignment

to minimize the cost of the combinational circuits three possible binary state assignments


State assignment

any binary number assignment is satisfactory as long as each state is assigned a unique number

use binary assignment 1


5-8 Design Procedure

From the word description of the circuit behavior, derive a state diagram for the circuit.

State reduction if necessary Assign binary values to the states Obtain the binary-coded state table Choose the type of flip-flops Derive the simplified flip-flop input equations and

output equations Draw the logic diagram


Synthesis using D flip-flops An example state diagram and state table

Detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line.

Fig. 5.27 State diagram for sequence detector


The flip-flop input equations A(t+1) = DA(A,B,x) = (3,5,7)

B(t+1) = DB(A,B,x) = (1,5,7)

The output equation y(A,B,x) = (6,7)

Logic minimization using the K map DA= Ax + Bx

DB= Ax + B'x y = AB

Synthesis using D flip-flops


Fig. 5.28 Maps for sequence detector


Sequence detector The logic diagram

Fig. 5.29 Logic diagram of sequence detector


Excitation tables

A state diagram flip-flop input functions straightforward for D flip-flops we need excitation tables for JK and T flip-flops


Synthesis using JK flip-flops The state table and JK flip-flop inputs


JA = Bx'; KA = Bx JB = x; KB = (A x)‘⊕ y = ?

Fig. 5.30 Maps for J and K input equations


Fig. 5.31 Logic diagram for sequential circuit with JK flip-flops


Synthesis using T flip-flops A n-bit binary counter

the state diagram

no inputs (except for the clock input)

Fig. 5.32 State diagram of three-bit binary counter


The state table and the flip-flop inputs


Fig. 5.33 Maps of three-bit binary counter


Logic simplification using the K map TA2 = A1A2

TA1 = A0

TA0 = 1

The logic diagram

Fig. 5.34 Logic diagram of three-bit binary counter


5-7 Synthesizable HDL Models of Sequential Circuits Behavioral Modeling

Example: Two ways to provide free-running clock

Example: Another way to describe free-running clock


Behavioral Modeling

always statement

Examples:

Two procedural blocking assignments:Two nonblocking assignments:


Flip-Flops and Latches

■ HDL Example 5.1


Flip-Flops and Latches

■ HDL Example 5.2


Characteristic Equation

Q(t + 1) = Q ⊕ TQ(t + 1) = JQ + KQ

For a T flip-flop

For a JK flip-flop

■ HDL Example 5.3


HDL Example 5-3 (Continued)


HDL Example 5-4

Functional description of JK flip-flop


State Diagram

■ HDL Example 5.5: Mealy HDL model






Mealy_Zero_Detector

Fig. 5.22 Simulation output of Mealy_Zero_Detector


HDL Example 5-6: Moore Model FSM


Simulation Output of HDL Example 5-6

Fig. 5.23 Simulation output of HDL Example 5.6


Structural Description of Clocked Sequential Circuits

■ HDL Example 5.7: State-diagram-based model










Simulation Output of HDL Example 5-7

Fig. 5.24 Simulation output of HDL Example 5.7

Documents

Chapter 5 Synchronous Sequential Logic 授課教師 : 張傳育 博士 (Chuan-Yu Chang Ph.D.) E-mail: [email protected]@yuntech.edu.tw Tel: (05)5342601 ext

Chapter 5 Synchronous Sequential Logic 授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.) E-mail: [email protected]@yuntech.edu.tw Tel: (05)5342601 ext