Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series

Lab : SmarTest and Digital Testing Module

1. Change directory to $HOME a unix% cd ~

2. Invoke SmarTest offline mode

a unix% HPSmarTest -o &

3. Create a SmarTest Device Directory a SmarTest

b Devicechange device

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series c Device DUT BUFCTRLCreate

d Device name DUT PPU tester model P600 default create device

e Device Device Data Manager

f Setup data Manager Select Setup

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 4. Defining the Pins

a Pin Config CONFIG Pin Configuration

b Pin Configuration ModeEDITOR Mode

c Pin Configuration Download Pin No Pin Name Mode Type Ser.R[Ohm]

Load C [uF] Tester Channel

1 reset std i 0. 11715 2 burst std i 0. 11716 3 valid std o 0. 11802 4 put std i 0. 11804 5 data3 std io 0. 11806 6 data2 std io 0. 11808 7 data1 std io 0. 11810 8 data0 std io 0. 11812 9 addri0 std i 0. 11814 40 addri1 std i 0. 11706 41 addri2 std i 0. 11707 42 rdy std o 0. 11708 43 clk1 std i 0. 11709 44 clk2 std i 0. 11710 45 get std i 0. 11711 46 addro0 std o 0. 11712

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 47 addro1 std o 0. 11713 48 addro2 std o 0. 11714 iovdd DPS 1. DPS12 corevdd1 DPS 1. DPS23 corevdd2 DPS 1. DPS24

d Pin Configuration Selectgroups Pin Group Definition

e Pin Group Definitionnew atomar definition pin group define

f group groupname group group pincopy pin name group member paste delete group member copy all Iscopy all Os/group members save group groups

i. ALLINPUT

ii. ALLIO

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series iii. ALLOUTPUT

g group Pin Group Definition done Pin Configuration

h Data Manager CONFIG CONFIG DIP18save Pin Configuration

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 5. Defining the Levels

a LEVEL Level Setup b Level Setup Select

Edit Equations

c Level EquationsShellDownload

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series d Level Specifications Level Setup Select

Edit SpecificationsSpec Tool

e Select level equation set Eqn Description 1 levels equation setcreate

f Spec set Create level spec set unused Numbers 1Description spec01create

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series g Select level equation set done

Level Equations spec Spec Tool Level

h Level Spec Doenload

i Spec Tool Level Setup Level levelsave

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series j level Level Setup Select

Show I/O Eqn. & Specs ResultsShow DPS Eqn. & Specs Results I/O Pin DPS Pin Level

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 6. Defining the Timing and Vector

a ASCII Interface Timing Vector

b ASCII Interface terminal unix% cp -rf ~ateusr/ate_env_file/ASCII_TOOLs ~/BUFCTRL/.

c ASCII TOOLS avc pattern ascii_vectors unix% cp ~ateusr/ate_env_file/Lab/d93000_lab_bufctrl_1.v ~/BUFCTRL/ASCII_TOOLs/ascii_vectors/. pattern unix% cp ~ateusr/ate_env_file/Lab/d93000_lab_bufctrl_2.v ~/BUFCTRL/ASCII_TOOLs/ascii_vectors/.

d ASCII_TOOLs/x1_mode.bash

e ASCII_TOOLs/sample.aic

#!/bin/bash

ait -i sample -o bufctrl -z P600

aiv bufctrl

\cp bufctrl.tim ../timing

\cp single_vectors/*.binl.gz ../vectors/

AI_DIR_FILE

tmp_dir ./tmp

tmf_dir ./timing_mapping_files

vbc_dir ./

avc_dir ./ascii_vectors/

allvec_file ./all_vectors/all

pinconfig_file /home/user93k//BUFCTRL/configuration/DIP18

single_binary_pattern_dir ./single_vectors/

PATTERNS name type ctim xfact {vec_ascii_dvc ascii_dvc};

d93000_lab_bufctrl_1 MAIN NCT 1 {std std};

d93000_lab_bufctrl_2 MAIN NCT 1 {std std};

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series f ASCII_TOOLs/sample.dvc

g avcaic dvc unix% ./x1_mode.bash

SPECS default

freq 10

EQUATIONS std1

Tperiod = 1/freq*1000

t1 = Tperiod/4

t2 = Tperiod/2

t3 = 0.75*Tperiod

t4 = 0.42*Tperiod

DVC std

period = Tperiod

PINS clk1

1 F00:0 F10:t1 F00:t3

PINS ALINPUT clk2

0 F00:0

1 F10:0

PINS ALLOUTPUT

L FNZ:0 L:t2

H FNZ:0 H:t2

X FNZ:0 X:t2

PINS ALLIO

0 F00:0 X:t4

1 F10:0 X:t4

L FNZ:0 L:t4

H FNZ:0 H:t4

X FNZ:0 X:t4

x FNZ:0 X:t4

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series h Timing Vector

Data Manager Timing vector

i Specs Data Manager

Timing Level Spec

i. Timing Timing Eqns Timing Select Specification

Specifications Timings Select Data Manager Timing EqnsTiming Specs Timing Set

ii. Level Level Eqns Level Select Specification Specifications Levels

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series Select Data ManagerLevel EqnsLevel Specs Level Set

j Data Manager DATA SETBUFCTRLsave check message BUFCTRL OK

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 7. Standard Test Function execution

lab PASS a Main Tool Bar Data Manager Test Control

Test Control

b Editdefault Test group

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series c Test group DC Testsgroup

continuityexec ui_report pass fail

d defaultDC TestsDPS Connectivityexec ui_report

e defaultAC Testsfunctionalexec ui_report

f defaultSweep Testsshmoo_spec

new shmoo exec shmoo pass

Chip Implementation Center (CIC) The Digital IC Testing with V93K SoC Series 8. Verigy 93000 Series main tool bar FileQuit

STOP

End of Lab