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Configuration File

Spartan-IIE devices are configured by sequentially loading

frames of data that have been concatenated into aconfiguration

file.

PROM, hard drives, FLASH cards are commonly used to storeconfiguration data before loading them into the FPGA

Configuration

Configuration is the process by which the bitstream of a

design, as generated by the Xilinx development software, is

loaded into the internal configuration memory of the FPGA.

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There are two kinds of pins that are used to configure Spartan-

IIE devices: Dedicated pins perform only specificconfiguration-related functions; the other pins can serve as

general purpose I/Os once user operation hasbegun.The dedicated pins compeises

the mode pins (M2, M1, M0)

the configuration clock pin (CCLK)

the PROGRAM pin(active low)

the DONE pin

and the boundary-scan pins (TDI, TDO, TMS,TCK).

Depending on the selected configuration mode, CCLK maybe an output generated by the FPGA, or may be generated

externally, and provided to the FPGA as an input.

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The Process

The sequence of steps necessary to configure Spartan-IIE

devices can be divided into three different phases.

Initiating configuration

Configuration memory clear

Loading data frames

Start-up

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Loading Conf igurat ion Data

Once INIT is High, the user can beginloading configuration data frames into thedevice.

CRC Error Checking

After the loading of configuration data, a CRC valueembedded in the configuration file is checked againsta CRC value calculated within the FPGA. If the CRC

values do not match, the FPGA drives INIT Low toindicate that an error has occurred and configurationis aborted.

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Slave Serial Mode ( M0=1 M1=1 M2=1 )

In Slave Serial mode, the FPGAs CCLK pin is driven by anexternal source, allowing the FPGA to be configured fromother logic devices such as microprocessors or in a daisychain configuration

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Master Serial Mode( M0=0 M1=0 M2=0 )

In Master Serial mode, the CCLK output of theFPGA drives a Xilinx PROM, which feeds a serialstream of configuration data to the FPGAs DIN

input.

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Slave Parallel Mode (SelectMAP)

( M0=0 M1=1 M2=1 )

The Slave Parallel mode, also known as SelectMAP, is

the

fastest configuration option. Byte-wide data is writteninto

the FPGA on the D0-D7 pins. Note that D0 is the MSBof

each byte for configuration.

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Boundary-Scan Configuration Mode ( M0=1 M1=0 M2=1

)

In the boundary-scan mode, no nondedicated pins arerequired,configuration being done entirely through the

IEEE 1149.1 Test Access Port (TAP).

Configuration through the TAP uses the special CFG_IN

instruction. This instruction allows data input on TDI to be

converted into data packets for the internal configuration

bus.