This article was downloaded by: [Tufts University]On: 07 October 2014, At: 08:52Publisher: Taylor & FrancisInforma Ltd Registered in England and Wales Registered Number: 1072954 Registered office: MortimerHouse, 37-41 Mortimer Street, London W1T 3JH, UK

IETE Journal of ResearchPublication details, including instructions for authors and subscription information:http://www.tandfonline.com/loi/tijr20

Design and Implementation of SPDT Switch, 6 BitDigital Attenuator, 6 bit Digital Phase Shifter For L-Band T/R Module Using 0.7µm GaAs MMIC TechnologyNagaveni D Doddamania, Anil V Nandia & Harish chandrab

a Department of Electronics and CommunicationB V Bhoomaraddi College of Engineeringand Technology, Hubli 580 031, India e-mail: ,b Electromics and Radar Development EstablishmentC V Raman Nagar, Bangalore 560093, India e-mail:Published online: 01 Sep 2014.

To cite this article: Nagaveni D Doddamani, Anil V Nandi & Harish chandra (2007) Design and Implementation of SPDTSwitch, 6 Bit Digital Attenuator, 6 bit Digital Phase Shifter For L-Band T/R Module Using 0.7µm GaAs MMIC Technology,IETE Journal of Research, 53:6, 527-532, DOI: 10.1080/03772063.2007.10876169

To link to this article: http://dx.doi.org/10.1080/03772063.2007.10876169

PLEASE SCROLL DOWN FOR ARTICLE

Taylor & Francis makes every effort to ensure the accuracy of all the information (the “Content”) containedin the publications on our platform. However, Taylor & Francis, our agents, and our licensors make norepresentations or warranties whatsoever as to the accuracy, completeness, or suitability for any purpose ofthe Content. Any opinions and views expressed in this publication are the opinions and views of the authors,and are not the views of or endorsed by Taylor & Francis. The accuracy of the Content should not be reliedupon and should be independently verified with primary sources of information. Taylor and Francis shallnot be liable for any losses, actions, claims, proceedings, demands, costs, expenses, damages, and otherliabilities whatsoever or howsoever caused arising directly or indirectly in connection with, in relation to orarising out of the use of the Content.

This article may be used for research, teaching, and private study purposes. Any substantial or systematicreproduction, redistribution, reselling, loan, sub-licensing, systematic supply, or distribution in anyform to anyone is expressly forbidden. Terms & Conditions of access and use can be found at http://www.tandfonline.com/page/terms-and-conditions

IETE Journal of ResearchVol 53, No.6, November-December 2007, pp 523-532

Design and Implementation of SPDT Switch, 6 BitDigital Attenuator, 6 bit Digital Phase Shifter For L­

Band T/R Module Using O.71Jm GaAs MMIC TechnologyNAGAVENI D DODDAMANI, ANIL V NANDI

Department of Electronics and Communication, B V Bhoomaraddi College of Engineering andTechnology, Hubli 580 031, India. e-mail: nagaveni30@yahoo.co.in.anilnandy@bvb.edu

AND

HARISHCHANDRA

Electromics and Radar Development Establishment, C V Raman Nagar, Bangalore 560 093, India.e-mail: harishchandra2000@yahoo.com.

The performance of modern radar systems with active phased array antennas is mainlydriven by the performance of the microwave TIR modules. To reduce the size, weight, costand power consumption, as weil as to achieve better phase and amplitude accuracies forrealizing low side lobe levels with an accurate beam steering, TIR modules, now-a-days,employ MMICs (Monolithic Microwave Integrated Circuits) for Implementing TransmlUReceive chain.

The L-band SPDT Switch, 6-Bit Digital Attenuator, 6·Blt Digital Phase Shifter have beendesigned using GAETEC Hyderabad 0.7um GaAs MESFET Switch model to handle 30dBmpeak power. All the above components have been designed and simulated using AgilentADS CAD tool Interfaced with Academy Layout.

The SPOT Switch with Insertion loss less than -1dB, isolation greater than 60dB andreturn loss better than 20dB has been realized on a single 3.0 mm )( 2.35 mm GaAs chip. A6·Bit Digital Attenuator has a 31.5dB attenuation range In 0.5dB Increments, 2.50 phaseerror and return loss better than 15dB. The 6 bits are cascaded to form a completeattenuator on a double 3.5 mm )( 2.35 mm GaAs chip with 3 attenuator bits In each for abetter yield. A 6-Bit Digital Phase Shifter with 9dB insertion loss, return loss better than15 dB has been realized on a two GaAs chips with size 4.0mm )( 2.35mm and 3.0 mm )(2.35 mm and 3 phase bits in each chip for the better yield.

Indexing tenns: Monolithic microwave integrated circuit, T/R module, SPOT switch, Digitalattenuator, Digital phase shifter.

Phased Array antennas is mainly driven by theperformance of the TIR Modules which form the keyelements of the Active Phased Array. The concept ofActive Aperture Array is critically dependent on theavailability of compact and minimum weight, lowconsumption and high reliability Microwave TIRmodules. The large number of individual TIRmodules integrated with the respective radiatingelements of the Active Array ensures a great degreeof redundancy in case of failure of elements (gracefuldegradation). Due to the close connection of the TIRmodules to the radiating, the losses in both cases,transmit and receive, are low, compared to passivearray systems. This leads to a low receive noise figure

523

MODERN day Phased Array Radar Systemsemploy Active Aperture Array architecture to

overcome the major Passive Array problems of lpwerreliability and higher losses/lesser efficiency. AnActive Phased Array utilizes individual Solid-StateTransmitlReceive (TIR) Microwave Module at eachof its radiating elements, distributed over the ArrayAperture, and consequently provides a significantlyhigher efficiency, smaller size and lighter weight thanthe conventional Passive Phased Array Systems. Theperformance of modem Radar Systems with Active

Paper No 70-A; Copyright @ 2007 by the IElE.

1. INTRODUCTION

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

52~ IETE JOURNAL OF RESEARCH, Vol 53, No.6, November-December 2007

TABLE 1: Design specifications of SPDT Switch

2. MMIC SPOT SWITCH

and high transmit efficiency.

To reduce the size, weight, cost and powerconsumption, as well as to achieve better phase andamplitude accuracies for realizing low side lobelevels with an accurate beam steering, TIR modules,now-a-days, employ MMICs (Monolithic MicrowaveIntegrated Circuits) for implementing their receivechain and also part of their Transmit chain [1].

This paper describes the design, performance andtest results of GaAs monolithic SPDT Switch, 6-BitDigital Attenuator and 6-Bit Digital Phase Shifter.

In recent years GaAs FET based monolithicswitches have been replaced by PIN diodes especiallyfor low to medium power and medium to high powerapplications. GaAs FET MMIC switches have alsobeen demonstrated for high linearity and powerhandling requirements. Monolithic implementationhas resulted in some very high performance andextremely complex circuits being realized on verysmall chips.

2.1. Circuit Design

In design of SPDT Switch 0.7~m Switch ModelMESFET Transistor is used. The Designspecification of a SPDT Switch is given in Table 1.

The SPDT switch is based on the use of MetalSemiconductor Field Effect Transistors (MESFET)as the active elements as shown in Fig 1. EightMESFETs are arranged in two mirror-image series­shunt configurations originating at the common RFnode. The series MESFET provides a through pathfor the "on" arm while the shunt MESFET providesisolation for the "off' arm. Two 3k ohm resistors willbe connected to control inputs at port2 and port3 tothe MESFET gates while providing isolation betweenthe RF path and the control circuitry. Each seriesMESFET gate is connected to the shunt MESFETgate on the opposite arm of the switch.

The width of the MESFET is decided by thepower handling capability, insertion loss, isolationand the length of the transmission lines is used toprovide signal integrity and proper matching for goodreturn loss, high isolation and less insertion loss.

The circuit has been laid out compactly in a chipsize of 3.0 mm x 2.35 mm.

The circuit topology is based on first stage series­shunt and second stage shunt-series switchconfiguration for obtaining the required Isolation andInsertion loss. The transmission lines (TL1 to TL6)

used for connecting the two stages of series-shunt /shunt -series MESFETs in each of the arms (FET1 toFET4 or PETs to FET8) have been designed forappropriate impedance and length for a good returnloss characteristics of the switch in either of themodes viz., Insertion loss and isolation. The biasingcircuitry also has been chosen appropriately for theoperation of the SPDT switch with complementarygate control voltages (VG and VG) which could beapplied through series mounted high value resistors(-3K.). The biasing circuitry is appropriately chosenfor operation with complementary gate controls. Inthe on-state, the low channel resistance of the FET isthe dominating parameter and this results in avirtually independent frequency response.

In the off-state, however, the equivalentcapacitance of the circuit dominates and this showsstrong frequency dependence. Therefore, insertionloss for the series FET and isolation for the shuntFET configurations,' both in the on-state, showfrequency invariant behavior. On the other hand,isolation for the series FET and insertion loss for theshunt FET configurations, both in the off-state, showfrequency dependence. Increasing the size of the FETreduces its on-state resistance and thus reducesinsertion loss. However, it also results in increasedgate-source and gate-drain capacitance and increasedsource-drain fringing capacitance, which limit theswitch performance in the off-state. ....,

In the two switching states the gate junction iseither reverse biased or is biased at zero gate-sourcebias voltage. In both these states the gate drawsnegligible current, which greatly simplifies thecontrol circuit design requirements. In the off-state ofthe FET switch, the gate-drain and gate-sourcecapacitances are equal, as both the source and drainterminals are not isolated from each other and the RFimpedance of the gate bias circuit affects theequivalent drain-source impedance.

<-15 dB

<-15 dB

<-1.0 dB

>60dB

30dBm

<50ns

Input return loss

Output return loss

Insertion loss

Is'olation

Power handling

Switching speed

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

N D DODDAMANI et al: DESIGN AND IMPLEMENTATION OF SPDT SWITCH 525

3. MMIC DIGITAL ATTENUATOR

A digital attenuator consists of a number ofcascaded units, each containing an individual bit thatcan be switched in or out to achieve the desired valueof attenuation. These cascaded bits are usually binaryweighted with the least significant bit (LSB) level asthe minimum resolvable level. The most significantbit (MSB) determines the upper level of attenuation.Minimum attenuation is obtained when all theindividual bit states are turned off, while at themaximum attenuation level all the individual bit statesare turned on [2,3].

The six required amplitude bits are O.5dB, l.OdB,

. TABLE 2 Design specification of a digital attenuator

Insertion loss

I/O return loss

Phase error

Amplitude error

4.5 dB (max.) .

-15 dB (max.)

± 2S (max.)

± 0.5 dB (max.)

2.0dB, 4.0dB, 8.0dB, 16.0dB 'which provide O.5dBresolutio~ over 31.5dB dynamic range. The Designspecification of a SPDT Switch is given in Table 2.

3.1. Circuit Design

For smaller bit attenuation values of up to 8dBswitched bridged T-attenuator technique as shown inFig 2 is been used. For larger attenuation bit switchedn attenuator as shown in Fig 3 is been used. Two 8­dB attenuator bit with switched n attenuatortechnique has been cascaded to achieve 16 dB.

The switched bridged T-attenuator configurationconsists of a classical bridged T-attenuator with ashunt and series PET, as shown in Fig 2. SwitchedPETs are placed across the bridge resistor R I and inseries with the shunt resistor Rz. These two PETs areswitched on or off to switch between the zero stateand the attenuation state, whose value is determinedby the bridged T-attenuator. The bridged T-attenuatorinherently provides good input and output matches.

1'1:71

Fig 1 SPDT switch

J.- ..J .... ---.

f"ET2

IN R2 au0 ..............,...,.·_- ..-----"'~, ...".... ....---..-- ------

Yo.

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

526 JETE JOURNAL OF RESEARCH, Vol 53, No.6, November-December 2007

Va bits has been cascaded in this manner to reduceinteractive effects.

4. MMIC DIGITAL PHASE SHIFTER

Ro = Circuit characteristic impedance in Ohms.

A = Attenuation value in dB.

Similar to the bridged-T attenuator configuration,Switched n attenuator technique offers lowerinsertion loss than the switched attenuator design as ituses much smaller FETs. As smaller FETs havelower parasitic capacitances this technique has goodhigh frequency capability.

4.1. Circuit Design

To design all the 6 phase bits, Switched filtertopology has been used. It works b)' switching the RFsignal path between a high-pass filter and a low-passfilter, by means of two SPDT switches. For thisreason, this approach is also known as a high-pass!low-pass phase shifter. A low-pass filter consisting ofseries inductors and shunt capacitors provides phaselag (or delay) to signals passing through it. A high­pass filter consisting of series capacitors and shuntinductors provides phase lead (or advance) to signalspassing. through it. Both filters are matched forinsertion loss at the operating frequency but havedifferent insertion phases. Therefore, when the signalpath is switched between the two filters, the desiredchange in insertion phase can be achieved withoutany significant change in the insertion loss. Thecircuit diagram of the 5.625° phase bit is 'shown inFig 4.

The phase shifter circuit consists of 6 digital phasebits corresponding to differential phase shifts of5.625°, 11.25°, 2.5°, 45°, 90° & 180° cascaded inseries. This arrangement provides 64 phase statesbetween 0& 360 degrees in the steps of 5.625degrees [4,5]. The Design specification of a SPOTSwitch is given in Table 3.

(1)

(2)

OUT

R2 f--Fig 3 Switched n-attenuator

R2

R1---+-.JVV'v---~------

R I = Ro[ lOA/2 - 1]

R2 = [ I04:~-I ]

Va -

IN

where,

(3) The 6 bits are cascaded to form a complete phase,shifter on a two GaAs chips with size 4.0rnrn x~

2.35mm and 3.0 mm x 2.35mm and three phase bitsin each chip for the better yield. The 45° phase bit

(4) followed by 90°, 22.5°, 5.625°,11.25°,180° is beencascaded in series.

where,

Ro = Circuit Characteristic impedance in Ohms.

A = Attenuation value in dB.

For all bits, the switching is performed onlythrough the gate control voltages and no other bias isrequired for the operation of the attenuator.

5. EXPERIMENTAL RESULTS

5.1. Results of MMIC SPOT Switch

Figures 5 and 6 illustrates the measured frequencyvs. Insertion loss and Isolation. The maximum

TABLE 3: Design specifications of Digital Phase Shifter

The 6 bits are cascaded to form a completeattenuator on a double 3.5 mm x 2.35 rnrn GaAs chipwith 3 attcnuator bits in each for a better yield. TheI6dD switched n attenu·ator was the first element inthe unit followed by 1,2,8,0.5 and 4dB bits. The six

Insertion Loss

UO Return Loss.

Phase Error

Amplitude Error

9.0 dB (max.)

-15 dB (max.)

± 2.50 (max.)

± 0.5 dB (max.)

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

N D DODDAMANI et al: DESIGN AND IMPLEMENTATION OF SPDT SWITCH 527

~~.-{FET1 -~t--·---JFET2

...."'...'r ~_-...J

OUT

--{]

L1 ClFig 4 5.625° Phase bit

0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8-. -1 16 ,.---,--.--r---.,.-..,...-----r--.---.---,.-~....,!O;:l • I

:z. ·1.18 I1~ ·1.20 +-----------------i:; -1.22 +----....:---=......10:::--.-------------...;~ .1.24 + . :::---::::J........-==•.---- --I

.......-.i ::~ ~I-... -.. -....-... -......-.....-......-......-...---......-._-..-.......-..._---_--~-_-._-~-..~-.-....=:;.--===.._.-..."~.~..J

FREQUENCY (GHz)

Fig 5 Insertion loss vs frequency

·90

-65 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.81

~ ·70 +------------------....;1~!

Z -75 4---------~.......='=----~5 ~-- :..... -80 ___

<3 -".'~'./) -85 4-I....-L.------_------------:'1i

.•_ .•• _ _._ _ _.., - .__ _ ' _._ '''''''' 1

FREOllEtKY (GHz)

Fig 6 Isolation vs. frequency

CD' -21..:::-Vl -21VI0 -22...J--c:: -22:::;Jl-w -230:::

9-·23-

0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1 5 1.7 1 8

----0_

----------. --«----.~-----•----_._--_._-_.

FHEOllEIKY{GHz)

Fig 7 Input return loss vs. frequency

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

528 lETE JOURNAL OF RESEARCH, VolS3, No.6, November-December 2007

insertion loss measure is -1.28dB at 1.8 GHz. Theminimum isolation measured is 72 dB at 1.8 GHz.

Figures 7 and 8 illustrates the measured frequencyvs. input and output return loss. The measured inputand output return loss is better than -20dB.

The chip photograph is shown in Fig 9. The chipsize is 3.0 mm x 2.35 mm.

.5.2. Results of MMIC Digital Attenuator

Figures 10 and 11 illustrates the measuredfrequency vs. Attenuation and phase error. Theattenuator characteristics were also measured for allstates. The maximum phase error was found to bearound 2dB over all 64-states.

Figures 12 and 13 illustrates the measuredfrequency vs. input and output return loss. The

measured input and output return loss is better than-15dB.

The chip photograph is shown in Fig 14. Theoverall chip size is 7.0 mm x 2.35 mm.

5.3. Results of MMIC Digital Phase Shifter

Figures 15 & 16 illustrates the measuredfrequency vs. Phase angle and insertion loss. Thephase shift characteristics were also measured for allphase states. The maximum insertion loss is 9.4 dB,which is the worst case.

Figures 17 & 18 illustrate the measured frequencyvs. input and output return loss. The measured inputand output return loss is better than -15dB.

The chip photograph is shown in Fig 19 theoverall size is 7.0 mm x 2.35 mm

co ·200.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

-;; -21r,f'lo -21

---------J

~ -22 -------.::>I- -22 "«--.....Wex:: ·230- -'-.~-.. ~0 -23 _._-~----

FHEQUEIKY {Gill}

Fig 8 Output return loss vs. frequency

Fig 9 Layout of SPDT switch

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

N D DODDAMANI et a1: DESIGN AND IMPLEMENTATION OF SPDT SWITCII

-- 35co ---'.'.--...._.._--_. ··--··-·..·..----1 ---O.od8- • • • • • •~. 30 -- : -k-1.0d8

0 25 -2.0d8- 20~ -4.0d8~ '15 -4-8.0d8~- '10- --1t3.0d8IJJ • • • • • • • • • • !~ 5 -~.5d8

~I • • • • !

0 ! -'-2Jd8I I

0.80,0 1D 1.1 1.2 13 1.4 1.5 1.5 1.7 1B -+- 31.5dB

FRE fJUE IICY{GHz)

Fig 10 Attentuation ys. frequency

529

2.5 ----------.---------.....-j 2.0

.::;, 1.5 n::~4:~=~y:::::~~::_~UJ

~ 1.0 ~;;:;:~~~:=:::i::;;:;:::b:~g: 0.5 +-:-=--'=--~"'C'"'"'___:"r.....c_-_z_'"'""'b~___,,~

0.0 +--.,-.-~;:::t=;~~~~~~.:....{

0.80.9 '1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

fREOUEIIC'{(GHz}

Fig 11 Phase error ys. frequency

--0.5dB-4r-1.0dB-20dB-4.0d8-+-8.0dB--16.0dB-28.5dB--Q-20dB-31.5dB

_.CO 0-.:::.(I) ·5(/').;:. ·10..J=·150:~·?OI- -w0: ·25

:: ·30

0.3 :),9 i.) 1.1 1:2 1.3 1.·1 15 1.6 1.7 113• . . I

...... - ....- - -y-

. ..

FREOUE IICY(GHz)

Fig 12 Input return loss ys. frequency

---O.tdB-..-1.Qj8

2.OjB-4.0j8-+-8.OjB

-16Dd8-28.5dB··--2DdB-+-31.5dB

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

530 JETE JOURNAL OF RESEARCH, Vol 53. No.6, November-December 2007

O.80;;1.:)1.1121.31:~ 151.6'1.71.8co 0 I ITI I I I I I I ! ---O.SdB~ -5 -+- ....;1 -+-1.0dB

~ --2.0dBo -10 4-------------1

...Jz -15f!~E~~~~~~t --4.0dB

_ _ _ _ -+-8.0dB

(( -20 --16.0dB~ "'-.L--.... ---w -25 ... ----.~~It--,r__,k__,~--:; j - 28 .5dB~ -30 -t- ~~__=;--:::::;;=---*.:::..--..:::..r<::~l - 20dB, io -35 -J -+- 31 .SdB

fRE QUE II CY{GHz)

Fig 13 Output return loss vs. frequency

Fig 14 Layout of 6-Bit Digital Attenuator

, --+

... 250 ----------------,~ Iq,I I....-.!~. 200 -+-------------.;W5 150 +- e-,

-- .« 100 -t----;-:::~~~i----1w~ 50 +------,~J=_=:a:==r_--__1

~ 0 L .....I-..--I~I~I~I~~I~§lI-..I-,-I.-J,OB 0.9 1.0 1.1 1.2 13 1.4 1.5 1.6 1.7 1.8

fREOUEIICY(GHz)

Fig 15 Phase angle vs. frequency

.....5.625deJ·+-1115 de;].--22.5deg.-46d~.

-+-QOdeJ·--180~g.

-16g75~g.

-10C.875del-+-213.75 ~g.

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

N D DODDAMANI et al: DESIGN AND IMPLL\1ENTATION OF SPDT SWITCH 531

.-.£g 1a ----~----_._----.--~.~

(,0) 9B +--------~I-----

39B +-------.r-/-'------:- ~/~Q 9.4 +-----..,..-Y~L.------I-~ 92 +------------;w~ 9 +-...,..--r--r---.,r-~...--r--r--r---.,r--;

0.8 0.9 1D 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

FREOUEIICY GUZI

Fig 16 Insertions loss ys. frequency

-- 5.625 deg.1125 deg.225 deg.

--45deg.--90deg.--180deg.-16B75de~

----106875 df-+- 213.75 de{

-.~..- .,..:O::.:..:.8~O;.:.;.9::...,...;..;1D;:..,...;.:1...;..,1....;.;1.~2~1;.;;..3~1;.:..;.4T_1~.5~1.6~1.7.;..,._;_1 ...,8co 0 - 5.6:&5 deg.

-k- 1t .2:5 deg.~-10 +----------------1 -22.5~g.

3-20 +------\~~--=-=~p.r.---___i -45 ~g._ I -+- ro oog.-0: .30 -180 d~.

~ -16.875 de;}.w-40 +------------:.------!, -106275 ~g.

0: J -+-213.75 del~ ·50 ----.-..------.-------.------

fRE QUE IICYl.GHz)

Fig 17 Input return loss ys. frequency

D.O 0.9 1.0 1.1 1.2 1.J U 1.5 L& 1.7 1.0_ 0 .,....--r--r--r-r--r---r--,..--,r--r---r---,

E9 -5 +--------------1.:::-(/) -10 +-------------~~ -15 -r----~~~~~.---~~ -20 +----....-,..c:;;:--=*'-~..::;:.~---__l~ 5 ;/- ~:::>.2 i----~t'S.oCl::::~......~?C='ly'f"-----j~ -30 +-------::::>.r~~....,:~/"'-------i

, 0: -35 +--------~\I-r---"o,,:---~a-40 -i-------'l/."-------!

-45

FREQUEIIC'{{GHz)

Fig 18 Output return loss ys. frequency

--5.625 deg.-It- 11.2:5 deg.-22.~~g.

-45~g.

--ro~g.

--180deg.--16.S75deg-100.875 ~-+-213.75deQ

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014

532 IETE JOURNAL OF RESEARCH, VoIS3. No.6, November-December 2007

Fig 19 Layout of 6-Bit digital phase shifter

6. CONCLUSIONS

An L-band SPDT Switch with the insertion lossless than -1 dB and isolation more than 60 dB hasbeen realized using GaAs switch FETs.

An L-band GaAs monolithic attenuator with0.5dB, 1.0dB, 2.0dB, 4.0dB, 8.0dB, 16.0 dBattenuator bits has been made using GaAs switchFETs. A digital attenuator with 31.5dB attenuationrange in 0.5dB increments with the phase error lessthan 2.5°, input/output return loss better than 15 dBand 64 distinct states has been realized.

,An L-band GaAs monolithic phase shifter with5.625°, 11.25°,22.5°,45°,90°, 180° phase bits hasbeen made using GaAs switch FETs. A digital phaseshifter with the insertion loss less than 9.0 dB, input/output return loss better than 15 dB and 64 distinctphase states between 0° and 3600 has been realized.

ACKNOWLEDGEMENT

This work has been carried out at E-Radar Scanlaboratory of Electronics Radar Development

Establishment (LRDE), Bangalore and supported bythe Department of Electronics and Communication BV Bhoomaraddi College of Engineering andTechnology, Hubli, Karnataka.

REFERENCES

1. I D Robertson & S 'Lucyszyn, RFIC and MMIC designand technology, lET publishing and Inspec. ISBN: 0­85296-786-1 & 978-0-85296-786-7, 2001.

2. D Krafcsik. F Ali & S Bishop, Broadband. low-loss Sand6 bit digital attenuators, IEEE International MicrowaveSymposium Digest, vol 3, pp 1627-1630, 1995.

3. J Bayruns. P Wallace & N Scheinberg, A monolithicDC -1.6 GHz digital attenuator, IEEE InternationalMicrowave Symposium Digest, vol 3, pp 1295-1298.1989. .

4. Y Ayasli et ai, A monolithic X-band four bit phase ~

shifter, IEEE International Microwave SymposiumDigest. vol 82, Issue I, pp 486-488. 1982.

5. Consantine Andricos, Inder J Bahl & Edward L Griffin,C-Band 6-Bit GaAs Monolithic Phase Shifter, IEEETransactions on Electronic devices. vol 32, 12, pp 2760­2765, 1985.

Dow

nloa

ded

by [

Tuf

ts U

nive

rsity

] at

08:

52 0

7 O

ctob

er 2

014