Designing a Processor from the Ground Up to Allow

Voltage/Reliability Tradeoffs

Andrew Kahng (UCSD) Seokhyeong Kang (UCSD)

Rakesh Kumar (Illinois)John Sartori (Illinois)

Timing Errors

• Power is a first-order design constraint

• Voltage scaling can significantly reduce power

• Voltage scaling may result in timing errors

Operating Voltage

Research Questions

• How does a conventional processor behave when we fix frequency and scale down voltage?

• How can we reduce the voltage at which timing errors are observed? • Reduce power while maintaining the

same performance level

Limitation of Voltage Scaling• At some voltage, circuit breaks

down

Voltage scaling must halt after only 10% scaling.

0.0

0.1

0.2

0.3

0.4

0.5

0.50.60.70.80.91.0Voltage

Err

ors

/ C

ycle

.

Limitation of Voltage Scaling

  Error Rate (%)

Module 1.0V 0.9V 0.8V 0.7V 0.6V 0.5V

lsu_dctl 0.00 0.23 8.60 29.46 45.13 54.90

lsu_qctl1 0.00 5.94 10.85 16.99 16.56 37.53

lsu_stb_ctl 0.00 0.08 0.65 5.19 11.79 22.38

sparc_exu_div 0.00 0.15 0.23 0.35 0.49 1.10

sparc_exu_ecl 0.00 3.31 10.97 87.08 88.93 73.03

sparc_ifu_dec 0.00 0.08 0.87 7.09 15.22 20.48

sparc_ifu_errdp 0.00 0.00 0.00 0.00 0.00 9.21

sparc_ifu_fcl 0.00 10.56 22.25 50.04 55.06 56.95

spu_ctl 0.00 0.00 0.00 1.30 2.96 35.53

tlu_mmu_ctl 0.00 0.01 0.02 0.06 0.14 0.19

What problems are caused by steep error degradation?

Problems with Steep Error Degradation

Erro

r Ra

te

(lower voltage)

Maximum error rate

Power consumption

Pow

er Error rate

Vmin

Pmin Erro

r Ra

te

(lower voltage)

Maximum error rate

V’min

P’min

Voltage scaling limited in traditional designs.

• No power savings as error rate increases

Error RateError Rate Technique 2

Power consumption

PowerPTech1

Error Rate Technique 1

PTech2

Traditional design No reliability/power tradeoff

Problems with Steep Error Degradation

Why do circuits fail catastrophically?

• Reliability/power tradeoffs enabled• Allows switching between error

tolerance techniques at different voltages/error rates

Error RateError Rate Technique 2

Power consumption

Power

PTech1

Error Rate Technique 1

PTech2

Higher error rate Lower power

Problems with Steep Error Degradation

Reason for Steep Error Degradation• Critical paths are bunched up in

traditional designs.

Question…

How can we change the slack distribution to achieve a graceful

failure characteristic?

Power-optimized design:

Reclaim excess timing slack

Make slack distribution gradual by re-distributing slack between paths.

Both gradual failure and low power can be achieved.

Slack-optimized design:

Optimize critical paths

Design Objectives and Insight

Timing slack0

Zero slack after voltage scaling

0

‘wall’ of slack ‘gradual slope’ slack

Num

ber o

f pat

hs

• Optimize frequently exercised critical paths.• De-optimize rarely exercised

paths.

Positive SlackNegative Slack

Slack Re-distribution Example

0.0

-0.1

Negative SlackPositive Slack

Error Rate = 1%Error Rate = 25%

Proposed Design Flow

Estimate Error Rate at Target

Voltage

Optimize Negative Slack Paths at Target

Voltage by Resizing Cells

Error Rate>Target Rate

YESUndo

OptimizationPower >

Current PowerYES

NO

Place and Route

Choose New (Lower) Target

Voltage

NO

Error Rate>Target Rate

NO YES

Reduce Power by Resizing Non-critical

Cells (optional)

Voltage ScalingPath OptimizationArea Reduction

• Input: RTL description• Output: Gradual slack design• Objective: Minimize voltage for a

given error rate over a range of error rates

Using fixed target results in over-optimization.

Iterative optimization avoids unnecessary swaps.

Iterative Optimization

Error Rate Forecasting

CLK

BA B

FF FF

P1

P2

P3P1 P1 P1P2 P2 P3

TG(P1) = 0.3TG(P2) = 0.2TG(P3) = 0.1

Slack(P1) = posSlack(P2) = negSlack(P3) = pos ER(B) = TG(B) ∙

TG(B) = 0.6

Timing Error

TG(P2)

TG(P1) + TG(P2) + TG(P3) = 0.2

•Functional simulation•Cadence NC Verilog – Gate-level simulation

•Library characterization•Cadence SignalStorm – Synopsys Liberty generation for each voltage

•Slack Optimization•C++ with Synopsys PrimeTime interface

•ECO P&R•Cadence SOCEncounter – Placement and Routing

•Benchmark generation•Virtutech Simics – Test vector generation

Design-level Methodology

Gradual Slack Distribution

Slack optimization achieves gradual slack distribution.

Processor Module Optimization

Slack optimized design has lowest power for all error rates.

Processor Error Rate and Power

Designs with comparable error rates have much

higher power/area overheads.

Reliability/Power Tradeoff

Slack-optimized design enjoys continued power reduction as error

rate increases.

Enhancing Razor-based Design

Slack optimization extends range of voltage scaling and reduces Razor

recovery cost.

Summary and Conclusion

• Showed limitations of traditional processors w.r.t. voltage scaling• Traditional designs break down

• Presented design technique that enables voltage/reliability tradeoffs• Optimize frequently exercised critical

paths• De-optimize rarely-exercised paths

• Demonstrated significant power benefits of gradual slack design• Reduced power 29% for 2% error rate,

27% on average

Bonus Slides

Slack Optimization Techniques

• Path Optimization and Power Reduction

Erro

r Rat

e

Vmin

Pmin

(lower voltage)

Maximum error rate

Power consumption

Pow

er

Error rate

Operating point Er

ror R

ate

(lower voltage)

Maximum error rate

Power consumption

Pow

er

Error rate

Operating point

Vmin

Pmin

1. Optimize Paths

Erro

r Rat

e

(lower voltage)

Maximum error rate

Power consumption

Pow

er

Error rate

Operating point

Vmin

Pmin

2. Reduce Power

Extended Voltage Scaling

• Focus on frequently exercised negative slack paths

• Reduce error rate while minimizing cell swaps (power overhead)

Path TG Opt. Rank

A-B-C-D 0.22 1A-B-D 0.15 2A-C-D 0.05 3

Rank paths by error rate contribution.

Upsize cells in paths to increase slack.

SWAP

Power Reduction

• Downsize cells on rarely exercised paths

• Reduce leakage power while leaving error rate unaffected

SWAP

Toggle Rate ≈ 0

Check Path Slack

Error Rate Forecasting

• Error rate contribution of one FF

• Error rate of design

ALL

NEG

P

Pffff TG

TGTGER

Dff

ffD ERER

Significance of Processor Power• Power is a first-order design

constraint• Voltage scaling can significantly

reduce power

0

20

40

60

80

100

0.50.60.70.80.91.0Voltage

Pow

er S

avin

gs

(%)

.

Voltage Scaling: 50% Power Reduction: 80%

DVFS Benefit and Cost

0.00.20.40.60.81.0

0.50.60.70.80.91.0Voltage

Relative Power Relative Performance

How effective is voltage scaling when frequency is fixed?

Alternatives – Blueshift

• Goal: Optimize paths that cause errors to enable more frequency overscaling

• Techniques: PCT/OSB• Uses iterative simulation loop –

infeasible for large designs

Alternatives – Tightly Constrained SP&R

• Goal: Optimize all paths aggressively

• Technique: Traditional SP&R with aggressive target

• Some paths will not meet tight constraint, and slack distribution becomes more gradual

Insight

• Optimize frequently exercised paths at the expense of rarely exercised paths

• Optimizing frequently exercised paths enables deeper voltage scaling

• De-optimizing rarely exercised paths keeps power overhead low

Iterative Optimization Flow

Estimate Error Rate at Target

Voltage

Optimize Negative Slack Paths at Target

Voltage by Resizing Cells

Error Rate>Target Rate

YESUndo

OptimizationPower >

Current PowerYES

NO

Place and Route

Choose New (Lower) Target

Voltage

NO

Error Rate>Target Rate

NO YES

Reduce Power by Resizing Non-critical

Cells (optional)

Scale Voltage

Optimize Paths

Iterate

A New Processor Design Goal• Reshape the slack distribution so

processor fails gracefully

Timing slack0

Zero slack after voltage scaling

0

‘wall’ of slack ‘gradual slope’ slack

Num

ber

of p

aths

Moore’s Law

• Power consumption of processor node doubles every 18 months.

Power Scaling

• With current design techniques, processor power soon on par with nuclear power plant

Outline

• Background and Motivation• Insight• Power Reduction Techniques• Design Flow• Results• Summary