Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani , Royal Institute of Tech., Sweden

©스마트 파워 모빌 컴퓨팅 Lab. 1

Introduction 1. Field Programmable Gate Array are the most flexible solutions

for reconfigurable platforms. However, they do not always deliver the required performance, e.g. in base-band processing, where the trend is to use DSP processors for flexibility and very specialized ASIC for performance.

Te flexibility of FPGA comes at the cost of performance and area loss due to its fine grain architecture.

Fine grain architecture requires extensive number of reprogrammable switches for configuration. It is also difficult to estimate the final timing of the design.

Introduction 2. Telecommunication standards are too diverse to be integrated

into one platform in the current generation of base stations and handheld devices.

The current crop of telecommunication hardware is primarily based in digital signal processor systems and very specialized ASICs.

High performance DSP consumes more power than necessary due to the overhead in their inherited generic processor structure.

Most automatic synthesis and routing tools are inefficient. Moreover, the capacity of current generation of FPGA is limited. Large system requires partitioning across many FPGA chips, further increase the complications and reduce the performance.

Introduction 3. The devices available commercially are rarely optimized for

telecommunication architecture. This is in fact the reason that FPGA and FPIC remains a prototyping platform and used mainly for logic emulation.

Special reconfigurable architecture for base-band processing customized structure to minimize any overhead needed.

The architecture incorporates programmable resources and reconfigurable processing arrays into a flexible low power platform for telecommunication hardware.

Master controllers Under the normal operations conditions,

when a particular configuration is required, the master controller sends a “mode” signal down the shared control bus to the distributed controllers.

The master controller can be switched to a special programming operation for reconfiguration.

This way the flexibility of the platform is ensured because each individual module is programmable via a centralized controller.

Control Bus On this control bus, the usual

communication is the mode control signal set by the master controller.

The other use of the control bus is for updating the control configuration data on the distributed controllers.

Since this only happens during service or firmware update, configuration speed is not crucial to this operation. Hence a narrow bus is sufficient and can be implemented using serial or parallel bus protocols.

Distributed controllers It is not necessary to broadcast these data

to other modules, so each controller will store its own special configuration data and parameters in the local memory.

The local controllers also contain decoder-type firmware memory

It reads the configuration bits set by the master configuration controller and then derives the corresponding parameters from the memory and set up the module.

Shared Memory In some case, for example during

reprogramming or cross-block data processing, there is a need to share memory storage between blocks.

The distributed memory available locally on the various blocks is designed for very fast access and should be used for speed instead.

A dynamic memory management system will handle the allocation, reservation, protection, de-allocations and address translation from and between various modules.

Virtual Wire Hardware (VWH) 1. We propose to use time multiplexing on the

bus in order to reduce the number of lines needed.

This function is implemented using dedicated hardware to give maximum transparency to the communication protocol between the blocks and minimize the area overhead needed for such hardware.

This separate hardware module can also run at a clock frequency multiple times higher than the system clock, ensuring the maximum bandwidth of the data lines is being used.

Virtual Wire Hardware (VWH) 2. Using shift register, VWH will be

implemented. However, shift register requires many configuration blocks within the FPGA to implement, causing too much overhead on the system.

The data is loaded into the shift register from the local parallel bus at the same speed as the system.

The data is being shifted out sequentially into the data bus

Switch Matrices (SM) The switch matrices have the same

functions as the commercially available field programmable interconnect devices.

The SMs are embedded within the platform, there is no need for I/O pad buffering. This makes the SM much smaller than an equivalent FPID and the delay much shorter.

In addition, we have reduced the number of wires to be connected by using VWH in the communication busses

Data processing blocks 1. The internal parameters and circuit

settings of each block are very different. Since flexibility and worldwide compatibility are paramount in designing a versatile platform for telecommunication circuits, we need a programmable structure which accepts all these parameters.

FPGA uses the same fine-grain cell repeated regularly within a fixed structure. Reconfigurable connections and switches customize the data paths within the FPGA.

Data processing blocks 2. The resource needed in each block is very

similar, with different connection style. This shows a scalable block structure is more appropriate than hardware structures with repetitive fine grain cells.

A more area efficient architecture than DSP & FPGA

A customized structure that has little overheads and much in-built flexiblity

Less power required than generic structures

Higher performance and room for expansion

Data coding and Channel coding block

There are obvious structural similarities between all the popular standards used in the channel coding mechanism.

A repetitive structure with specially designed slice element and custom terminators is the most flexible solution in terms of ease of configuration and expansion.

Results 1. Custom block design is much

smaller and more power efficient than FPGA.

More advance technologies, such as LSI G12 ASIC library, can improve the performance and power of our design.

Result 2. The capacity improvements on

each physical wire by using virtual wire and special route through hardware.

As the system frequency increases, the potential improvement is lowered due to the inherent delay in the shift register and the extra hardware associated with VWH.

Result 3. The delay associated with

transmission of a simple 32 bit binary number using normal wire at the system frequency and the delay with virtual wire hardware.

Conclusion 1. The flexible dedicated telecommunication platform has many

advantages over platforms using Field Programmable Gate Array and Digital Signal Processors.

The hardware is designed to give better performance with much smaller amount of overhead than DSP, yet maintaining the same flexibility.

The hardware structures are optimized to give silicon area to support bigger and more complex telecommunication circuits over traditional FPGA and FPIC combinations.

Conclusion 2. The distributed control system, distributed memory and the

shared memory management system reduced the complexity of control system design.

The virtual wire hardware uses time multiplexing to decrease the size and the complexity of the programmable resources on the platform, conserving the chip area for other valuable logic resources.