Digital Electronics

Chapter 3

Gate-Level Minimization

Karnaugh Maps

Simplify

F =A'B'C + A'BC' + AB'C+A'BC + ABC

K-Map

Simplify

F =A'B'C + A'BC' + AB'C+A'BC + ABC

F = C + A'B

K-Map with “don’t care”Simplify

F(w,x,y,z) = Σ (1,3,7,11,15)

d(w,x,y,z) = Σ (0,2,5)

F = z (y + w' )

DeMorgan’s Picture!

Two Equivalent Representations

How Bubbles Move !

F = AB + CD

Three equivalent representations of F = AB + CD

NAND Implementation

F = xy' + x'y + z

Designing for Equivalence

Design a circuit to check if x = y

Hint: Review XOR and XNOR

XNOR will be high if x = y

Odd and Even Functions

(a) Checks for odd number of 1’s

(b) Checks for even number of 1’s

Parity Generator / Checker

Even Parity Generator Even Parity Checker

P = 1 if x,y,z have odd number of 1’s so that the four bits, x, y, z, and P have an even number of 1’s

C= 1 if there is error, that is if the four bits received have an odd number of 1’s

VHDL

Verilog Hardware Description Language

// A simple example

module my_example (A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and g1 (e,A,B);

not g2 (y,C);

or g3 (x,e,y);

endmodule

Comments on my_example

// indicates a comment line

statements are terminated with ;

endmodule has no semicolon

keywords like module, input etc. must be in lowercase

gate declarations must have the output first then the inputs separated

by commas

Circuit Diagram of my_example

That’s All Folks!