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Ph.D. DISSERTATION
High Density 3-D Stacked NAND flash Memory Structure and Trap Characterization
고집적 3차원 적층형 낸드플래시 리 조와 트랩
분석
BY
MIN-KYU JEONG
February 2014
DEPARTMENT OF ELECTRICAL ENGINEERING AND
COMPUTER SCIENCE COLLEGE OF ENGINEERING
SEOUL NATIONAL UNIVERSITY
High Density 3-D Stacked NAND flash Memory Structure and Trap Characterization
고집적 3차원 적층형 낸드플래시
리 조와 트랩 분석
지도 수 종 호
논문 공 사 논문 로 제출
2014 년 02 월
울대 대 원
전 컴퓨터공
정 민 규
정민규 공 사 논문 준
2014 년 02 월
원 : 영 준 ( )
원 : 종 호 ( )
원 : 병 ( )
원 : 계 ( )
원 : 최 우 영 ( )
i
ABSTRACT
A new 3-D stacked NAND flash memory with the cell area of 3F2/n was proposed to
achieve high-density NAND flash memory device by using common gate structure. By
adopting trench structure instead of through-hole structure, threshold voltage variation in
cells of a string can be reduced and the number of stacked control-gate electrodes in a
gate stack can be increased as a result. In the trench between adjacent control gate stacks,
gate stack, which consists of tunneling oxide/nitride storage layer/blocking oxide stack,
poly-Si bodies, backside oxide (BOX). We showed that proposed device had the
advantages of better reliability, cheaper process cost and lower variation of the threshold
voltage and program speed than the 3-D stacked NAND flash memory cells in via-hole.
To investigate the characteristics of proposed 3-D stacked NAND flash memory device,
TCAD simulation tool was used. Firstly, we studied about body coupling effect with the
bit-line voltage (VBL) and the geometry of the device. To solve the body coupling effect,
we showed the guideline of circuit operation. We investigated the scaling down limitation
of gate length and space, and optimized the geometry of proposed device. The modified
contact scheme that connects both sides channels in bottom region was proposed. To
overcome body cross-talk effect, we suggested the 3-D stacked NAND flash memory
with shield layer. The 3-D stacked NAND flash memory device with shield layer has
ii
almost same structure. The effect of shield layer with shield type and shield bias was
investigated by TCAD simulation. To implement the full array, we suggested the metal
wiring of 3-D stacked NAND flash memory with shield layer for read and program
operation. To confirm device characteristics, we fabricated proposed 3-D stacked NAND
flash memory cell strings which have 3 layers of vertically stacked CGs. Vth could be
controlled by applying a bias to the shield layer. We also showed reasonable cycling and
retention characteristics of a cell in a string and good pass-gate properties of the cell in
the bottom of the trench. In appendix section, Trap density (Dit) was extracted for the first
time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure.
We verified extracted Dit with conductance method and charge pumping method in 32 nm
floating gate (FG) NAND flash memory device. The simulation results of IBL-VCG and C-
VCG based on the Dit were conformable with the measurement data. Then we investigated
the effects of program/erase cycling stress on 1/f noise in NAND flash devices. Finally,
we extracted firstly the position of a trap generating random telegraph noise (RTN) by
considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND
flash memory cell.
Keywords: 3-D stacked NAND flash memory, trench structure, body coupling effect,
shield layer, trap characterization.
Student number: 2009-30934
iii
CONTENTS
Abstract……………………………………………………...i
Contents……………………………………………………iii
Chapter 1
Introduction……………………………………………….1
Chapter 2
3F2 3-D stacked NAND flash memory cell string in
trench
2.1 Device Structure of Proposed Flash Memory
Cell…………..........9
2.2 The Advantages of Device
iv
Structure……….................................15
2.3 Investigation of Body Cross Talk
Effect…...................................24
2.4 Device Scaling
Limitation .……………………………………...29
2.5 Modified Bottom n+ Structure with Pass
Transistor......................33
Chapter 3
3-D stacked NAND flash memory with shield layer
3.1 The Motivation of Using Shield
Layer..........................................35
3.2 Device Structure of 3-D Stacked NAND Flash Memory with
Shield Layer and
Layout.....................................................................37
3.3 The Effect of Shield Type and
v
Bias………..................................43
3.4 Device Characteristics as Body Doping Concentration and
Dopant
type…..................................................................................................4
6
3.5 Metal wiring for read and program inhibit in full
array................48
Chapter 4
Fabrication of proposed 3-D stacked NAND flash
memory with shield layer
4.1 Mask Layout and Mask
Design.....................................................55
4.2 Process Sequence for Device
Fabrication.....................................57
4.3 Device
vi
Characteristics...................................................................65
4.4 Process Suggestion of Si/SiGe SEG technology for Low
Resistance Control
Gate…..................................................................78
Conclusions…………………………………………….82
Appendix
Trap characterization in 3-D stacked NAND flash
memory
A.1
Introduction..................................................................................83
A.2 Measured Device Structure and Circuit
Scheme .........................85
A.3 Interface Trap
Characterization....................................................87
vii
A.4 RTN
Characterization...................................................................94
A.5 Characterization of Traps in Nitride Storage
Layer......................98
Bibliography……………………………………………102
Abstract in
Korean………………………………………114
1
Chapter 1
Introduction
Recently, demand for non-volatile memory have increased since digital applications
like MP3, digital camera, solid state disk(SSD) and so on using non-volatile memory
have increased in market. To satisfy this market demand, NAND flash memory based on
silicon technology and floating gate storage node has been developed to the technology
node of 1x nm generation and beyond. Cell size reduction in NAND flash memory is
required continuously to achieve cheaper cost, faster speed and higher capacity for
advanced digital applications. Due to enormous shrink of the cell size, it is getting
difficult to fabricate highly scaled NAND flash memory. As alternative technologies to
substitute NAND flash memory, new memories such as RRAM, PRAM and MRAM have
been studied [1]-[10]. However, these new generation memories still have demerits in cell
device reliability and memory density when compared with NAND flash memory based
on Si technology. The guideline for scaling down in NAND flash memory using Si
technology is shown in Fig. 1. 1 [11]-[20]. To enhance memory density without reducing
the cell size significantly, 3-D stacked NAND flash memory structures have been studied
in many groups [11]-[15].
2
Fig 1.1. 2011 ITRS road map for the design rule of NAND flash memory device.
3
To implement such stacked NAND flash memories, simply stacking the 2-D cell
strings was adopted in the stacked NAND flash technology as shown in Fig. 1.2 [11].
Hereafter we call this structure as “Simply stacked NAND flash memory”. The vertical
bit-line and stacked CGs were adopted in 3-D stacked NAND flash technology [12]-[15].
In the simply stacked NAND flash memory, since nearly the same number of process
steps is used repeatedly for each cell string layer of the stacked structure, the process cost
per bit is relatively higher than that in 3-D stacked NAND flash memory. Considering the
bit cost of device, 3-D stacked NAND flash memory structure has an advantage over the
simply stacked NAND flash memory. As a result, 3-D stacked NAND flash memory has
been considering as better candidate for high-density NAND flash memory beyond the
floating gate planar NAND flash memory structure.
In 3-D stacked NAND flash memory technology, there are two typical structures,
which are word-line and bit-line stacked NAND flash memory structures. In bit-line
stacked NAND flash memory, Si-SiGe epitaxy technology is used for crystalline channel.
However, the WL stacked NAND flash memory device have poly-Si channel. There are
two device structures which are Terabit Cell Array Transistor (TCAT) and Pipe-shaped
Bit Cost Scalable (P-BiCS) as shown in Fig 1.3 (a) and (b), respectively. Both TCAT and
P-BiCS structures have some problems due to their device structures. O/N/O gate stack
was formed in through-holes in CG stack where control-gates were stacked, and a layer of
poly-Si for thin vertical body was formed to implement vertical bit-line structure.
4
Fig 1.2. Simple stacked NAND flash memory device [11]
5
(a)
(b)
Fig 1.3. (a) Tera-bit cell array transistor (TCAT) by Samsung electronics [13],
(b) Pipe-shaped bit cost scalable (P-BiCS) NAND flash memory device by Toshiba [12].
6
However, these structures using through hole have a limitation in the number of
vertical bit cell because the holes are not vertically etched. This etch profile makes the
radius variation in vertical cell string shown as Fig. 1.4. Thus, the radius variation of cell
string makes large threshold voltage distribution in one-bit line. And through-hole size
changes significantly with position as the number of stacked control-gates increases.
When we consider the cell size in a stack, the cell size is ~6F2/n, which is very difficult to
be reduced further due to their unique structures, where n is the number of control gate
stack. Metal gate structure used in TCAT can make bad retention characteristics in an
elevated temperature operation due to the stress coming from relatively large thermal
expansion coefficient of the metal gate stack. For the P-BiCS structure, it is quite difficult
to form through-holes through in alternately stacked poly-silicon (control gate) and oxide
(isolation) layers by using etching process. Thus, we require new 3-D stacked NAND
flash string to solve the problems mentioned above.
7
Fig 1.4. The channel radius variation due to non-vertical via-hole profile
Fig 1.5. The limitation of scaling down in via-hole based NAND flash memory
0.5F
1F
0.5F
1F
0.5F
CG
body
• One cell size per layer is ~6F2
One cell area: 3F´2F=6F2
• Limitation of minimum feature size (F)
CG
50 nm
20 nm
O/N/O
50 nm
20 nm
O/N/O
Assumption : O/N/O=3/6/6 nm
8
In this work, we propose new 3-D stacked NAND flash string which has a common
gate structure to increase memory density and shield layer to suppress any interference
between bodies in a bit line. Firstly, we show how to achieve one cell area of ~4F2/n and
important features of proposed structure. Then process flow to fabricate the structure will
be explained briefly.
9
Chapter 2
3-D stacked NAND flash memory device with
common gate structure and 3F2/n area in
trench
2.1 Device structure of proposed 3-D stacked NAND flash
memory
Fig. 2.1 shows the 3-D schematic view of proposed 3-D stacked NAND flash
structure. In the trench between control-gate stacks, gate stack (contains the blocking
oxide, storage layer and blocking layer), poly-Si body and backside oxide (BOX) are
formed. The BOX is placed between two bodies and isolates these bodies. Source and
drain pads are formed on top of control gate stack. This n+ region can be easily formed
by ion implantation process. Considering etch profile of trench, this etch profile makes
channel length and width variation. This width or length variation does not affect the
10
threshold voltage variation. And the trench can be deeper than through hole. Thus, the
etched trench width is more consistent with increasing control gate stack than the etched
through-hole diameter. The body on the top of the control gate stack and the bottom of
the trench is doped n+ dopants for reasonable conduction. Top n+ region is used for
source or drain. Bottom n+ region is used for electrical conduction between adjacent
vertical bodies. One control gate can control two bodies on both gate stacks so that we
can achieve high density (< 4F2). The cell transistors have no source/drain regions and
operate by utilizing fringing field.
11
Fig. 2.1. 3-D schematic view of proposed 3-D stacked structure in trench
Active
BOX
BOX
12
The simulation device structure of proposed 3-D stacked NAND
flash memory
Fig. 2.2 (a) shows top view of our proposed structure. Here, the yellow layer and red
layer means control gate and poly-Si body, respectively. As you can see, the source and
drain pad is placed in top of the gate stack. Thus channel current flows as U-shaped. The
body, which is used for channel active region, stands vertically and is not shown on top
view. There are vertical bodies in both sides of one control gate. Also, the one gate can
control two bodies. The bodies are isolated by SiO2, which is called back side oxide. We
call this gate structure common gate structure. Because of using common gate structure
in proposed structure, the area of control gate occupies just half minimum feature size
(F) and source and drain pad occupies 2F with isolation area in device area. Thus, we
can achieve 3F2 area design.
The 2-D structure, which is used in device simulator, is shown as Fig. 2.2 (b). We
performed device simulation with Sentaurus TCAD tools to investigate a cell string with
3 layers control gates as shown in Fig. 2.2 (b). On the control gate of top and bottom
cells, the pass bias is applied for sufficient conducting. The device, which placed in the
center of control gate stack, is used cell device. To connect the left and right side
channel, the bottom region is n+ doped region. In device fabrication, we can make this
layer by only ion implantation process. And the top n+ region are used source and drain.
13
Here, the SONOS (Silicon/oxide/nitride/Silicon) gate stack is used for charge trapping
device. In SONOS device structure, top and bottom oxides are used for blocking and
tunneling oxide, respectively. In this structure, the traps in nitride are used for charge
trapping region. The trapped hole or electron makes threshold voltage shift. In this
device simulation, the thickness of O/N/O (tunneling oxide/nitride storage
layer/blocking oxide) is 3/6/6 nm. The Tb, G-G, Ls and Lg represents poly-silicon body
thickness, gate to gate length, spacer length and gate length, respectively.
14
(a) (b)
Fig. 2.2. (a) Top view of proposed 3-D stacked structure showing 3F2/n. (b) 2-D
simulation structure and geometries of proposed 3-D stacked structure.
2F
1F
1F1F 1F
3F2Cgate
Cgate
Cgate
S/DPad
BOX
Cgate
Active
O/N/O
2F
1F
1F1F 1F
3F2Cgate
Cgate
Cgate
S/DPad
BOX
Cgate
Active
O/N/O
CG CG
G-G(2F)
Pass Pass
Pass Pass
Substrate
O/N/O Tb
Lg
Ls
F
BOX
S/D(n+)
n+
15
2.2 The advantages of device structure
In the preceding section, key device structures of the proposed 3-D stacked NAND
flash memory were depicted. From now on, advantages of the proposed 3-D stacked
NAND flash memory device will be explained.
First, the advantages of the bottom n+ region in 3-D stacked NAND flash memory
are better device reliability and lower process than BiCS or P-BiCS and flash memory
device. Fig. 2 (a) shows the process sequence to connect bottom source and body in
BiCS flash memory device fabricated by Toshiba. To etch only bottom gate stack, SiN
base tunneling oxide and blocking oxide were deposited and the DHF (diluted
hydrofluoric acid) based wet chemical etch process was used. This fabrication method
made bad retention characteristics because wet chemical gave the damage to tunneling
oxide and SiN based tunneling oxide had more trap than SiO2. To overcome this oxide
damage, Toshiba developed the P-BiCS structure.
Fig. 2 (b) shows the key process sequence of P-BiCS NAND flash memory to
make pipe-shaped channel structure. In P-BiCS NAND flash memory, the tunneling
oxide quality became better but the process sequence was more complicated than BiCS
NAND flash memory. To make the pipe-shaped channel structure, the sacrificial layer
deposition and etch process were added and the cell string and SSL/DSL cell could not
be formed at the same time. These can increase the process cost.
16
In proposed 3-D stacked NAND flash memory structure; this bottom n+ region can
be form by ion implantation process to connect both sides bit-line. Thus, the bottom n+
region has the advantages in NAND flash memory reliability and process cost. Our
channel shape also gives advantage in program and erase speed variation and threshold
voltage distribution in single bit-line.
(a)
17
(b)
Fig. 2.3 (a) The process sequence to etch only bottom region (b) The Key process of P-
BiCS NANA flash memory device
The 3-D stacked NAND flash memory device (fabricated by Samsung, Toshiba and
SK hynix) adapts the gate-all-around (GAA) channel structure and nitride storage layer.
Comparing the planar with GAA SONOS NAND flash memory, the advantage of GAA
channel structure is the faster program speed than planar channel structure. Due to field
focusing effect, the electric filed at the channel surface in GAA channel structure is
18
higher than the planar structure. The field focusing effect is directly affected by channel
radius. In GAA channel NAND flash memory, the radiuses of cells in one bit-line have
variation, because the etch slope is not vertical. Thus, the program speed and threshold
voltage has variation with respect to cell position. In proposed 3-D stacked NAND flash
memory, the etch profile makes only device width and length variation. When the trench
is formed by etch process, the larger etch area guarantees the vertical etch profile. In
body etch process, the etch profile is almost same to through hole case. Thus, we should
consider only channel width variation. To compare our structure and TCAT (or P-BiCs)
which has tube channel, we performed device simulation. In our device structure, the
channel is simply flat. The geometry variation mainly comes from the channel width
variation along the path from the top to the bottom. Thus, we changed the channel width
from 20 nm to 30 nm as an example, and checked the Vth variation. Fig. 2. 4. (a) shows
the simulated device structure of planar SONOS flash memory having the width
variation. The widths of simulated structure are 25, 30 and 35 nm. Here the thickness of
the body is 20 nm. In Fig. 2. 4. (b), we checked the threshold voltage variation with IBL-
VCG characteristics as channel width change. As you can see, the variation is quite small
(less than 20 mV). However, the Vth variation with the geometry variation in the tube
structure is quite significant. In reference [16], the tube size (diameter) changes
significantly along from the top of the via to the bottom. For example, we changed the
diameter the tube from 40 nm to 60 nm at a fixed body thickness of 10 nm, and checked
the Vth variation was ~900 mV, which cannot be ignorable. In this sense, we can say our
19
structure has much smaller Vth variation which comes from the geometry variation. To
check program speed due to channel width variation in planar SONOS NAND flash
memory device, we performed the transient device simulation. Here, the geometries
used in device simulation are same with the geometries which was used to check the
threshold voltage variation. Here, the program voltage is 18V and the program times are
100us and 1ms. In both fully and non-fully program state, the threshold voltage shift
almost same in all devices with different width.
(a)
20
-3 -2 -1 0 1 2 3 410
-15
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Proposed 3-D stcked NAND Flash
W=20 nm W=25 nm W=30 nm
I BL (
A)
VCG
(V)
Initial state
Vth= - 0.372 V
(b)
-2 0 2 4 6
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
PGM(18V,100ms) W=20nm PGM(18V,100ms) W=25nm
PGM(18V,100ms) W=30nm PGM(18V,1ms) W=20nm PGM(18V,1ms) W=25nm PGM(18V,1ms) W=30nm
I D (
A)
Gate Voltage (V)
3D stcked NAND Flash
(c)
Fig. 2.4 (a) The simulated device structure for investgating threshold
votage variation (b) The threshold voltage with channel width (c) The
variation of threshold voltage shift with channel width variation.
21
22
Our device structure has advantage of device area. In terms of “U-shaped” body, our
structure is a bit similar to that of P-BiCs. However, there is a bottom cell, which can
have similar cell characteristics in our structure. And it is impossible to implement a
bottom cell between adjacent vertical bit-lines because the tube-type body in the vertical
bit-line is totally different in shape and performance from the planar-type body on the
bottom. And the cell size and scalability of our structure are also different from those of
P-BiCs.
.Fig. 2.5 compare device area of through hole structure and proposed device
structure. In the lateral direction, the length of a cell consists of 1F (body width) and
two 0.5F (isolation widths). As a result, the lateral length of a cell is 2F. In the vertical
direction, the length of a cell consists of 0.5F (a half of gate stack width) and about 1.5F
(a dimension including a half of the shield layer, isolation dielectric between the shield
layer and the body, the thickness of the body, and the gate stack which includes O/N/O
stack). Then the vertical size of the cell is ~2F. If we consider the cell area, then the
horizontal size (2F) times the vertical size (2F) becomes the cell area.
For the comparison of one cell size in Fig.2 .5, you can see clearly the difference.
In Fig. 2.5, we compared our structure and TCAT (or P-BiCs) in a minimum feature size
(F). Now we quantify the cell size by considering real size. Please see the Fig. 2. 5. for
quantitative comparison when 1F is 50 nm. Let us assume we are using 50 nm
technology. The horizontal size is 100 nm (=2F) clearly as can be expected. Let us
assume that the blocking oxide thickness is 10 nm, the nitride thickness is 6 nm, and the
23
tunneling oxide is 4 nm. The body thickness is 15 nm, the isolation oxide between the
body and the shield layer is 15 nm (which is scalable to 10 nm if the body thickness
scales down to 10 nm). Then the vertical size is also 100 nm. The total area of one cell
is 104 nm2. Since one cell area of TCAT (or PBiCs) is 6F2, the total area of one cell is
1.5´104 nm2. However, it is nearly impossible to implement a O/N/O stack of 20 nm, a
body thickness of 15 nm, and an inner oxide if any in a via hole of a diameter of 50 nm.
If we form 20 nm thick O/N/O stack inside the via hole, remaining hole size in diameter
is just 10 nm. In this 10 nm via, it is impossible to form 15 nm thick body. In this sense,
our structure is denser in cell size compared to that of P-BiCs.
24
Fig. 2.5. Comparison of one cell area when 1F=50 nm.
25
2.3. Body cross talk effect
In this section, we explain the body cross talk effect. The Fig. 2.6 shows the
coupling capacitance, which causes body cross talk effect between both side bodies. In
Fig 2.6, the bit-line voltage and ground are applied to left side (drain) pad and right side
(source) pad, respectively and this bias condition means that the cell string is under read
condition. Here, the pass voltage is applied to control gate of 4 cells in bottom and top
of gate stack, the left and right cells in center operates the read cell. In the proposed 3-D
stacked NAND flash memory, two read cells are facing each other and there is SiO2
layer (or dielectric layer) in the middle of these for isolation. Under the read condition
of left read cell, the control gate of right read cell is applied with pass voltage and this
device is under linear region of MOSFET. The channel potential of right cell follows the
ground potential, because the channel resistance is very low in this bias condition. In
opposite case, the channel potential of left cell follows bit-line voltage. The body of
proposed 3-D stacked NAND flash memory is thin to reduce effect of trap placed in
poly-Si grain boundary. As a result, the body is under the volume inversion and the
potential of body backside is almost same as the channel potential or surface potential.
This potential is coupled with the body of opposite side cell, because there is SiO2
between two cells. So, we call this potential coupling “body cross talk effect”.
26
Fig 2. 6. 2-D schematic view of proposed 3-D stacked NAND flash memory showing
the body cross-talk effect
BLSide
SSL
Substrate
BOX
VBL GND
GSL
CG CG
GNDSide
27
In Fig. 2.7, source side transistor shows more serious DIBL characteristics than
drain side transistor. Due to volume inversion, source or drain bias is coupled with
opposite site body through the body and BOX. Thus source side transistor is affected by
drain bias and drain side transistor is affected by source bias. The device structure with
thicker BOX is less affected by body cross talk effect. Here, Lg = 60 nm. Ls = 40 nm. Tsi
= 10 nm. The insert shows bias operation.
Fig. 2.8 shows IBL-VCG characteristics of the proposed structure as a parameter of
drain bias. The source side transistor is more sensitive to drain bias than drain side
transistor Here, Lg = 60 nm. Ls = 40 nm. Tsi = 10 nm.
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.510
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
BLSide
SSL
Substrate
BOX
VBL GND
GSL
CG CG
GNDSide
VBL
= 1 V
Lg=60 nm, L
s=40 nm
Tb=10 nm
Nb=1x10
17cm
-3
I BL (
A/m
m)
Control Gate Votage (V)
Tw
GND Side BL Side 80 nm 100 nm 120 nm
VBL
= 0.05 V
Fig. 2.7. IBL-VGS characteristics of the proposed structure as a parameter of G–G length.
28
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.510
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
BLSide
SSL
Substrate
BOX
VBL GND
GSL
CG CG
GNDSide
Lg=60 nm, L
s=40 nm
Tb=10 nm, N
b=1x10
17cm
-3
Tw=80 nm
I BL (
A/m
m)
Control Gate Voltage (V)
VBL
GND Side BL Side 1 V 0.7 V 0.5 V 0.2 V 0.05 V
Fig. 2.8 ID-VGS characteristics of the proposed structure as a parameter of drain bias
29
Fig. 2.9 shows off-state surface potential profiles cut along X-X’ in the inset by
exchanging BL and GND biases. Given biases are VBL=1 V, VGND=0, VPASS=4.5 V and
VCG=-1.5 V. The GND-side cell has lower potential barrier since the higher body
potential at the BL side makes the potential low. As a result, the DIBL of the GND side-
cell is much larger than that of BL-side cell as shown in Fig. 2.9.
According to this result, we can know that drain bias is applied to array with read
cell to avoid body couple effect. In circuit operation, both source and drain bias can be
applied to both ends.
0.05 0.10 0.15 0.20 0.25 0.30-0.5
0.0
0.5
1.0
1.5
Substrate
BOX
S/D(n+)
X
X`
CG
CG
CG
CG
CG
CG
CG
Surface PotentialL
g=60 nm, L
s=40 nm
Tb=10 nm, N
b=1x10
17cm
-3
VBL
=1 V, VCG
=-1.5 V, VPASS
=4.5 V
Tw=80 nm
GND side Cell BL side Cell
Po
tentia
l(V
)
Y (mm)
Drain
Source
Fig. 2.9. Surface potential profiles of proposed structure along the channel direction. In
insert, the surface potential is cut from X to X’
30
2.4 Device scaling limitation
Fig. 2.10. (a) shows IBL-VCG characteristics of the proposed structure with Lg=40, 60,
80 nm and Ls= 20, 40, 80 nm as parameters gate length and spacer length. With
decreasing Ls, the SS is increased. Long Lg gives less sensitivity to Ls variation due to
increase of gate controllability to channel.
Fig. 2.10 (b) shows on-current characteristics of proposed 3-D stacked structure
with Ls=10 to 100nm, Lg=60 mn as function of Ls. Long Ls gives decrease of on-current
-1 0 110
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
-1 0 1 -1 0 1
Ls (nm)
20 40 80
I D (
A/m
m)
Control Gate Voltage (V)
Lg=80 nmL
g=60 nmL
g=40 nm
Tw=80 nm
Tb=10 nm
O/N/O= 3/6/6 nm
Nb=1x10
17cm
-3
(a)
31
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Lg=60 nm
Tb=10 nm, N
b=1x10
17cm
-3
O/N/O=3/6/6 mnT
w=80 nm
I D (
mA
/mm
)
Control Gate Voltage (V)
Ls (nm)
10 20 30 40 60 80 100
(b)
Fig 2.10. (a) IBL-VCG characteristics of the proposed structure as parameters gate length
and spacer length, (b) On-current characteristics of the proposed structure as a
parameter spacer length. Here, Tb = 10 nm, Lg = 60 nm and G-G= 80 nm.
32
Fig. 2.11 shows IBL-VCG characteristics of the proposed structure with Ls= 40 nm as a
parameter of spacer length with log scale. With Lg increasing, SS decreases. However,
on-current decreased due to increase of channel length..
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Tb=10 nm, L
s=40 nm
Nb=1x10
17cm
-3
O/N/O = 3/6/6 nmT
w=80 nm
VBL
0.05V 1V Lg
20 nm 40 nm 60 nm 80 nm
I BL (
A/m
m)
Control Gate Voltage (V)
Fig. 2.11. IBL-VCG characteristics of the proposed structure as a parameter gate
length. Here, Tb = 10 nm, Ls = 40 nm and G-G= 80 nm.
33
The simulation result of proposed 3-D stacked NAND flash
memory
In this section, the program and erase characteristic of proposed 3-D stkaced NAND
flash memory device is investigated. To show the Vth shift with the storage charge in
nitride layer, IBL-VCG characteristic simulation was performed by TCAD simulation tool.
The injected hole and electron densities of 6x1012 cm-2 in nitride make about 1.7 V
threshold voltage shift.
-2 -1 0 1 210
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
PGM
Qnit
= -6x1012
cm-2ERS
Qnit
= 0 cm-2
DVth
=1.77 V
Tb=10 nm
Lg=60 nm, L
s=40 nm
O/N/O = 3/6/6 nmT
w=80 nm
I BL (
A/m
m)
Control Gate Voltage (V)
DVth=1.67 V
InitQnit
= 6x1012
cm-2
Fig. 2.12. IBL-VCG characteristics of the proposed structure as a parameter gate
length. Here, Tb = 10 nm, Ls = 40 nm and G-G= 80 nm.
34
2.5 Modified bottom n+ structure with pass transistor
Fig. 2.13. (b) shows IBL-VCG characteristics of the proposed structure and modified
structure. The Fig. 2.13. (a) shows modified 3-D stacked NAND flash structure. To
make this structure, n+ dopant implantation might be performed after Si trench etching
in fabrication process. Because bottom body region of modified structure is not doped
by n+ dopant, pass voltage is applied to n+ region to connect both side of channel.
The modified structure with Lg=60 and Ls=40 nm shows similar characteristics to
proposed structure with same geometry.
(a)
CG CG
G-G(2F)
Pass Pass
Pass Pass
Lg
Ls
F
BOX
S/D(n+)
Substrate
O/N/O Tb
n+
35
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510
-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Tb=10 nm
Lg=40 nm, L
s=40 nm
Nb=1x10
17cm
-3
O/N/O = 3/6/6 nmT
w=80 nm
I BL (
A/m
m)
Control Gate Voltage (V)
n+-region p-sub V
BL
0.05 V 1 V
Fig. 2.13. (a) 2-D schemetic view of 3-D stacked NAND flash
memory with bottom pass transistor (b) IBL-VCG characteristics of the
proposed structure as a parameter gate length. Here, Tb = 10 nm, Ls =
40 nm and G-G= 80 nm.
36
Chapter 3
3-D stacked NAND flash memory with shield
layer between the two bodies
3.1 The motivation of using shield layer
Fig. 3.1. (a) shows the 3-D schematic view of 3-D stacked NAND flash structure
without shield. In the trench between control-gate stacks, gate stack, poly-Si body and
backside oxide are formed. The source drain pads are formed on top of control gate
stack. Etched trench width is more consistent with increasing control gate stack than the
etched through-hole diameter. The body on the top of the control gate stack and the
bottom of the trench is doped n+ dopants for reasonable conduction. Top n+ region is
used for source or drain and bottom n+ region is used for electrical conduction between
adjacent vertical bodies. One CG can control two bodies on both gate stacks so that we
can achieve high density (< 4F2). The cell transistors have no source/drain regions and
operate by utilizing fringing field. To check basic characteristics, we adopted a cell
string with three CGs as shown in Fig. 3.1. (b), and performed simulation using
37
Sentaurus TCAD tools. The Tb, Tw, Ls and Lg represent poly-silicon body thickness,
trench width, length between CGs, and gate length, respectively. However, in this
structure, we need to exchange bit-line (BL) and ground (GND) bias depending on the
cell position that we want read due to body cross-talk.
To solve problem mentioned above, 3-D stack NAND flash structure with shield was
proposed. The shield is formed between the bodies facing each other to eliminate the
body cross-talk.
(a) (b)
Fig. 3. 1. (a) 3-D schematic view of the 3-D stacked structure without shield (b) 2-D
simulation structure and geometries of 3-D stacked structure without shield.
CG
Tw
Substrate
O/N/O Tb
Lg
Ls
F
BOX
S/D(n+)
n+
SSL
CG
CG
GSL
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
BO
X
Substrate
S/D
Pad
S/D
Pad
Body
SSL
CG
GSL
CG
CG
Tw
Substrate
O/N/O Tb
Lg
Ls
F
BOX
S/D(n+)
n+
SSL
CG
CG
GSL
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
BO
X
Substrate
S/D
Pad
S/D
Pad
Body
SSL
CG
GSL
CG
38
39
3.2 Device structure of 3-D stacked NAND flash memory with
shield layer and layout
Fig. 3.2 (a) shows 3-D schematic view of proposed 3-D stacked NAND flash
memory with shield layer. As an example, this figure shows 7 layers of CGs and one
layer for selection devices. The selection devices are represented by SSL (string
selection line) and GSL (ground selection line). In the trench between adjacent CG
stacks, gate stack, poly-Si body, backside oxide (BOX) and shield layer are formed.
Poly-Si bodies formed on the top of the CG stacks are used for bit-line(BL) contacts at
both ends of a cell string.
The number of cells in a cell string shown in Fig. 3.2. (a) is 14. If contacts for a bit-
line are formed on the pads of every other stack, the number will be 21. We can freely
control the number of cells in a cell string by controlling the number of CGs and the
contact configuration. The contact for the shield layer can also be made on the top
surface.
40
(a)
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
BL
contact
Substrate
SSL
GSL
Active
BOX
ShieldBL
contact
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
BL
contact
Substrate
SSL
GSL
Active
BOX
Shield
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
CG
BL
contact
Substrate
SSL
GSL
Active
BOX
ShieldBL
contact
41
(b)
Fig. 3. 2. (a) 3-D schematic view of proposed 3-D stacked NAND flash
memory with a shield layer between adjacent gate stacks. The structure
in this figure has 7 layers of control gates and one layer for selection
devices (SSL and GSL) as an example. (b)Top cross-sectional view
proposed 3-D stacked NAND flash memory with a shield layer showing
one cell area ~4F2.
<3F
1F
1F1F 1F
<4F2
CG
CG
CG
Bit-line contact
BOX
Shield
<3F
1F
1F1F 1F
<4F2
CG
CG
CG
Bit-line contact
BOX
Shield
42
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
O/N/O Tb
Substrate
BOXn+
TwF
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
O/N/O Tb
Substrate
BOXn+
TwF
43
(a) (b)
Fig. 3.3. (a) Cross-sectional view of the structure with the shield layer.
(b) Cross-sectional view of modified structure which has bottom n+
region in the substrate between adjacent gate stack. In our device
fabrication, we adopted two layers of control gate and one layer for
selection devices.
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
Substrate
BOX
TwF
n+
O/N/O Tb
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
Substrate
BOX
TwF
n+
O/N/O Tb
44
The shield layer in the trench suppresses any cross-talk between the bodies facing
each other which are formed on the side surfaces of adjacent CG stacks. Without the
shield layer, difference of Vths in two cells facing each other in a cell string was
significantly depending on bias at SSL and GSL. The effect of the shield layer has been
checked by using device simulator.
By adopting the shield layer, the width of the trench needs to be increased and can
be determined to be less than 3F as shown in Fig. 3.2. (b). A CG in a CG stack is
common for both cells formed on the side surface of the CG. Therefore, the cell size in a
CG stack is ~4F2/n as represented by solid line box in Fig. 3.2. (b).
In proposed structure, adjacent control-gate stacks are isolated by forming the trench.
The trench width near the bottom is generally narrower than that near the top, which
becomes a limiting factor in increasing the number of CGs in a CG stack. Such limiting
factor is more serious when we etch through-hole as in TCAT and P-BiCs.
Thus, we think our structure is more expandable compared to them. It needs to be
noted that the variation in through-hole size directly leads to Vth variation in a cell string.
However, proposed structure has no significant Vth variation with the position along the
trench because our structure has planner channel structure, although the trench width
near the bottom of the trench becomes narrow with increasing trench depth.
The body on the top of the CG stack and the bottom of the trench can be doped by n+
dopants for reasonable conduction. The n+ regions in the body formed on CG stacks are
used for the top contacts, and the n+ body region in the bottom of the trench is used for
45
electrical conduction between vertical bodies formed on the side of adjacent CG stacks.
Although the cell transistors have no S/D regions, a cell string consisting of the cells
could be worked by utilizing fringing field.
46
3.3 The effect of shield type and bias
Fig. 3.4. (a) and (b) shows DC characteristics of the proposed structures with n+
shield and p+ shield in GND-side cell and BL-side cell. The DIBL and SS characteristics
show almost same result and higher on-current is shown in GND-side cell due to low
source resistance [27]. The structure with p+ shield has higher threshold voltage due to
back bias effect [28]. In 3.4. (b), the difference of on-current is clearly shown.
-2 -1 0 1 210
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
BLSide
SSL
Substrate
BOX
VBL GND
GSL
CG CG
GNDSide
Shield
BLSide
SSL
Substrate
BOX
VBL GND
GSL
CG CG
GNDSide
Shield
p+ Shieldn+ Shield
I BL (
A/m
m)
Control Gate Voltage(V)
GND Side V
D=0.05 V
D=0.05
VD=1 V
D=1
BL Side V
D=0.05 V
D=0.05
VD=1 V
D=1
Lg=60 nm, L
s=40 nm
Tsi=10 nm, T
box=20 nm
Nb=1x10
17cm
-3
(a)
47
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.1
0.2
0.3
0.4
0.5
p+ Shieldn+ Shield
I BL (
mA
/mm
)
Control Gate Voltage(V)
Source Side V
D=0.05 V
D=0.05
VD=1 V
D=1
Drain Side V
D=0.05 V
D=0.05
VD=1 V
D=1
Lg=60 nm, L
s=40 nm
Tbox
=15 nm, Tsi=10 nm
Nb=1x10
17cm
-3
G-G : 3F (120 nm)
Fig. 3.4. (a) Log IBL-VCG and (b) linear IBL-VCG characteristics of the
proposed structures with n+ shield and p+ shield at different operation
condition. Here, Lg=60 nm, Ls=40 nm, Tb=10 nm and TBOX = 10 nm.
The insert shows bias operation.
48
Fig. 3.5 shows IBL-VCG characteristics of the structure with n+ and p+ shield as a
function of charge density in nitride (Qnit). There is no effect of shield on threshold
voltage shift [29]. Both devices show almost same Vth shift of 1.8 V with the same Qnit
of 6´1012 cm-2.
-3 -2 -1 0 1 2 3 410
-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
n+ p+ Qnit
(cm-3)
0
- 6x1012
6x1012
DVth
1.97 V
Tb=10 nm
Lg=60 nm
Ls=40 nm
TBOX
=20 nm
O/N/O:3/6/6 nm
I BL (
A/m
m)
Control Gate Voltage (V)
DVth
1.87 V
DVth
1.82 V
DVth
1.94 V
Fig. 3.5. IBL-VCG characteristics of the proposed structures with n+
and p+ shield as a parameter of Qnit. Here, Lg=60 nm, Ls=40 nm, Tb=10
nm and TBOX = 20 nm.
49
3.4 Device characteristics as body doping concentration and
dopant type
Fig. 3.6 shows threshold voltage and on-current (at VGS-Vth=1 V and VBL=1 V)
characteristics of the proposed structures with n and p-type body as parameter of body
doping concentration.
The n-type body can be used for n-channel MOSFETs because thin body thickness
makes depletion mode operation possible. In n type body, on-current is slightly higher
than p-type body due to lower channel resistance [30]-[33].
However, high body doping concentration (>1×1017 cm-3) reduce the on-current
because of carrier mobility degradation.
50
1015
1016
1017
1018
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
Lg=60 nm, L
s=40 nm
Tb=10 nm, V
DS=1 V
O/N/O=3/6/6 mnT
w=80 nm
VTH
ID(V
GS-V
TH=1 V)
p Body n Body
Body Doping (cm-3)
VT
H (
V)
0.10
0.15
0.20
0.25
0.30
0.35
0.40
ID (mA
/mm
)@V
GS -V
TH =
1 V
Fig. 3.6. Threshold voltage and on-current (at VCG-Vth=1 V and VDS=1 V)
characteristics of the proposed structures with n and p type body as parameter
of body doping concentration.
51
3.5 Metal wiring for read and program inhibit in full array
In this section, metal wiring for read and program inhibit in full array is suggested.
In the proposed 3-D stacked NAND flash device in trench, Fig. 3. 7. shows the metal
wiring design for read and program operation. The bottom select transistors (B.STr) and
top select transistors (T.STr) should be independently controlled. To reduce the area of
operation circuit, the control gates in same layers are connected. This is same as other
word-line stacked 3-D stacked NAND flash memory. In proposed device, there are
some difference. Because proposed device has common gate structure, which can
control the two side bodies, the control gates in same layer are alternatively controlled.
Fig 3.8 shows the schematic of cell array with proposed metal wiring. To perform read
and program operation in only selected cells, metal wiring has to be designed because
our device operates with common gate structure. First, bit-line pad should be connected
in common across each one. To enable the this metal wiring, bit-line or ground metal
should be given by a diagonal line. And the word-lines in top and bottom should be able
to be independently selected.
52
Fig. 3.7. Metal wiring for read and program operation in full array.
53
Fig. 3.8. The simplified schematic assuming full array.
54
Fig. 3.9 shows the bias condition of cell strings in full array. The yellow, red and
black color control gate is applied on control gate with select transistor pass bias, read
bias and off bias, respectively. Here, other word-lines are applied with pass voltage.
With this bias condition, we can read the only selected cell.
Fig. 3.9. The control gate bias condition of cell strings for read operation.
55
Fig. 3.10. (a) – (d) show the bias sequence for program operation. Because proposed
3-D stacked NAND flash memory has common gate structure, the program charge has
to be supplied from source/drain pad on the adjacent stack. Here, to implement this
program operation, we suggest the program bias operation sequence. In Fig. 3. 10. (a) of
pre-charging sequence, VCC and ground biases are alternatively applied with
source/drain pads. In Fig. 3. 10. (b), the top select cells of right stack and the bottom
select cell of second right stack are turned off to confine the electron in channel for
inhibit cell. The sequence of Fig. 3. 10 (c) connects the program cell to ground. Finally,
the program bias is applied to target word line.
(a)
56
(b)
(c)
57
(d)
Fig. 3.9. (a) – (d) the bias sequence for program operation.
58
Chapter 3
Fabrication of proposed 3-D stacked NAND
flash memory with shield layer
4.1 Mask layout and mask design
Fig 4.1 shows the mask layout for device fabrication. In device fabrication, the
number of masks is 6 layer. To show the key device characteristics, we make a device
mask for single device. The geometry of mask layout is determined for optical photo
equipment. As a result, we can simply demonstrate the proposed device using only
photo mask process. The masks are trench etch mask, active pad mask, stack1 etch mask,
stack2 etch mask, contact mask and metal mask. To independently select the control
gate stack in different layers, we used two poly-Si etch mask. The trench width is
designed under 0.6 um to form the shield structure. Here, you can see that the shield
contact is formed in same contact mask. This also shows the simple process step for
fabricating proposed 3-D stacked NAND flash memory device.
59
Fig 4.1. The mask layout for device fabrication
60
4.2 Process sequence for device fabrication
Fig. 4.2 shows key process steps. To clearly show the steps, we remove some of
top region in Figs. 4 (e) - (f). On substrate, SiO2 and Si layers are alternately formed by
chemical vapor deposition (CVD) in a reactor. Here Si layers are in-situ doped heavily
by n+ dopants. Then, single dry etching using a hard mask (step (c) forms trench.
Blocking oxide is formed by thermal oxidation or CVD, and followed by the formation
of storage node and tunneling oxide (step (d)). Then thin body is deposited and
patterned to form many strings (step (e)). Then oxide is deposited to fill the gap and
shield layer is formed as shown in Fig 4 (f).
(a) (b)
61
(c) (d)
(e) (f)
Fig. 4.2. Simplified process flow of the proposed structure with shield layer.
62
In device fabrication, we adopted two control gate stacks and one layer for selection
devices as shown in Fig. 4.3. If we increase the number of stack, the number of cells in
a string increases without increasing 2-D area, which leads to high memory capacity.
However, the bit-line current decreases with increasing the number of stack due to
increased channel resistance. The bit-line current expects to be decreased further
because the channel material is polysilicon which degrades the carrier mobility.
There are two selection devices (SSL and GSL) and 4 cells. If we count the cell in the
bottom as a cell, the number of cells in a string is 5. The n+ region shown in Fig. 4.3 (b)
can act as a CG in the bottom cell.
In Fig. 4.3, the Tb, Tw, Ls, and Lg represent poly-silicon body thickness, trench width,
length between control gates, and control gate length, respectively. In Fig. 4.3. (a), the
body near the bottom of the trench is doped heavily to guarantee reasonable electrical
conduction between the bodies formed on the side of the adjacent control gate stacks.
Fig. 4.3. (b) includes n+ region in the substrate under the trench, which acts as a control
gate as mentioned above. To form the bottom n+ region in this work, donor ions were
implanted after trench formation. If the bottom n+ region is used for only electrical
connection between both bodies, then the n+ layer can be also formed in the substrate
before forming the CG stacks. In Fig. 4.3. (b), the electrical connection between
adjacent bodies can be achieved by either of two methods: one is to apply a positive bias
to the n+ region and the other is to erase the cell formed on the bottom of the trench by
applying a negative bias to the n+ region. There are two methods to fabricate the
63
structure as shown in Fig. 4.3.
Fig. 4.3. (a) Cross-sectional view of the structure with the shield layer. (b) Cross-
sectional view of modified structure which has bottom n+ region in the substrate
between adjacent gate stack. In our device fabrication, we adopted two layers of control
gate and one layer for selection devices.
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
O/N/O Tb
Substrate
BOXn+
TwF
CG1
SSL
CG2
CG4
GSL
CG3
Lg
Ls
Sh
ield
TBOX
n+
O/N/O Tb
Substrate
BOXn+
TwF
CG1
SSL
CG2
CG4
GSL
CG3
Lg
LsS
hie
ldTBOX
n+
Substrate
BOX
TwF
n+
O/N/O Tb
CG1
SSL
CG2
CG4
GSL
CG3
Lg
LsS
hie
ldTBOX
n+
Substrate
BOX
TwF
n+
O/N/O Tb
64
In this work, we adopted the latter method. Fig. 4.4 shows cross-sectional SEM
image of fabricated device which includes the bottom n+ region shown in Fig. 4.3. (b).
In Fig. 4.4, CG stack, poly-Si body, gate stack and shield layer are successfully formed,
although the etch profile of the trench is not vertical. The Lg (thickness of poly-Si) is
~100 nm and the Ls (distance between adjacent CGs) is ~40 nm. Since 0.5 µm photo
lithography process technology was used for device fabrication, Tw and channel width
are 0.5 µm and 0.8 µm, respectively. For device fabrication, 6 masks were used. Key
fabrication steps are explained below.
Fig. 4.4. Cross-sectional SEM image of the fabricated device
65
Fig. 4.5. Top SEM image of fabricated device.
66
First, 60 nm thick oxide was grown on Si substrate in wet ambient. Then deposition
of 100 nm thick in-situ n+ doped amorphous (a) Si for a control gate was followed by
deposition of 40 nm thick TEOS oxide for isolating vertically adjacent control gates.
This stacking of a-Si and oxide was repeated two more times. After trench mask
patterning, trench etch process was performed by changing etch chamber. To remove the
trench etch damage, chemical cleaning was performed. Arsenic ions were implanted into
the Si substrate to form the bottom n+ region under the trench with a dose of 1´1015 cm-2
and an energy of 15 keV. Rapid thermal annealing (RTA) process was performed for 5 s
in N2 ambient at 1050 °C. Blocking oxide, storage nitride and tunneling oxide were
formed sequentially with thicknesses of 10 nm, 6.5 nm and 3.5 nm, respectively. Then
undoped a-Si with 20 nm thickness was deposited for the body, and annealed for 30 min
at 800 °C in N2 ambient to re-crystallize the a-Si. According to our simulation results,
the cell FET with n-type body showed better characteristics than the device with p-type
body, so the n-type body was chosen. To dope the body n-type with a concentration of
~1017 cm-3, arsenic ions were implanted into the wafers being tilted (30°) with two
rotations (0° and 180°). After forming photoresist patterns for cell-string array, chemical
dry etch process was done to achieve isotropic etch of poly-Si layer in sidewall and flat
face. For the BOX, oxide, nitride and oxide were deposited sequentially with
thicknesses of 10 nm, 15 nm and 10 nm, respectively. In Fig. 4.3. (b), there is only oxide
layer for isolating the shield and the bodies. However, in this fabrication, the O/N/O
layers were used for the isolation because the nitride layer is useful to fill the trench
67
with doped poly-Si through wet oxidation and wet etch processes. After depositing 500
nm thick in-situ n+ doped poly-Si layer to fill the trench, ~450 nm thick of the poly-Si
was etched using dry etch process. After that, poly-Si film was removed by the wet
oxidation and wet etch processes as mentioned above, resulting in the shield filled in the
trench only.
To dope the body formed on the top of the CG stack, arsenic ions were implanted with
a dose of 1´1015 cm-2 and an energy of 25 keV. Two photolithography steps were
performed to provide reasonable contacts for stacked CGs. A layer of oxide was
deposited by using high density plasma chemical vapor deposition (HDPCVD) process.
The oxide in contact holes was etched and followed by conventional metallization
process. In fabricated cell devices, Lg, Ls and Tb are 100 nm, 40 nm and 20 nm,
respectively. The channel width is 0.8 mm.
68
4.3 Device characteristics
Fig. 4.6 shows program and erase characteristics (bit-line current (IBL) versus control
gate bias (VCG)) of a fabricated SB-CAT at a fixed bit-line bias (VBL) of 1 V. Here, the
bias of the shield layer (Vshield) is 0 V. The insert shows the position of measured read
cell (CG2) and bias condition. In insert, VCG is applied to the CG of the CG2 transistor
and Vpass of 6 V is applied to the CGs of all devices except CG2. The bottom n+ region
acts as the CG of the bottom device (CG5) in this measurement.
Since two bodies share one CG, we should confirm the bias condition to guarantee
the program from only one side body in program operation. For this bias condition, Vpass
is applied to the CGs of CG1, GSL, and CG3-CG5. The SSL selection device is biased
to be turned-off, and the potential in the body on the left side of the SSL, CG1, and CG2
stack is boosted to achieve program-inhibit. Then a program bias is applied to the CG of
CG2 and electrons supplied through GSL are injected to the storage node of CG2. For
erase operation, holes should be generated by utilizing GIDL phenomenon since holes
are not supplied from substrate. A negative bias pulse is applied to the CG of GSL to
generate GIDL and generated holes move to the body of CG2 when an erase bias is
applied to the CG of CG2 [37]-[40]. For program and erase operations, 15.5 and -14.9 V
are applied to the CG for 300 ms and 100 ms, respectively. The Vth of a read cell is
69
extracted from the VCG at IBL = 10-7 A. The CG2 cell shows a threshold voltage shift
(DVth) of 1.32 V.
-2 0 2 410
-11
10-10
10-9
10-8
10-7
10-6
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
PGM:15.5V, 300 ms ERS:-14.9V, 100 ms
VBL
=1 V
Vpass
=6 V
Vshield
= 0 V
DVTH
= 1.32 V
I BL (
A)
Control Gate Voltage (V)
Fig. 4.6. IBL-VCG characteristics with program and erase of a fabricated
cell-string. The insert shows bias condition for each control gate. For
the program and erase of CG2, 15.5 V for 300 µs and -14.9 V for 500
ms are applied to the control gate, respectively.
70
71
Fig. 4.7 shows IBL-VCG characteristics of a fabricated our SB-CAT by changing the
bottom CG bias. When the bottom CG bias is -1 V, the bottom cell is turned off,
resulting in quite small current flow (~10-11 A). If the bottom CG bias is larger than Vth
of the bottom cell, IBL starts to flow as a consequence of contact of both sides channel.
As the bottom CG bias increases, IBL increases due to reduction of the channel
resistance of the bottom cell. From this characteristic, we can confirm that the bottom
cell provides reasonable conduction between left and right vertical bodies. Note the
bottom cell can be operated as a cell in the same cell-string as well as a pass cell.
-2 -1 0 1 2 3 410
-12
10-11
10-10
10-9
10-8
10-7
10-6
VBL
= 1 V
Vpass
= 6 V
Vshield
= 0 V
Bottom n+ region bias
-1 V 1 V 4 V 6 V
I BL (
A)
Control Gate Voltage (V)
Fig. 4.7. IBL-VCG characteristics of a fabricated cell-string as a parameter
of the bottom CG (n+ region) bias. Here the bottom CG bias is from -1 V
to 6 V, and VBL, Vpass and Vshield are applied 1 V, 6 V, and 0 V, respectively.
72
Fig. 4.8. (a) IBL-VCG characteristics of a fabricated cell-string with shield biases (Vshield)
of -2, 0 and 2 V as a parameter. As the Vshield increases, Vth decreases and IBL increase
and, because increasing Vshield decreases the potential barrier of back channel. For a 2 V
of Vshield, subthreshold swing (SS) degrades significantly since Vshield affects appreciably
the channel conductance. Fig. 4.8. (b) shows Vth behavior as a parameter of three
different Vshields in program and erase states. The Vth behaviors with Vshield are nearly the
same in program and erase states. In our structure, the Vshield of 1 V changes Vth by 0.7 V.
Note that it is also possible to control cell Vth by programming (or erasing) back O/N/O
stack between the body and the shield electrode. By utilizing this functionality, we can
control Vth distribution of cell-strings in the bit-line direction.
-2 0 2 410
-12
10-11
10-10
10-9
10-8
10-7
10-6
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
I BL (
A)
Control Gate Voltage (V)
Shield Voltage -2 V 0 V 2 V
VBL
=1 V
VPASS
=6 V
(a)
73
-0.50 -0.25 0.00 0.25 0.50
0.5
1.0
1.5
2.0
2.5
3.0 PGM:15.5V, 300 ms ERS:-14.9V, 100 ms DV
th=1.324 V
DVth=1.323 V
Vth (
V)@
I BL=
0.1
mA
Shield Bias (V)
DVth=1.339 V
(b)
Fig. 4.8. (a) IBL-VCG characteristics of a fabricated cell-string with
Vshield=-2, 0 and 1 V as a parameter. (b) Vth behavior with the bias applied
to the shield layer in program and erase states. For program and erase of
the CG2 cell, 15.5 V for 300 µs and -14.9 V for 500 ms are applied to the
control gate, respectively.
74
Fig. 4.9 shows IBL-VCG characteristics of fabricated our SB-CAT as a parameter of
Vpass from 4 V to 6V. Here, pass gates are SSL, GSL, CG1, and CG3-CG5. Applied Vpass
is enough to fully turn on the pass cells. For the Vpass, the Vth of the cell string is
determined by CG2. Higher pass bias induces higher carrier density in the channel of
pass cells, resulting in IBL increase.
-4 -2 0 2 4
0.0
0.3
0.6
0.9
1.2
1.5
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
Substrate
VBL GND
VShield
CG1
SSL GSL
CG5n+
CG2
CG4
CG3
Shield
VBL
=1 V
Vshield
= 0 V
Pass Gate Voltage 4 V 5 V 6 V 7 V
I BL (
mA
)
Control Gate Voltage (V)
Fig. 4.9. IBL-VCG characteristics of a fabricated cell-string as a parameter
of pass bias. The pass bias was applied to the CGs of remaining cells
except CG2 in a cell-string. The pass bias changes from 4 V to 7 V, and
VBL and Vshield are fixed at 1 and 0 V, respectively.
75
The Fig. 4.10 shows retention characteristic of a cell in 4-cell string. No serious
charge loss is detected up to 104 s. The Vth for erase state is nearly constant over time,
but the Vth for program states decreases. The ΔVth (1.46 V) at the initial time was
decreased to 0.84 V after 10 years.
100
102
104
106
108
0.5
1.0
1.5
2.0
2.5
3.0
(10 year)
PGM:15.5V, 300 ms ERS:-14.9V, 100 ms
DVth = 0.84 VDV
th = 1.24 V
Vth (
V)@
I BL=
0.1
mA
Retention time(sec)
DVth = 1.46 V
Fig. 4.10. Retention characteristic of a cell in a cell-string. The DVth after
10 years is 0.84 V.
76
Fig. 4.11. shows endurance characteristic of a cell in 4-cell string. We can observe
similar Vth behavior with P/E cycling for program and erase states. Although Vths for
program and erase states are increased, the increase is less than 0.3 V at 5×103 P/E
cycles. The increase of the Vth with the P/E cycles is attributed to increasing interface
trap between tunneling oxide and channel.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
101
PGM:15.5V, 300 ms ERS:-14.9V, 100 ms
DVth = 1.76 V
Intial 104
103
Vth (
V)
P/E cycling #
102
DVth = 1.83 V
Fig. 4.11. Endurance characteristic of a cell in a cell-string. The Vths in
program and erase states are increased slightly with cycles up to 1k, and
then saturated while keeping nearly the same DVth.
77
In Fig. 4.12, shown is measured pass disturbance characteristic of our SB-CAT.
Each Vpass was given for 1 ms. Our SB-CAT shows nearly constant Vth for the Vpass up to
9 V, which is reasonable when compared with that of conventional 51 nm NAND flash
memory. We also checked the program disturbance in our SB-CAT using device
simulation. A inhibit cell under a program bias of 17 for 100 ms showed Vth shift less
than 50 mV.
2 3 4 5 6 7 8 9 10 11 12 13 14
0.5
1.0
1.5
2.0
Vth (
V)
Vpass
(V)
tpass
= 1 msec
Fig. 4.12. Pass disturbance characteristics. Our SB-CAT shows nearly
constant Vth at given Vpass biases up to 9 V. Each Vpass was given for 1 ms.
78
79
We also fabricated the 3-D stacked NAND flash memory with bottom pass transistor.
In Fig. 4.13, the device structure of 3-D stacked NANA flash memory with bottom pass
transistor. In Fig. 4.14, we checked that main device structures were well formed.
Fig. 4.13. 2-D cross sectional view of fabricated 3-D stacked NAND
flash memory with bottom pass transistor
80
Fig. 4.14. TEM image of fabricated 3-D stacked NAND flash memory
with bottom pass transistor
Shield
SSL
CG1
CG2 CG3
CG4
GSL
Body
81
In Fig. 4. 15, the I-V characteristics of each cell in gate stack were investigated. Due
to different doping profile in each layer, the threshold voltage is different in each layer.
And high body doping concentration, we applied negative voltage to shield.
-6 -4 -2 0 2 410
-12
10-11
10-10
10-9
10-8
10-7
10-6 CG2(CG3)
CG1(CG4) SSL(GSL)
I BL (
A)
Control Gate Voltage (V)
Lg= 80 nm, L
s=40 nm
W= 800 nmV
BL=1V, V
pass=6V,
Vshield
=-4V
Fig. 4.15. IBL-VCG characteristics of proposed 3-D stacked NAND flash
memory device with bottom pass transistor.
82
In Fig. 4. 16, the program characteristics of 3-D staked NANA flash memory device
with bottom transistor was measured. In the program condition of Vpgm=16 V and
tpgm=0.3 msec, the threshold voltage shifts 2.4 V
-4 -2 0 2 410
-12
10-11
10-10
10-9
10-8
10-7
10-6
Fresh Program
I BL (
A)
VCG
(V)
VBL
= 1 V, Vpass
= 6 V, Vshield
= -4 V
VPGM
= 17 V, TPGM
= 300 msec
DVth = 2.4 V
Fig. 4. 16. Program characteristics of 3-D stacked NANA flash
memory device with bottom pass transistor.
83
4.4 Process suggestion of Si/SiGe Technology for low resistance
control gate
In this section, we suggest the process sequence based on the Si/SiGe selective
epitaxial layer growth (SEG) process technology. In this fabrication method, the single
crystalline n+ doped Si could be used for the word line. Because the mobility of
crystalline-Si is higher than poly-Si, higher device speed could be achieved than device
with poly-Si gate [34]-[36]. The Fig 4.17 shows the process sequence of Si/SiGe SEG
based process technology.
(a)
84
(b)
(c)
85
(d)
Fig 4.17. The process sequence of single crystalline Si gate based on
Si/SiGe SEG process technology
86
Conclusion
We have investigated characteristics of proposed 3-D stacked NAND flash cell string
through extensive device simulation. It was verified that the shield layer formed in the
trench between adjacent gate-stacks could suppress completely the cross talk between
the bodies facing each other. By controlling the work-function and/or bias of the shield
layer, we could control cell VTH. Effect of body doping was investigated for both n- and
p-type bodies. Reasonable n-type body doping was ~1×1017 cm-3 under the condition
that the body is fully depleted. For p-type body, the body doping needs to be as low as
possible. The oxide thickness between the body and the shield layer was optimized to be
~20 nm in terms of subthreshold swing and drain-induced-barrier-lowering. We have
proposed a new 3-D stacked NAND flash memory structure which was named SB-CAT
and explained key features of the structure. By using common control-gate and shield
layer, the cell area of ~4F2/n in a stack is guaranteed. A fabricated cell-string that
implemented with 3-layers of electrodes includes two selection devices (SSL and GSL)
and four cells. By adopting trench for isolating adjacent stacks, the stacking of
electrodes is more expandable compared to conventional through-hole type structure.
We confirmed that control-gate stack, poly-Si body, gate stack and shield layer were
successfully formed through the SEM image. Fabricated cell string showed reasonable
87
operation in terms of Vth shift, passing capability of pass cells, retention (0.84 V after 10
years) and cycling (ΔVth > 1.5 at 5×103 P/E cycles). It was also confirmed that the cell in
the bottom of the trench worked well so that the vertical bodies on both vertical surface
could be connected successfully by turning on the bottom cell. By controlling the bias
of the shield in the trench, we could control the cell ΔVth for both program and erase
states.
88
Appendix
A.1 Introduction
As a promising way to increase memory capacity, 3-D stacked NAND flash
technology using vertical bit line string has been reported [21],[25]. In the reported
structures, tube-type poly-Si body has been adopted. RTN and LFN can fluctuate
significantly the read current [41]-[45], which generates threshold voltage fluctuation
(DVth) and a read error. Because the poly-Si body has many grain boundaries that
include many traps, it is expected that current fluctuation occurs more seriously in 3-D
stacked NAND flash memory with the poly-Si body. Therefore, it is required to
understand the behavior of RTN and LFN of the poly-Si body 3-D stacked NAND flash
memory. However there has been no report on the noise properties in 3-D stacked
NAND flash memory. In this paper, we report for the first time the noise properties in
sub-100 nm 3-D stacked NAND flash memory. In the reported structures, tube-type poly-Si
body has been adopted. Because the traps of grain boundary in poly-Si body induce high
leakage, degradation of the subthreshold swing (SS) and the mobility [46]-[50], the traps
should be characterized. Since RTN can fluctuate significantly the read current, it is
89
required to investigate the RTN from the cells of 3-D stacked NAND flash memory with
tube-type poly Si body. In previous study, RTN characteristics with control gate bias,
bit-line bias and pass bias were observed. However there has been no report on the
characterization of traps due to poly-Si grain boundary and characterization of RTN in
the 3-D stacked devices.
90
A.2 Measured device structure and circuit
configuration
The 3-D stacked NAND flash memory was fabricated at SK hynix and has thin tube-
type poly-Si body, gate dielectric stack including SiN layer, and virtual source/drain.
Cell string is similar to that of p-BiCS structure. Gate length (Lg), space between
vertical word-lines (WL) and tube diameter are less than 100 nm shown in Fig A.2. 1.
To obtain sufficient capacitance and conductance for measurement, we used multi-BL
and tied WL structure shown in Fig. A.2. 2 where DSL and SSL were biased with a pass
voltage.
Fig A. 2. 1. Device structure for measurement
91
Fig A. 2. 2. Schematic of bit-line cell transistors connected in parallel
for conductance and capacitance measurement.
DSL
WL[n]
BL1
SSL
WL[0]
WL[1]
DWL
DWL
BL2 BLn
CSL
92
A.3 Interface trap characterization
To characterize density of the traps, the capacitance and conductance measurements
in the frequency range from 100 Hz to 1 MHz were performed in the 3-D stacked
NAND flash memory and 32 nm FG NAND flash memory [51]-[55]. Fig. A. 3. 1. (a)
explains that channel electrons can interact with deeper traps in both oxide and poly-Si
body at low frequency than high frequency. Thus, it could be assumed that the extracted
trap density at low frequency contains the bulk traps. Fig. A. 3. 2. (b) shows the
capacitance model considering trap-state in tube-type body. The Ctrap depends on
significantly the frequency (f). Cdep is virtual grounded and becomes ignorable when
inverted
93
Fig. A. 3. 1. (a) Energy band diagram showing electron interacting
with traps at low and high frequencies and (b) equivalent capacitance
model considering interface and bulk traps.
94
Figs. A. 3. 2 shows measured capacitance of 32 nm FG NAND flash memory
devices as a parameter of frequency in fresh. At a lower control gate bias than the
threshold voltage, low frequency capacitance starts to increase and then saturated
around threshold voltage, because traps in deep states need more time to interact with
channel electrons than traps near conduction band (Ec). Fig. A. 3. 3 shows measured
capacitance of 3-D stacked NAND flash memory devices as a parameter of frequency in
fresh. We can observe clearly humps of C-V curves at control gate voltage below
threshold voltage when the frequency is low, because more traps than those in 32 nm
NAND flash memory devices are distributed inside the poly-Si body near the interface
and respond well to the slowly changed gate signal. At high frequency, the hump was
disappeared.
Fig. A.3.4 shows parallel conductance (Gp/ω) related with Dit versus frequency at
different VCGs in 32 nm FG NAND flash memory. From measured Gp/ω versus
frequency, the Dit and trap time constant (τit) related with position of Ec-ET can be
extracted using equation (1) and (2).
( )
2
22 2
p m ox
m ox m
G G C
G C C
w
w w=
+ - (1)
( )2
ln 12
p itit
it
G qDwt
w wté ù= +ë û (1)
95
Extracted Dit for program or erase state of the devices increases as Ec-ET decreases.
Extracted Dit in 32 nm FG NAND flash memory is 2~5×1011cm-2eV-1 in the Ec-ET of
0.3~0.52 eV.
Fig. A.3.5 shows Gp/ω versus frequency at different VCGs in 3-D stacked NAND
flash memory cells. Extracted Dits versus Ec-ET are shown in Fig. A. 3. 6. Extracted Dit
profiles look like concave in the Ec-ET of 0.15~0.35 eV, from which we can infer that
the Dit increases as close to Ec and also increases as energy decreases. The Dit extracted
from fresh devices changes within 1.5~2×1012 cm-2eV-1 for the energy range, which is
higher than that of 32 nm FG flash memory devices. After 600 P/E cycling stress, the Dit
is increased to 2~3×1012 cm-2eV-1.
Using the Dit in fresh state, we extended Dit profile in sub-bandgap represented by
dash-dot line shown in the inset of Fig. A. 3. 7 (a). Using this profile, we could obtain
good agreement between measured and simulated IBL-VCG. Simulated C-VCG curves in
Fig A. 3. 7 (b).
96
-3 -2 -1
10
20
30
40
50
-1 0 1 2
VTH
@Program@Erase
Cap
acit
an
ce (
pF
)
Control Gate Voltage (V)
VTH
102 Hz
103 Hz
104 Hz
105 Hz
@32nm FG, Fresh
Fig. A. 3. 2. Measured C-VCG as a parameter of frequency in 32 nm FG
NAND flash memory device without P/E cycling stress.
-2 -1 0
0
40
80
120
160
200
2 3 4
VTH
@Program
Control Gate Voltage (V)
Cap
acit
an
ce (
pF
)
10 Hz
103 Hz
104 Hz
105 Hz
@Erase
@3D stack, Fresh
VTH
Fig. A. 3. 3. Measured C-VCG as a parameter of frequency in 3-D
stacked NAND flash memory device without P/E cycling stress.
97
102
103
104
105
106
0
10
20
30
40
50
60
102
103
104
105
106
@32nm FG, Fresh
Gp/w
(n
F/c
m2)
@Erased cells
VCG
= -2.975~ -2.3 V
Frequency (Hz)
@Programmed cells
VCG
= 2.1~ 2.65 V
Fig. A. 3. 4. Parallel conductance (Gp/ω) versus frequency at different
VCGs in 32 nm FG NAND flash memory.
102
103
104
105
106
0
50
100
150
200
102
103
104
105
106
@3D stack, Fresh
Gp/w
(n
F/c
m2)
@Erased cells
VCG
= -2.3~ -1.2 V
Frequency (Hz)
@Programmed cells
VCG
= 1.7~ 2.8 V
Fig. A. 3. 5 Measured Gp/ω (parallel conductance) versus frequency at
different VCGs in 3-D stacked NAND flash memory without cycling.
98
2
3
0.4 0.3 0.2 0.1
1
2
Fresh 600th cycling
@3D stack
@Erased cells
@Programmed cells
Dit (
10
12c
m-2eV
-1)
EC-E
T (eV)
Fig. A. 3. 6. Extracted density of trap-state (Dit) in 3-D stacked NAND
flash memory device without and with 600 P/E cycling stress.
0 1 2 310
-6
10-5
10-4
10-3
10-2
10-1
100
0 1 2 3
8
12
16
20
24(b)
Bit
-lin
e C
urr
en
t (A
.U.)
Control Gate Voltage (V)
Measurement
Simulation
(a)
0.4 0.2
2
4
6
8
10
Dit (
10
12cm
-2eV
-1)
Ec-E
T (eV)
Extracted Dit
Cap
acita
nce (a
F)W/ trap
102 Hz
105 Hz
W/O trap
102 Hz
105 Hz
Fig. A. 3. 7. (a) Measured and simulated IBL-VCG curves and (b)
simulated C-VCG with extracted Dit shown in the inset of Fig. (a).
99
A.4 RTN characterization of 3-D stacked
NANA flash memory
Fig. A. 4. 1 shows an example of measured RTN with VCG. As VCG increases, capture
time (τc) becomes short. To extract trap depth (xT) and position (yT) along channel length
of a trap responsible for RTN, equation (3) was derived considering cylindrical
coordinate and pass cell resistance [56].
0 0
1ln ( ) ( ) ( )c
Cox T s s C C Fp s C
e B
E E q V V E E V qVk T
tj y
té ù= - - - + + + - - + +ë û
1 2 30
1 2 2 3 3 11
1
ln 1
( )
ln 1
T
di digs FB p s s C
B di di di di di didi
x
R C CqV V V V
k T C C C C C CT
R
y y- -
- - - - - --
æ öæ ö+ç ÷ç ÷
æ öè øç ÷- - - - - -ç ÷ç ÷ + +æ ö è ø+ç ÷ç ÷ç ÷è øè ø
(3)
Since it is very difficult to solve the channel potential in the tube-type body, we
extracted the potential from measured activation energy (Ea=Ec-EF) which was obtained
from IBL-VCG curves with temperature as shown in Fig. A. 4. 2. By solving (5) with the
ln(τc/τe) shown in Fig. A. 4. 3 and parameters considering pass cell resistance in forward
and reverse readings, xT and yT are extracted to 0.35 nm from the surface and 0.95Lg
from the source, respectively. The RTN shows more sensitive change with bit-line bias
in forward reading than reverse reading as shown in Fig. A. 4. 4, which verifies that yT
is located near drain side.
100
70
80
60
70
60
70
0.0 0.1 0.2
50
60
I BL (
nA
)
VCG
=-1.3 V
VCG
=-1.25 V
VCG
=-1.35 V
Time (sec)
VCG
=-1.4 V
Fig. A. 4. 1. (a) IBL RTN waveform with VCG. The VCGs are -1.4, -1.35,
-1.3 and -1.25 V in the measurement.
Fig. A. 4. 2. Extracted activation energy with respect to VCG. The insert
shows current change with temperature and the red dashed lines
represents linear fitting.
0.0 0.5 1.0 1.5 2.00.0
0.1
0.2
0.3
0.4
32 34 36 38-18
-16
-14
-12
-10
ln(I
BL)
(A)
1/kT (eV-1)
Ea (
eV
)
Control Gate Voltage (V)
3-D stacked NAND flash
101
Fig. A. 4. 3. Ratio (ln(τc/τe)) of capture time (τc) and emission time (τe)
versus VCG with forward and reverse reading condition. The dashed
lines represent linear fitting. The insert visualized the trap position in a
cell.
-1 .40 -1 .35 -1 .30 -1 .25
-1
0
1
2
3
4
5
Forw ard : -15 .47 R everse : -13 .26
S lope
ln(t
c/t
e)
C ontro l G ate V o ltage (V )
SiO2Poly-SiSiO2
yT
xT
BLCSLPass cells Pass cells
xT = 0.34 nm, yT= 0.95Lg from source
102
Fig. A. 4. 4. DIBL and te-tc behavior with VBL (0.2~0.4 V) at (a)
forward and (b) reverse
0.10 0.110.0
0.2
0.4
0.6
0.8
1.0
0.14 0.16 0.18 0.20
Forward ReadingV
BL=0.4 VV
BL=0.3 V
Co
un
t N
um
be
r
Bit-line Current (A.U.)
VBL
=0.2 V
(a)
0.10 0.120.0
0.2
0.4
0.6
0.8
1.0
0.14 0.16 0.18 0.20 0.22(b)
Reverse Reading
Co
un
t N
um
ber
Bit-line Current (A.U.)
VBL
=0.2 V VBL
=0.3 V VBL
=0.4 V
103
A.5 Characterization of Traps in Nitride
Storage Layer
To extract the Nt with respect to trap energy level (EC-ET) in 3-D stacked NAND
flash memory, retention characteristics were measured with different temperatures (T).
In programmed cells, the dominant mechanisms of electron loss are represented by
schematic energy band diagram in Fig. A. 5. 1. The electron trap activation energy lies
closer to the conduction band edge in the nitride layer than the activation energy for
hole traps to the edge of the valence band in the nitride layer. As a result, the electron
loss of the programmed cells is much more significant compared to the hole loss of
erased cells, as the T increases to ~150°C and beyond, as shown in Fig. A. 5. 2 [57]-[60].
Based on the equation explaining charge loss during retention at high T in
Cartesian coordinate, we derived an equation to include geometrical effect in cylindrical
coordinate. Assuming a spatially uniform Nt throughout the nitride, by differentiating
equation (4) with respect to time, we can obtain equation (5) which gives ΔVth. EC-Et
can be calculated by using equations (6) and (7).
104
TAln ln ( , , ) dnit
tox TA
Rt nit t blk
thR E
nit blk nit
qN R qN RV r E t r rdE
r Rr
e e
é ùD = - + ´ ×ê ú
ë ûò ò (4)
( ) *
2 2 2th nit nit blktox nit tox
nit tox blk nit
22.3 1ln 1 ln ( )
log t 2 2B
TA
V R Rk TR R R g E
R R
e
e e
é ùæ ö¶D= - - + - +ê úç ÷
¶ è øë û (5)
( )*
2 2
TAln 2.3 log( )B BE k T AT t k T AT t= = (6)
3 2*n,e BB
n * 2n,e
222
m kkA
m h
ps
é ù= ê ú
ë û (7)
The extracted Nts with respect to EC-Et are shown in Fig. A. 5. 3. The Nts versus EC-
Et show similar profile with different Ts (180 and 200 °C) and have a peak Nt of 1×1019
cm-3eV-1 at the same EC-Et.
105
Fig. A. 5.1. Schematic energy band diagram of a programmed cell,
showing dominant charge (electron) loss mechanism in retention
model.
Fig. A. 5. 2. Retention characteristics in P and E states with various
temperatures. The result in P state only shows significant temperature
Tunneling oxide
Gate Blockinglayer
Nitride Poly channel
Thermal excitation
Trap-to bandtunnelingETA
100
101
102
103
104
All temperatures
Temperature
Vth
(A
. U
.)
25 °C 80 °C 150 °C 200 °C
@ Program
@ Erase
Time (sec)
106
dependency.
1.0 0.9 0.8 0.70
2
4
6
8
10
T=180 °C (Fitting)
T=200 °C (Fitting)
Nt (
10
18c
m-3e
V-1)
EC-E
T (eV)
T=180 °C (Measure)
T=200 °C (Measure)
Fig. A. 5. 3. Extracted nitride trap density (Nt) with respect to trap
energy level (EC-ET) at 180 and 200 °C in 3-D stacked NAND flash
memory device. The inset shows measurement scheme.
DSL
WL[n-1]
BL1
SSL
WL[0]
WL[read]
BL2 BL3
CSL
WL[1]
WL[n]
107
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재 플래시 모리는 폰, MP3 플 이어 등 이동식 장
매체 그 용 분야 시장 규모가 차 어 가고 있다. 이러한
장 매체 용 해 는 고집 , 고용량 모리가 필요하다. 특히,
플래시 모리는 특 과 DRAM 보다 우 한 집 도
인해 트 Density 증가 트 Cost 감소에 리하며, 용량 장
매체 써 그 요가 증하므 집 도 향상이 필 이라 할 있다.
하지만 존에 사용 구조 플래시 모리가 scaling down이 에 라
공 용이 증가하고 신뢰 이 나 지는 등 여러가지 이
생하게 다. 이 같 해결하 해 재 플 게이트
태 낸드플래시 모리 구조는 한계에 다다르게 었고, 라 욱
집 도를 높이 해 3차원 층 소자가 개 이 었다.
재 개 3차원 소자는 원 태 채 가지고 있 에,
소자 집 도를 높이는데 한이 생 게 다. 라 이 같 한계를
극복하 해 본 논 에 는 트랜치를 고 그 안에 시키는 새 운
태 3차원 소자를 안하 다.
1, 2 장에 는 새 운 태 3차원 소자가 개 연구 경
소개하고, 소자 특 시뮬 이 통해 알아보았다. 본 연구에 안한
소자는 트라인 면 이 3F2 이하이다. 하지만 이 소자에 는 구조 인
이 인해 생하는 마주보는 사이 간 효과가 생하게 고, 이
121
를 해결하 해 쉴드가 삽입 새 운 태 3차원 소자를 다시
안하게 다. 3장에 는 앞에 언 한 쉴드가 삽입 새 운 태 3차원
소자에 해 명 하고 삽입 쉴드 조건에 른 소자 특 살펴
보았다. 그리고 새 운 태 3차원 구조에 합한 리드 법과 프 그램
법에 해 안하 다. 마지막 4장에 는 안 소자를 직
작하여 그 특 알아보았다. 안 3차원 소자를 측 통해 알아 본
결과 매우 잘 동작하고 신뢰 측면에 도 가 없 인하 다.
주요어: 3차원 낸드플래시 모리, 트랜치 구조, 쉴드, 하드랩 낸드플래시
모리, 간 효과
학 번: 2009-30934
