ĐỒ ÁN KỸ THUẬT LẬP TRÌNH

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N K THUT LP TRNHMC LCM u Chng I.I.1 : I.2 : I.3 :

: Mclc, li ni u, biTNG QUAN V ARM LPC2103. GII THIU TNG QUAN V ARM ARM CORTEX V ARMv7 GII THIU TNG QUAN V ARM CU TRC V B NH V CHC NNG PIN LPC 2103

tr.1 tr.2 tr. tr. tr. tr.6 tr.7 tr.8 tr.8 tr.9 tr.10 tr.13 tr.19 tr. tr. tr. tr. tr. tr.23 tr.27 tr.37

Chng II.II.1 II.2 II.3 II.4 II.5 II.6

PINSEL0 v PINSEL IOPIN IODIR IOSET/ IOCLR CU TRC CC PIN LPC2103 CC CHC NNG PORT 0 PLL Control Register (PLL0CON & PLL1CON)

Chng III.III.1 III.2 III.3 III.4 III.5

PLLCON PLL Status Register (PLL0STAT & PLL1STAT): PLL Feed Register (PLL0FEED & PLL1FEED) Pulse Width Modulator (PWM): PWM CHN PHN MM LP TRNH CHO CHP THIT K PHN CNG LPC 2103

Chng IV. Chng V.

Chng VI. Kt lun v ti liu tham kho.

_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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li ni uHin nay, cc nghnh kinh t ni chung v c kh ni ring i hi k s c kh v cc cn b k thut c o to ra phi c kin thc su rng, ng thi phi bit vn dng nhng kin thc gii quyt nhng vn thng gp trong sn xut v s dng my mc. Cng vi s pht trin ngy cng cao ca khoa hc k thut th nhng dng chp mi c ra i vi nhng tnh nng vt tri, nhm p ng nhng yu cu ngy cng cao ca x hi. Mc tiu ca mn hc l gip sinh vin cng c kin thc ca cc mn hc nh: K thut lp trnh, K thut in, Lp trnh C cho vi iu khin, . Ngoi ra cn gip sinh vin tm hiu thm v mt dng chp mi(chp 32 bit) vi nhng im mnh ni tri c th trong tng lai khng xa s thay th nhng dng chp khc bng nhng ng dung, li ch v tc vt tri m n mang li. Qua sing vin nm chc hn v phng php tnh, thit k v quy trnh ch to mt mch in c bn nh mnh ngun, mch cng sut . Cng nh cc yu cu cng ngh, v kinh t vi mc tiu l sn phm ch to ra phi p ng c yu cu v hp vi thi i ngy nay. n K Thut Lp Trnh nm trong chng trnh o to ca nghnh c tin k thut thuc khoa c kh t ng v robot c vai tr ht sc quan trng, l bc u cho sing vin trong con ng hc tp, gip sinh vin hiu su hn v nhng nhim v v nhng yu cu c bn ca mt ngi k s c in, v quan trng nht l tng hp li nhng g mnh hc trong sut thi gian qua. Trong qu trnh thc hin n c s hng dn v gip tn tnh ca thy H NGC NGUYN cc em hon thnh n ny Em xin chn thnh cm n. -------Ngi thc hin NGUYN HU MINH L ANH KHOA

PHN I:

TNG QUAN V ARM LPC2103.


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I.1 : GII THIU TNG QUAN V ARM 1. 1ARM = Acorn RISC Machine. Sau ny, do c thm nhiu cng ty cng pht trin v mt s l do khc, ngi ta thng nht gi ARM=Advance RISC Machine. 1.2ARM c dng trong Iphone ca Apple (ARM Cortex A5) 1.3ARM s dng kin trc RISC: Kch thc 1 lnh l c nh vi ch mt vi nh dng S dng kin trc load-store , cc lnh x l d liu ch trong thanh ghi

( ton hng ch c nm trong thanh ghi,phi dng lnh truy cp load ni dung t b nh vo ri mi thc hin cng tr v..v..) Gii m cc lnh logic bng phn cng Thc thi theo pipeline

1.4ARM nhanh hn, tit kim nng lng hn v nh gn hn 1.5Thch th chn, c lm sao ko? I.2 ARM CORTEX V ARMv7 Trc ht ARM khng phi l 1 b vi iu khin kiu nh 8051, AVR N

ch l mt ci li (core) chuyn x l d liu, v kin trc ca li ny c cng ty ARM thit k, bn cho cc hng khc theo dng cp php s hu tr tu (Intellectual Property), cc hng sn xut khc s lp thm cc thnh phn ngoi vi vo ci core ny to ra 1 sn phm hon thin. n gin , cc bn hy tng tng core ARM chnh l ci chp core-i5, core-i7 thm ch l core-9. Cc cng ty s lm nhim v lp thm RAM, ROM, cng USB, cng LAN v cho ra i cc sn phm c th nh : LPC2000,LPC2148, LPC3xxx, LPC1114, ATSAM7


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Dng ARM7 da trn kin trc Von Neumann s dng chung vng nh

cha d liu v chng trnh, do dng chung bus cho vic truy xut. Cortex-M3 da trn kin trc Harvard, c c trng bng s tch bit gia

vng nh cha d liu v chng trnh do c cc bus ring truy cp. V c th c cng lc lnh v d liu t b nh, b vi x l Cortex-M3 c th thc hin nhiu hot ng song song, tng tc thc thi ng dng.

I.3 KIN TRC CA ARM71.3.1 Kin trc c bn:

Cu trc load-store Lnh c chiu di c nh Lnh c 3 a ch. Thay v ch dng 1 chu k xung nhp cho tt c cc ch lnh, ARM thit k

sao cho ti gin s chu k xung nhp cho mt ch lnh, do tng c s phc tp cho cc ch lnh n l.1.3.2

Cu trc load store:

Cng nh hu ht cc b x l dng tp lnh RISC khc, ARM cng s dng cu trc load-store. iu c ngha l: tt c cc ch lnh u c thc hin trn thanh ghi. Ch c lnh copy gi tr t b nh vo thanh ghi hoc chp li gi tr t thanh ghi vo b nh mi c nh hng ti b nh. 1.3.3 Tp lnh ca ARM: Tt c cc lnh ca ARM c th thuc 1 trong 3 loi sau: + Ch lnh x l d liu: ch thay i gi tr trn thanh ghi._____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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+ Ch lnh truyn d liu: copy gi tr t thanh ghi vo b nh v chp gi tr t b nh vo thanh ghi. + Ch lnh iu khin dng lnh: Bnh thng, ta thc thi cc ch lnh cha trong mt vng nh lin tip, ch lnh iu khin dng lnh cho php chuyn sang cc a ch khc nhau khi thc thi lnh, ti nhng nhnh c nh, hoc l lu v tr li a ch phc hi chui lnh ban u hay l ln vng code ca h thng . Mt s c im ring bit ca tp lnh : + tng tnh mm do v gim kch thc chng trnh, ARM a ra mt loi lnh gi l THUMB ch c 16 bit. Vi lnh 16bit ny tc thc thi ca chng trnh s gim tuy nhin b nh lu tr ca chng trnh s tit kim hn. Theo nh datasheet ca LPC2148 th : + Mi cu lnh trong ARM u c th vit thnh cu lnh c iu kin v d: EQMOV R1, #0x02FE0302 ; c ngha l move gi tr #0x02FE0302 vo R1 nu kt qu ca cu lnh trc = R1 v s set c Z ln 1(EQ c thm vo trc MOV v ngi ta gi th loi ba nhn ny l Suffix, c th tra datasheet ci bng Suffix ny) . iu ny lm cho mt s cu lnh r nhnh c thc hin rt nhanh.

Phn II : CU TRC V B NH V CHC NNG PIN LPC 2103Cc tnh nng c h tr trong LPC2103 - L vi iu khin 32 bit_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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- C 8KB Ram v 32KbRom, hot ng cao nht 70Mhz (Dng LPC2101/2102 l tng t nhng c Ram v Rom t hn) - ISP/IAP, kh nng np xung vi iu khin 256bytes/1ms hay xa ton b chip trong 100ms - Kh nng Debug theo thi gian thc bng cng JTAG - ADC 10bit vi thi gian thc hin 2.44u. Ghi thng vo thanh ghi kt qu khng cn dng ngt. - 2 b timer 32 bt (Timer0 v Timer1) vi 7 chn Capture v 7 knh so snh. - 2 b timer 16 bt (Timer2 v Timer3) vi 3 chn Capture v 7 knh so snh. - ng h thi gian thc low power (Real-Time Clock (RTC)) cp ngun ri v kh nng dng xung ri 32Khz. - 2 b UART, 2 b FastI2C (400Kbit/s) SPI v SSP. - B vct ngt c th iu chnh u tin.(1 ngt nhanh Fast IRQ, 16 vector ngt c th lp trnh a ch Vectored IRQ, cc ngt cn li NonVectored IRQ bn c th nh danh ngun gy ra ngt sau khi vo ch ngt. - 32 chn ng xut nhp cng dng chung 5V - 13 chn c kh nng lm chn ngt ngoi - C b nhn tng gip VK hot ng 70Mhz vi tn s ng vo t 1 n 25Mhz. - C ch Idle, Power-down. - Thc dy trong ch Power-down hot Idle thng qua ngt ngoi hot nh gi trong RTC. - C kh nng tt hoc m tng phn cc module ngoi vi gip ti u ha lng in nng tiu th. - C ch Thump dng tp lnh 16bit thay v 32bit v c kh nng phi hp c 2 ch , gip ti u thi gian thc hin cng nh chi ph b nh. Trong ch Thump bn gim c 30% code nhng chy chm hn 40% so vi ch 32 bit ( thng c gi l ch ARM ) ARM c mt b PLL l mt b nhn tn s. Tc l khi thch anh u vo ca_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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bn ch l 12MHz v bn mun hot ng tn s 60MHz (h tr cao nht n 70Mhz) th bn cn nhn 5 tn s ng vo. iu ny c thc hin thng qua thanh ghi PLLCON, PLLCFG v PLLFEED. V thng c khai bo sn trong file startup.s mc nh ca Keil. Clock sinh ra thng qua PLL gi l Cclk. Cclk quyt nh tc thc thi lnh cng nh tc AHB bus (cc bus c tc cao trong VK nh bus b nh). Bn cnh th ARM cn c mt b chia tn s gi l b VPB divider. Clock sinh ra thng qua b chia VPB s quyt nh tc ca VPB bus v c tn l Pclk. Bus ny thng c dng giao tip vi cc thit b ngoi vi (nhm trnh gy hin tng nghn c chai do tc ca cc thit b ngoi vi chm hn tc ca VK). Bn cnh cn dng iu khin Timer (nu dng ngun clock ni th c mi xung ca Pclk s tng timer count ln 1, cn nu dng xung ngoi th c mi cnh ln ca Pclk th VK s kim tra tn hiu ng Capture). B VPB c quyt nh bi thanh ghi VPBDIV. V d, nu bn cho VPBDIV = 0x00000002 th tc l Pclk s c tn s bng tn s ca Cclk II.1 PINSEL0 v PINSEL1 - y l hai thanh ghi chn chc nng cho chn ca vi iu khin. Ring con LPC2103 ch c mt Port 0 duy nht gm 32 chn nh du t P0.0 n P0.31. Mi chn thng c t 3 n 4 cng dng. Chc nng mc nh l chn xut nhp chung (tc dng iu khin Led hoc LCD hoc nhn phm bm tc lm bt c g m khng dng n module thit k sn bn trong VK). - PINSEL0 iu khin cho 16 chn u, cn PINSEL1 iu khin 16 chn cn li. Bt th 0 v 1 ca PINSEL0 s iu khin cho P0.0, bt th 2 v 3 iu khin cho P0.1. Tng t cho cc chn cn li, tc 2 bt iu khin cho 1 chn. - Chng hn P0.0 c 3 chc nng, chc nng th 0 l GPIO, th 1 l TXD0 (chn Transmitter ca UART0) v th 2 l MAT3.1(PWM th 1 ca timer 3) vy nu bt 1v 0 ca PINSEL0 c gi tr l 00 th P0.0 l GPIO, nu l 01 th l TXD0 v 10 l MAT3.1. Gi tri 11 khng c s dng. Cc chc nng cng nhng th t chc nng ca mi chn cc bn c th tham kho trong phn User manual rt hon chnh. cc Tuts sau mnh s c gng trnh by y cc chc nng m bn c c t mt con LPC2103. II.2. IOPIN_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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- y l thanh ghi dng c trng thi ca cc chn, khng cn bit chn ang l Input hay Output. Mi bit trong thanh ghi IOPIN s tng ng trng thi ca mt chn trong P0. - Bn c th ghi thng vo thanh ghi ny cc gi tr cn xut ra cho cc chn, lu l tt c cc chn s b thay i theo gi tr m bn gn. Khc vi thanh ghi IOSET hay IOCLR l ch cc v tr bn gn 1 th port mi thay i gi tr. Quyt nh dng thanh ghi IOPIN hay IOSET/IOCLR s gip bn ti u c chng trnh ca mnh. II.3. IODIR - Thanh ghi dng quyt nh mt chn l Input hay Output. Ci ny ch c tc dng khi chn l GPIO(nu khng phi l GPIO th vic l output hay input s do cc module c sn trong VK ph trch). Bt bit no ln th Port tng ng vi bt s l output, mc nh s l input.

II.4. IOSET/ IOCLR - 2 thanh ghi dng thay i trng thi ca cc chn. Nu bn ghi bit 1 vo thanh ghi IOSET th ti v tr tng ng chn s c logic mc cao. Cn nu bn ghi bit 1 vo thanh ghi IOCLR th ti v tr tng ng chn s c logic mc thp (ch ghi 1 vo IOCLR, ghi 0 vo s khng c tc dng).\ E. Cc thanh ghi FastGPIO : (Khi SCS = 0x00000000 (mc nh) bn ch GPIO cn nu SCS = 0x00000001 bn vo ch FastGPIO). Thanh ghi tng ng nh cc thanh ghi GPIO nhng tc ci thin 3.5 ln (Gip bn c th sinh ra nhng tn hiu c tn s cao hn). - Tng t vi cc thanh ghi FIODIR, FIOMASK, FIOPIN, FIOSET, FIOCLR.S khc bit ln nht gi Fast GPIO v Slow GPIO l tc p ng chnh nhau khong 3.5 ln, tc l tn s bn c kh nng sinh ra cc chn c th cao ln gp 3.5 ln. V iu khc bit th hai l khi ghi hoc c d liu vo cc thanh ghi FIOPIN, FIOSET hay FIOCLR th ch cc bit no trong thanh ghi FIOMASK l 0 th mi c c hoc ghi. V d ti mun cho cc chn t P0.0 n P0.15 ln 1 v gi nguyn gi tr cho cc chn cn li, ti c th gn cho FIOMASK=0xFFFF0000 v gn cho FIOPIN =_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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0xFFFFFFFF. Lc cc chn t P0.16 tr i s b che. - iu ng lu l cc thanh ghi ny cha c khai bo trong file LPC210x.h ca Keil, mnh ch xin khai bo li 5 thanh ghi FIODIR, FIOMASK, FIOPIN, FIOSET, FIOCLR m thi. Cn mt s thanh ghi b sung nhm gip ti u ha qu trnh xut nhp, cc bn c th tra thm trong User manua

II.5 : CU TRC CC PIN LPC2103 2.5.1 : S khi ca ARM LPC 2103.


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2.5.2 : Th t chn trn chp trn chip LPC 2103.


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2.5.3: Chc nng v nhim v ca tng chn. - Vi iu khin LPC 2103 c 48 chn . - Gm 32 chn t P0.0 ti P0.31 vi chc nng I/O . - Chn s 7,19,43 ni GND. - Chn s 42, 17, 40 ni VCC(3,3V) - Chn s 5 ni VCC(1,8V)


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- Tng cng c 32 chn ca Port 0 c th c s dng nh mc ch chung hai chiu va c th l tn hiu u ra va c th l tn hiu u vo.Ring Port 0.31 ch c th l tn hiu u vo input. - Cc chn ca Port 0 c hot ng ph thuc vo chc nng pin la chn thng qua cc kt ni khi pin . - LPC 2103 s dng hai thch anh dao ng ,mt thch anh cho mch chnh, mt thch anh cho ng h thi gian thc . - Chn s 20,25 s thch anh RTCX1,RTCX2 _32KHZ_l u vo v u ra cho mch giao ng RTC(rill time clock). - Chn s 11,12 s dng thch anh XTAL1,XYAL2 l u vo v u ra cho mch dao ng ni b . - Chn s 26 _ RTCK :Tr li ng h kim tra u ra .Extra tn hiu c gi n cng JTAG. H tr g ri ng b ha khi b x l tn s khc nhau. - Chn s 27 _ DBGSEL c chn: khi mc thp, mt phn hot ng bnh thng. Khi bn ngoi ko ln mc cao , P0.27 P0.31 c cu hnh nh JTAG cng v mt phn l ch Debug. - Chn s 6 _ RST_ Khi chn ny c a v mc thp th thit b b s c reset, gy ra cng I / O v thit b ngoi vi a vo trng thi mc nh ca h v thc hin x l bt u ti a ch 0. TTL vi thi gian tr 5 V l . II.6 : CC CHC NNG PORT 0 . - P0.0 : chn 13 ca LPC 2103. + Tng gim mc ch u vo / u ra k thut s pin. + TXD0 - pht u ra cho UART0. + MAT3.1 - PWM ra 1 cho Timer 3. - P0.1 : chn 14 ca LPC 2103._____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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+ Tng gim mc ch u vo / u ra k thut s pin. + RXD0 - pht u ra cho UART0. + MAT3.2 - PWM ra 2 cho Timer 3. P0.2 : chn 18 ca LPC 2103.

+ Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + SCL0 : C0 ng h u vo / u ra. + CAP0.0 : Bt u vo cho Timer 0, knh 0. P0.3 : chn 21 ca LPC 2103.

+ Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + SDA0 : C0 d liu u vo / u ra. +MAT0.0 : PWM u ra cho 0 Timer, knh 0 P0.4 : chn 22 ca LPC 2103.

+ Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + SCK0 : Serial ng h cho SPI0. SPI ng h u ra t ch hoc u vo cho thit b. + CAP0.1 : Bt u vo cho Timer 0, knh 1. P0.5 : chn 23 ca LPC 2103.

+ Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + MISO0 : D liu u vo cho SPI ch hoc d liu u ra t SPI thit b. +MAT0.1 :PWM u ra cho Timer 0, knh 1 - P0.6 : chn 24 ca LPC 2103. + Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m._____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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+ MOSI0 : D liu u ra t SPI ch hoc d liu u vo t SPI thit b. + CAP0.2 - Bt u vo cho Timer 0, knh 2 . P0.7 : chn 28 ca LPC 2103.

+ Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + SSEL0 : Thit b ngoi chn SPI 0.Chn giao din SPI l mt thit b bn ngoi thc thi. + MAT2.0: PWM u ra cho 2 Timer, knh 0. - P0.8 : chn 29 ca LPC 2103. + Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + TXD1 : pht u ra cho UART1. + MAT2.1 :PWM u ra cho Timer 2 , knh 1. - P0.9 : chn 30 ca LPC 2103. + Tng gim mc ch u vo / u ra k thut s pin. Kt qu l cng c m. + RXD1 : nhn u ra cho UART1. + MAT2.2 : PWM u ra cho Timer 2 , knh 2. P0.10 : chn 35 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + RTS1 : Yu cu u ra cho UART1 gi. + CAP1.0 : Bt u vo cho 1 Timer, knh 0. + AD0.3 : ADC 0, u vo 3. P0.11 : chn 36 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + AD0.4 - ADC 0, u vo 4._____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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+ CAP1.1 : Bt u vo cho Timer 1, knh 1. + CTS1 :Clear Gi u vo cho UART1. P0.12 : chn 37 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + DSR1 : Data Set Ready u vo cho UART1. + MAT1.0 : PWM u ra cho 1 Timer, knh 0. + AD0.5 : ADC 0, u vo 5. P0.13 : chn 41 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +DTR1 : Data Terminal Ready u ra cho UART1. +MAT1.1 :-PWM u ra cho Timer 1, knh 1 P0.14 : chn 44 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +DCD1 ; Pht hin nh cung cp d liu u vo cho UART1. + SCK1 : SPI ng h u ra t ch hoc u vo cho thit b . +EINT1 : ngt ngoi gin on 1 u vo . P0.15 : chn 45 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +RI1: Ring Ch s u vo cho UART1. +EINT2 : ngt ngoi gin on 2 u vo. P0.16 : chn 46 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +EINT0 - ngoi ngt 0 u vo. + MAT0.2 - PWM u ra cho Timer 0, knh 2 P0.17 : chn 47 ca LPC 2103.


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+Tng gim mc ch u vo / u ra k thut s pin. + CAP1.2 - Bt u vo cho Timer 1, knh 2. + SCL0 : C1 ng h u vo / u ra. P0.18 : chn 48 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + CAP1.3 - Bt u vo cho Timer 1, knh 3. +SDA1 :C1 d liu u vo / u ra. pin ny l mt cng m ra nu chc nng c chn trong cc kt ni khi pin . P0.19 : chn 1 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + MAT1.2 - PWM u ra cho Timer 1, knh 2. + MISO1 : D liu u vo cho SPI ch hoc d liu u ra t SPI thit b. P0.20 : chn 2 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + MAT1.3 - PWM u ra cho Timer 1, knh 3. + MOSI1 : D liu u ra cho SPI ch hoc d liu u vo t SPI thit b. P0.21 : chn 3 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + MAT3.0 - PWM u ra cho Timer 3, knh 0. + SSEL1 : Thit b ngoi chn SPI1.Chn giao din SPI l mt thit b bn ngoi thc thi. P0.22 : chn 32 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + AD0.0 ADC0, ng vo 0. P0.23 : chn 33 ca LPC 2103.


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+Tng gim mc ch u vo / u ra k thut s pin. + AD0.7 ADC0, ng vo 7 P0.27 : chn 8 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + TRST - Test thit lp li cho giao din JTAG. Nu DBGSEL l cao, chn ny l t ng cu hnh s dng vi EmbeddedICE (Debug ch ). + CAP2.0 - Bt u vo cho 2 Timer, knh 0. P0.28 : chn 9 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. + TMS - Chn ch th nghim cho giao din JTAG . Nu DBGSEL l cao, chn ny l ) t ng cu hnh s dng vi EmbeddedICE (Debug ch ). + CAP2.1- Bt u vo cho 2 Timer, knh 1. P0.29 : chn 10 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +TCK - Kim tra ng h cho giao din JTAG. ng h ny phi c chm hn 1/6 ln ca CPU ng h (CCLK) cho giao din JTAG hot ng. Nu DBGSEL_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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l cao, iu ny pin c t ng cu hnh s dng vi EmbeddedICE (Debug ch ). + CAP2.2 - Bt u vo cho 2 Timer, knh 2. P0.30 : chn 15 ca LPC 2103.

+Tng gim mc ch u vo / u ra k thut s pin. +TDI - Kim tra d liu nhp cho giao din JTAG. Nu DBGSEL l cao, chn ny l t ng cu hnh s dng vi EmbeddedICE (Debug ch ). +MAT3.3 - PWM ng ra 3 cho Timer 3. P0.31 : chn 16 ca LPC 2103.

+ Tng gim mc ch u ra k thut s pin. + TDO - Kim tra d liu ra cho giao din JTAG. Nu DBGSEL l cao, chn ny l t ng cu hnh s dng vi EmbeddedICE (Debug ch )

Phn III: PLL Control Register (PLL0CON & PLL1CON):III.1 : PLLCON Cha cc bit kch hot v kt ni PLL. Kch hot PLL cho php kha cu hnh hin ti (vi 2 s M & P). Kt ni PLL lm chip v ton b cc chc nng chy theo xung nhp t ng ra PLL. Bit 0 K hiu PLLE ngha bit = 1: cho php kch hot PLL v kha ti tn s yu cu._____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

Gi tr sau Reset 0

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1 7:2

PLLC -

khi PLLE v PLLC = 1 th PLL c kt ni nh ngun xung cho vi iu khin Reserved

0 n/a

III.2 : PLL Status Register (PLL0STAT & PLL1STAT): PLLSTAT l thanh ghi ch c, n cha cc gi tr thc s ca b PLL ti thi im c thanh ghi ny. Bit 4:0 6:5 7 8 9 10 15:11 III.3 : PLLCFG s khng c tc dng. thay i cu hnh PLL chn, phi ghi vo thanh ghi PLLFEED theo 1 th t xc nh: - Ghi 0xAA vo PLLFEED - Ghi 0x55 vo PLLFEED Thao tc ghi phi theo ng th t, v lin k nhau. K hiu MSEL PSEL PLLE PLLC PLOCK ngha Gi tr sau Reset 0 0 n/a 0 0 0 n/a s nhn hin ti ang c s dng bi b PLL s chia hin ti ang c s dng bi b PLL Reserved bit = 1: b PLL ang c kch hot bit = 1: b PLL ang c kch hot v kt ni. bit = 0: PLL cha c kha Reserved bit = 1: PLL c kha vi tn s yu cu

PLL Feed Register (PLL0FEED & PLL1FEED)

Sau khi b PLL c kt ni, mi thay i trong 2 thanh ghi PLLCON &


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******************************************************* V D: tnh ton tn s PLL: gi s tn s thch anh l 12MHz v tn s chip CCLK l 60MHz, khng s dng USB. Fosc: tn s dao ng thch anh Fcco: tn s dao ng ca PLL CCO CCLK: ng ra PLL, ng thi l xung h thng Ta c: CCLK = Fosc x M => M = 5 Fcco = CCLK x 2 x P 156 MHz < Fcco < 320 MHz => 1.3 < P < 2.7 => P = 2

Bng gi tr ca MSEL & PSEL: PSEL bits 6:5 ca PLLCFG 00 01 10 11 MSEL bits 4:0 PLLCFG 00000 00001 11110 11111 Vy PSEL = 01 v MSEL = 00100 Gi tr ghi vo thanh ghi PLLCFG s l 0x00000024 P 1 2 4 8 M 1 2 31 32

III.4 : Pulse Width Modulator (PWM):_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn SVTH : L Anh 1 Khoa Nguyn Hu Minh

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B to xung PWM c thit k da trn b Timer/Counter, hot ng theo xung PCLK. Nguyn tc hot ng da trn cc Match events ca 7 match register. C 2 loi xung: - Single Edge: tt c cc xung u c set ln 1 ngay khi bt u 1 xung PWM, xung c set v 0 khi gi tr ca timer counter bng vi gi tr ca 1 trong cc Match register 1-6. C th c ti a 6 xung Single Edge ng thi, tt c cc xung u c cng tn s c iu khin bi Match register 0 (khi gi tr ca timer counter bng gi tr trong Match register 0 th kt thc 1 xung PWM v bt u 1 xung mi).

III.5 : PWM - Double Edge: cc xung c set bng 0 khi bt u 1 xung PWM, c set ln 1 bng 1 Match register v set v 0 bng 1 Match register khc. Cc xung double edge cng c tn s c iu khin bi Match register 0.

PWM2 & PWM4: double edge PWM5: single edge Bng cc knh PWM: Knh Set by 1 Match 0 Single Edge Reset by Match 1 SVTH : L Anh 1

Double Edge Set by Khoa Nguyn Hu Minh

Reset by

_____________________________________________________________________________ GVHD : Th.S H Ngc Nguyn

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2 3 4 5 6

Match 0 Match 0 Match 0 Match 0

Match 2 Match 3 Match 4 Match 5 Match 6

Match 1 Match 2 Match 4 Match 5

Match 2 Match 3 Match 4 Match 5 Match 6

Match 0

Match 3

PHN IV : CHN PHN MM LP TRNH CHO CHPHin nay c nhiu phn mm lp trnh cho LPC2103 nh Keil uVision4 for ARM y l phn mm thng dng c s dng nhiu nht hin nay. Bn cnh cn c Raisonance Tools hay cn gi l Ride7 dnh ring cho ARM, phn mm ny h tr kh y cho vic lp trnh IO,PPL,ADC,PWM cho ARM vi vic khai bo sn trong file th vin (.h), cc v d n gin trong phn Example. Ngoi ra ngi s dng c th khai bo nhng thanh gi khc m khng c sn trong file th vin s dng cho nhng ng dng khc. y chng ta s dng Raisonance Tools lp trnh cho LPC2103. GIAO DIN V LP TRNH C BN VI RAISONANCE TOOLS Biu tng Raisonance Tools


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- Giao din chnh:


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Cc bc lp trnh cho LPC2103 bng Ride7 nh sau: Khi ng chng trnh. To New Project cho LPC2103 Chn cc thng s bn phn Properties Lp trnh (vit code) Bin dch sa li v np qua ISP V cu t rc chng trnh ca Ride7 tng i ging vi cc phn mm lp trnh

# cng s dng ngn ng C, ch khc nhng lnh h tr v tn thanh ghi th gn nh tng ng vi Keil uVision4 v d sau y l mt on chng trnh tng ng c Em vit bng 2 phn mm Keil uVision4 v Ride7 cho LPC2103. - Chng tring dch led t tri qua phi 8 bit t p0.16 -> p0.23 s dng delay vit tay. Ride7 :#include volatile unsigned int dcnt; volatile unsigned int i=0x00010000; void donothing(); #define IMAXVAL (0x800) #define MINDELAY (0x10) #define MYFIODIR IODIR #define MYFIOSET IOSET #define MYFIOCLR IOCLR #define MYOUTPUTSHIFT 16 #define MYOUTPUTMASK (0x00FF0000) main() { Delay(0x1000); MYFIODIR = MYOUTPUTMASK; while(1) { IOCLR = i & 0x00FF0000; Delay(MINDELAY*(1000)); IOSET = i & 0x00FF0000; i = i * 2; if (i>0x01000000) i =0x00010000; } } void donothing() {;} void Delay(unsigned int cnt) { dcnt=cnt; while(dcnt--) donothing();


n K Thut Lp Trnh MYFIOSET = MYOUTPUTMASK; IODIR = 0x00FF0000; }

Vit bng Keil uVision4#include #include void delay(int time)//Ham delay { unsigned int count; for (count = 0; count

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