October 20, 2015Dongsup Song

Test Challenge for Mobile APDFT Perspective

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Agenda

• Mobile AP DFT introduction• DFT for Logic inside Mobile AP• DFT for Memory inside Mobile AP• DFT for IPs inside Mobile AP• Conclusions

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Mobile AP Chips• Mobile AP Components

Interconnection network

CPU GPU• Multi channels bus architecture• Bridge• Synchronization• QoS

Multimediasubsystem

• 2D/3D graphic HW• Video codec• Image signal processing

Modem

Display/Camera

MemoryInterface

External peripheral

SystemPeripheral

• PLLs• DMA• System MMU• Audio

• USB for high speed I/F • UART• SPI• ADC

• DRAM controller : LPDDR3/4, Wide I/O• NAND controller: eMMC, UFS

• MIPI• eDP• HDMI• WIFI

• Multicore design• L2 cache• Enhancing CPU clock speed

• CPU• DSP• RF componet

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Mobile AP Chips• Characteristics of Mobile AP Chips

– Very large number of integrated transistor on a chip– Mixed signal technology on a chip

• Digital logic, embedded SRAM, analog, hard IPs• Requires different testing methodologies and test sets according

to the characteristic of components

– Diverse clock frequency– High performance– Short time to market– Cost sensitivity

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DFT for Mobile AP

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• General DFT scheme for logic test– Test coverage for highly reliable AP test

• Stuck-at fault, transition delay fault, bridging fault, small delay defects

– Full scan– Compression– Wrapper for testing inter-block– Shared IO or Serializer

DFT for Logic inside Mobile AP

[Source : Synopsys]

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• Scan shift speed that is scan test cost• Pipelined scan data

– Provide DFT structure that helps ease high speed timing closure during scan shift

– Timing critical paths

• Function output gating during scan shift– Reduce the power problems during scan shift

• Big voltage drop and big voltage overshoot

– Test cost reduction via faster scan shift clock frequency – Yield improvement: Better LVcc margin

DFT for Logic inside Mobile AP

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• At-speed testing of Mobile AP logic– Become important more and more to reduce

defective parts per million (DPM)– Transition delay fault model

• Most popular at-speed test pattern for production

– Path delay fault model– Small delay defect

• ATPG for transition delay fault– Two at-speed clock pulse during capture cycle

DFT for Logic inside Mobile AP

[source : Delay Test and small-delay Defects, Springer]

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• Scan design– OCCC(On-Chip Clock Controller)– Use the internal clocks for at-speed clocking during scan capture– Unnecessary scan clock mux inside IP could be eliminated

DFT for Logic inside Mobile AP

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• Effective X-handling is very important for high TD coverage– X source : black box, hard IP, SRAM, or timing violation, etc

• Very bad for compression (XOR tree)• Clue for pattern inflation & coverage degradation

– Isolation wrapper, X-chain

DFT for Logic inside Mobile AP

[Source : Synopsys]

X

X

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• TD coverage degradation due to improper scan clock – Proper scan clock distribution is very important to get high test coverage

especially for TD• Applying real speed (at-speed) scan clock feeding• Scan clock, Scan clock grouping, on-chip-clock controller location, etc.

– Transition delay test• Pattern should generate a transition at the fault site• Effect of transition should be captured at-speed

DFT for Logic inside Mobile AP

200MHzFCLKSCLK

STM

100MHzDIV

Masking

400MHzFCLKSCLKSTM

100MHz

200MHz

400MHz

OCCC

OCCC

OCCC

div4

div2

SCLK is fed by ATE clock Low test quality (not tested at

speed)

Same at-speed clock source for different clock domain

Make many timing violation-> X source

Cross domain could not be tested with at speed

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• Scan design– Scan clock structure

DFT for Logic inside Mobile AP

IP_0

PLL DIV

IP_0

PLL DIV

fclk

OCCC

ATECLK

fclk

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• Scan design– Scan clock structure

DFT for Logic inside Mobile AP

IP_1

PLL DIVfclk

DIV

IP_1

PLL DIVfclk

DIV

OCCC

OCCCATECLK

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• Scan design– Scan clock structure

DFT for Logic inside Mobile AP

400MHz

FCLK

IP_0

200MHz

FCLK

IP_1

200MHz

IP_2

100MHz

PLL DIV

OCCC

OCCC

DIV OCCC

OCCCFCLK

ATECLK

400MHz

FCLK

IP_0

200MHz

FCLK

IP_1

200MHz

IP_2

PLL DIV

OCCC

OCCC

DIV

FCLK

ATECLK100MHz

sync O

CCC

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• DFT for embedded SRAM– Characteristics of embedded memory

• Only limited access allowed at primary I/O• Simple functional specification, but features associated with analog circuit• Large and regular test patterns• Hard-macro (full custom design)

– Embedded memory testing method• BIST(Built-In Self Test) is commonly used method

– Memory BIST Benefits• Efficiently test embedded memory

with minimum test pin.• At Speed testing with low cost testers• Easy to test multiple memories in parallel• Fail memory and fail address detection

capability• Less routing overhead

DFT for Memory inside Mobile AP

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• DFT for embedded SRAM – Roles of Memory BIST circuitry

DFT for Memory inside Mobile AP

SRAM Defect localization

Repair address calculation

Yield enhancement through redundancy control

Point out exact faulty bit cell position via at-speed SRAM read/write operation

This information is used for the pFA input

SRAM binning – Prime good, repairable, unrepairable SRAM For repairable die, BIST offers the address to be repaired

(BIRA – Built in repair analysis)

DC defect screen : open, short Parametric defects• Fails occurred only within certain range of VDD

• In general, more likely to occur at low VDD than at high (VMIN)• Not defect-driven but driven by characteristics (VT, ION) of PG/PD/PU FETS• Occur when one of more FET in a cell is too far away from VT or ION target• Write fails

PG too weak (VT too high, ION too low) compared to PU on same side of cell• Access disturb (stability) fails

PD too weak compared to PG on same side PD too strong on other side PU too weak on other side

• Read fails PG-PD series combination too weak to pull down BL before WL turns off

• Hold fails

SRAM Defect screen

Feed the repair information to SRAM for repairing

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• Weak bit screen has become an important design and test issue– Weak bit (VDDMIN)

• A weak cell is a cell with inadequate SNM that can be easily flipped• Every bit cell must work properly• The SRAM bit cell is a ratioed circuit which depends on the relative strengths of

its transistors• Weak cell failures are random

– Cells are not entirely damaged – The state flipping may be triggered only under certain operating conditions

– SNM (Static Noise Margin)• Max static noise, which can be tolerated by an SRAM cell without changing its

logical state

DFT for Memory inside Mobile AP

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• DFT for embedded SRAM : Parametric defects– Sources of weak bit failure : “Within Die Variation”

• Random Dopant Fluctuations (RDF)– Statistical variation in the number and placement of dopants in the

channel– The variability of Vth due to RDF

• Line Edge Roughness (LER)• Gate Stack (tOX, etc.)• Lithography (ACLV, edge effects, etc.)• Temperature and temperature gradients

DFT for Memory inside Mobile AP

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DFT for Memory inside Mobile AP• Read failure

– Read operation (Iread = Cell current, Read current)

– Read failure modes• Fail to read by low delta between

BL and BLB• BL has not fallen far enough

below BLB for sense amplifier to sense the difference

• PG-PD series combination too week to pull down BL before WL turns off (low β)

)(

PDPG

PGPD

PG

PDread LW

LW

I

II

High beta helps prevent read fails

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• Write failure– During a write node NR must be pulled low through T6– If NR cannot be discharged below the trip point of INV(1,2), during

the WL pulse, the result is a write failure VTH

DFT for Memory inside Mobile AP

gamma = (PG Ion)↑ / (PU Ion)↓high gamma helps prevent write fails

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• Weak cell screen– VTEST is very important for screening weak cell

DFT for Memory inside Mobile AP

[Source : CMOS SRAM Circuit Design and Parametric Test in Nano-Scale Technologies (Springer, 2008)]

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Vin (V)

Vou

t (V

)

Vweak

VgoodVTEST

VDD

VDD

Weak cell will filps Good cell does not filp

[Source : Andrei Pavlov, ITC]

VTEST

Vweak

Vgood

VTEST

Vweak

Vgood

VTEST

Vweak

Vgood

Good cell pass Weak cell pass Weak cell escape

(High PPM)

target VTEST range Good cell fail Weak cell fail Yield loss

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• Design flow for developing mobile AP

DFT for IPs inside Mobile AP

Spec. decision

Architecture design

RTL design

Architecture spec.

design spec.

Start synthesis

RTL signoff (LINT/DFT rule check)

1st sign off

2nd sign off

Mask Tape Out

1st cap. is available

Design DFT logic- Design AP level DFT controller & Test access- IP level DFT design (wrapper etc…)- Memory BIST design- AP level DFT integration- DFT rule check

Define DFT architecture- AP level DFT control mechanism?- Test access mechanism?

DFT sign-off- Post-netlist simulation for all DFT mode with SDF- Sign-off PVT corner

SVP (Silicon Virtual Prototyping)

How many times are available from spec. decision to Mask tape out?

How many times do you need to verify modern AP netlist with SDF?

DFT synthesis & verification with pre-netlist- Scan synthesis- DFT rule check- Pre-netlist simulation for all DFT mode without SDF

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• Testing the entire AP as one monolithic entity has drawbacks with: – Test quality– Test development effort– Test application cost

• Modular AP testing– The integration of a complete system on an AP chip.

• Earlier consisted of multiple IC chips.– May include multiple types of design blocks and intellectual property (IP)– Typically AP’s are designed using embedded reusable cores– Modular testing makes total AP test development a distributed effort in

time and/or place

• Testing the nonlogic circuit such as: – Custom-designed processor cores– Mixed analog and digital(ADC, DAC, PLL), – High speed interface– Many hard IPs (MIPI, eDP, HDMI, etc…)– These nonlogic circuit structures exhibit different defect behavior, and

hence require their own test approaches with dedicated fault models

DFT for IPs inside Mobile AP

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• Concept of Modular AP Testing– Test source : On chip device or off-chip ATE– Test Sink : On chip device or off-chip ATE– Test controller : JTAG based controller – TAM (Test access mechanism)– Test wrapper : Provides test access or isolation

DFT for IPs inside Mobile AP

AP

Block(or hard IP or SRAM, etc…)

Test wrapper

Test controller

Test source

Test sink

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• Benefits of modular AP testing– Test pattern generation and verification can begin as soon as a

module is finished, rather than after the entire AP design is completed

– DFT reusability– DFT Verification TAT can be reduced

DFT for IPs inside Mobile AP

Module A design

Module B design

AP SOC integration of Module A and Module B

Newly Test development & verification for Module A and Module B at AP level

Module A design

Module B design

Module A Test development

AP SOC integration of Module A and Module BModule A Test development

Module level test can be reused at AP SOC Pattern retargeting methodology is needed

verification time reductionAP verification

can reuse that of Modules

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• Benefits of modular AP testing– DFT verification time could be reduced

• Design and test generation are typically iterative processes• File sizes and tool runtimes become more manageable

– Facilitates fake netlists for unnecessary block/IPs– Design partitioning should be considered during RTL design (test

clock etc…)

– Test time could be minimized through maximizing concurrent test • Test channel optimization for each IP could be obtained by test

wrapping

DFT for IPs inside Mobile AP

#. of test channel

(unwrapped)

#. of test channel

(wrapped)

USB 89 36

DAC 82 20

ADC 88 23

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• Most popular modular testing standard– IEEE1500

• Define test interface between core and SOC• Facilitate test reuse for embedded cores through core access and isolation• Wrapper cell operation

– Normal mode : wrapper is transparent– Test Access mode : Provides for controlling core inputs and observing core

output– Test isolation mode : Protects core and SOC from damage

• CTL(Core Test Language)– Test configuration(s)– Test Interfaces– Test data (stimuli and response)

DFT for IPs inside Mobile AP

[source: Marinissen 2002]

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• Mobile AP is a SOC which has– very large number of integrated transistor, diverse clock frequency,

and short time to market

• DFT for mobile AP– Perfect Stuck-at fault test is not enough– At-speed test coverage as much as stuck-at test is essential– Efficient weak bit cell screen is crucial for mobile AP test quality– Concurrent IP test helps test cost reduction

Conclusion