Edinburgh & Piezo 09 Presentation v1

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    Imsat logo

    Issues in Manufacturing of Wafer-scale 3DPiezoelectric-on-Silicon Structures.

    Manufacturing considerations for 3D Piezo 0nsilicon wafer scale structures.

    Edinburgh and Piezo 09

    March 2009

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    Imsat logo

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    Imsat logo

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    Loadpoint

    European SME since 1963

    Manufactures in EC to CE standards

    Direct process development service

    Consumable support

    Over 900 Dicing machines in

    operating work wide.

    3,700 Dicing Spindles sold, 500 inthe Pacific Rim

    45 years experience of electronics

    industry

    Backgrounds

    Imsat

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    Imsat logo Wafer scale back ground

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    Imsat logo Piezo-on-Siapplications

    Medical

    NDT

    Sonar

    Ink jets

    Gyroscopes

    Micropumps

    Pressure sensors

    MEMS resonators Microvalves

    Accelerometers

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    Imsat logo

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    Merging 3D technologies

    By permission Yole Developments, Yole News Nov, 2008

    5

    Note mainly silicon

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    Imsat logoLessons from 3 D silicon

    Semetach August 2008

    Their over view on the

    advantages for 3D silicon.

    This could be applicable to

    multi material multi wafer

    wafer scale packaging

    This is all moving very fast

    at the moment

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    Imsat logo Wafer scale basics

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    Imsat logo Packaging TechnologyPull

    ConsumerProducts

    Price

    Integrate as much as possible to reduce number of external

    connections.

    Performance / Capability per unit volume

    Automobile ProfessionalProducts

    Reliability

    Durability

    Performance / Capability per unit volume

    Wafer scale may eliminate 1 level of package, ie BGA QFN etc. This

    will be debated as time goes by.

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    Imsat logo Concepts in MEMS production

    The DRIE-defined structure in

    Si

    Ti

    mes t i

    mi

    ng reference gets asilicon cap at the wafer level

    before being merged w ith a

    CMOS structure in its QFN

    package

    InvenSenses Nasiri-

    Fabrication process

    simultaneously seals and

    interconnects the MEMS

    structure to the CMOS ASIC.

    Another step removes theexcess silicon on the CMOS to

    access the bond pads.

    Small Times September, 2007 Author: Randy Frank

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    Imsat logo Dicing processes, 2008

    Dicing Separation of wafers into

    individual die by sawing, lasering

    or diamond scribing.

    Singulation Separation of moulded frames

    into individual packages bysawing. Normally associated withBGA, BGA, QFN

    10

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    Imsat logo Background

    Supplied dicing machines for airbag pressure sensors to AC Delco,Kokomo in 1978

    Dicing street

    in s

    ilicon 300 m

    icron tosuit 200 micron blade needed for

    glass

    Wafer scale process

    This technology still being usedinspecialist sensors

    Other package dicing customers /projects include: BT Epic, IBMPowerPC, Nokia Telephones ,Siemens LCD, TI DLP, VTI RadioSonds, Ya Hsin SMD LEDS. SKA

    11

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    Imsat logo Silicon 3 D evolution

    //

    //

    //

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    Imsat logoTechnologies becoming useful

    Planarisation

    Thinning of material by grinding or CMP

    In this context grinding quickly gives geometry

    CMPused to give semiconductor / optical finish Dicing by grinding

    Fly cutting now becoming an option

    Post operation cleaning critical

    Interposers

    Vias through silicon, 20 micron 2008, 5 micron 2014

    Not just silicon FR3 & FR4 can be considered as well

    Rapid via generation needed for glass and other materials.

    13

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    Imsat logo Basic silicon Process

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    Imsat logo Issues

    Table 1. Issues in 3D PZT-Si integration

    Issue Description Solutions

    1 Standards: there seem to be very few at the moment so each organisation

    is developing its own.

    SEMI or similar body to undertake.

    2 Coefficient of linear expansion, COE Design, thermal vias, pixellation

    3 Internal stress build up Design, pixellation

    4 Test protocols, procedures and standards Industry

    5 Inspection systems and standards Industry and international standards organisations

    .

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    Dicing by grinding

    Scribe cut silicon wafer thinned to 80 micron

    thickness.

    Edge chipping was an occasional 2 micron size

    defect.

    Top photograph shows a wafer just after

    machining, the middle an enlargement and the

    bottom a cutintersection.

    CMP

    could be used toimprove f

    inish further

    ifneeded.

    Work performed on PicoAce.

    Process good for other materials, i.e.PZT.

    Funded by DTI / Eureka as part ofWalpackWSPProject

    17

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    Imsat logo 6material stack

    Method of build up

    Top down or build up

    Sub elements that are then

    assembled

    Dicing, epoxy potting, grinding

    usedin various combinations

    Molding compound grinds well

    Level to level alignment critical

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    Imsat logo Material combinations

    Possible combination,

    Similar structures now being considered for Research applications.

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    Level Mater ial Funct ion

    1 PZT Sensor / Actuator

    2 Ceramic Absorber

    3 Silicon Dr iver

    4 Silicon Processor

    5 Silicon Interposer

    6 PCB Connect ion

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    Imsat logoStarting point

    6 layer Test piece to explore concepts.

    There are actually 10if copper and bond layers areincluded. This sample 5.14 mm thick, could go muchthicker, say 30 mm

    Interestingideas

    Low profile pads, simply etch the copper

    Jigged pre-alignment

    Not new, 3D Plus have pioneered this approach

    Could be applicable for low medium to mediumvolumes

    Contractors being developed for high volumes

    Suitable for both wafer scale and QFN

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    Imsat logoMulti material, how many layers?

    FR4

    Glass

    Silicon

    Glass

    Silicon

    Ceramic

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    Copper

    FR4

    Copper

    Epoxy

    Glass

    Silicon

    Glass

    Silicon Epoxy

    Ceramic

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    Imsat logo

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    Materials

    Copper

    FR4 Copper

    Epoxy

    Glass

    Silicon

    Glass

    Silicon Epoxy

    Ceramic

    Multi material, how many processes?

    Processes that might be involved

    Routing & drilling FR4

    Photo-etching Copper

    Injection of epoxy

    Grinding & CMPglass Iso-static bonding silicon to glass

    Grinding & CMPsilicon

    Vias in silicon, glass, FR4 and ceramic

    Bulk removal, grinding, DRIE of Silicon

    Bumping and back fill for bumped wafers

    Grinding of epoxy

    Lapping, were suitable

    Cavity machining

    Bonding processes

    Planarisation by flycutting

    Dicing and profiling of all.

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    Imsat logoProcess Sources or development needed

    Routing & drilling FR4 PCB Industry

    Injection of epoxy Back fill or underfill

    Photo-etching Copper or inter-connectmaterial

    PCB Industry

    Grinding & CMP glass Optical industry

    Ink Jet printing of electrical circuits Emerging circuit ink jet printing companies

    Iso-static bonding silicon to glass Established bong organisations

    Grinding silicon Exists already

    CMP silicon Exists already

    Vias in silicon, glass, FR4 and ceramic Silicon evolving, glass development needed

    Bulk removal by DRIE of Silicon Exists already

    Bumping and under fill Exists already

    Grinding of epoxy and ceramic Development needed

    Lapping, were suitable Exists already some development needed

    Cavity machining Moulding, etching, machining

    Bonding processes, not iso-static Development needed

    Planarisation CMP Evolution outside silicon needed

    Planarisation, grinding Needs to be explored

    Fly cutting Rapidly emerging development needed

    Dicing of all or sub-elements Design of wafers and process critical for this

    Inspection 100% of all by X ray or whatever criticsl

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    Imsat logoUseful additions

    Internal screening, RF - MOD

    Islands delineated e

    ither by etch

    ing or gr

    inding

    Same idea for cavities

    Shapes or curves by milling or etching

    What else?

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    Imsat logo Dice out

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    After final bonding dice out of

    whole assembly.

    Might only mean only last one or

    two layers being diced, critical

    point being to maintain

    completeness of structure tomaintain position registration

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    Imsat logo Points to watch

    Tolerances

    Silicon +/- 2 micron

    Thin film +/- 50 micron

    Thick film +/- 75 micron Frame, copper +/- 150 micron

    PCB +/- 200 micron

    Geometry

    Parallelity

    Sequence of build up, epoxy does grind quite well Cleaning

    Dicing / grinding swarf.

    Protection of sensitive structures.

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    Material MachiningProducts

    PicoAce 300 mm waferNanogrinder & Fly cutter

    NanoAce 300 mm wafer dicing machine

    MicroAce 150 mm wafer dicing machine

    MacroAce 50 mm thickness dicer saw grinder

    Washpoint 300 mm after dicing cleaning machine

    Disc Point 150 Fly cutting machine

    Process development and sub-contract dicing grinding

    service

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    Thank you

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    Full list of references atwww.loadpoint.co.ukfrom the 4th March 2009