EE141 Microelectronic Circuits Microelectronic Circuits Ch.2. INHA Univ. 전자회로 1 Chapter 2: Operational Amplifiers 인하대학교 정보통신공학부 2008 년 2 학기

EE141 Microelectronic Circuits Microelectronic Circuits Ch.2.

INHA Univ.INHA Univ.

전자회로 전자회로 11

Chapter 2: Chapter 2: Operational Operational AmplifiersAmplifiers

인하대학교정보통신공학부

2008 년 2학기



ReviewReview

R1=7.5 k

I

R2=2.2 k

vI=5 V

v1 = ?

v2 = ?

I

I1 I2

R1=1k R2=3k

500mA

I

I

VRR

RV

VRR

RV

21

2

2

21

1

1

IRR

RI

IRR

RI

21

1

2

21

2

1

3.85V

1.15V

375mA

125mA



ReviewReview

R1 R2 R3

5V 3V 1V

I

2

2

13

R

VVI

R 0.33

6.6A



Operational Amplifiers


INHA Univ.INHA Univ.2.1 2.1 The Ideal OP AMP The Ideal OP AMP 2.1.1 The Op-Amp Terminals2.1.1 The Op-Amp Terminals

Op-amp has three terminals: two input and one output terminals Most IC op-amps require two dc power supplies.

terminal 4 and 5 connected to a positive voltage VCC and a negative voltage -VEE

Figure 2.1 Circuit symbol for the op amp.

Figure 2.2 The op amp shown connected to dc power supplies.


INHA Univ.INHA Univ.2.1.2 Function and Characteristics 2.1.2 Function and Characteristics of the Ideal Op Ampof the Ideal Op Amp

Op-amp function: sense the difference between the voltage signals applied at its two input terminals (i.e., the quantity v2-v1), multiply this by a number A, and cause the resulting voltage A(v2-v1) at output terminal 3.

Fig. 2.3 Equivalent circuit of the ideal op amp.

Inverting input terminal (V1 이 증가하면 Vo 가 감소한다 )

Noninverting input terminal (V2 이 증가하면 Vo가 증가한다 )

Positive power supply Negative power supply Open loop gain A



Characteristic of the Ideal Op-AmpCharacteristic of the Ideal Op-Amp

Infinite input impedance Ideal op-amp is not supposed to draw any input current

Zero output impedance The voltage between terminal 3 and ground will always

be equal to A(V2-V1)

Fig. 2.3 Equivalent circuit of the ideal op amp.



Characteristic of the Ideal Op-AmpCharacteristic of the Ideal Op-Amp

Zero common-mode gain or, equivalently, infinite common-mode rejection Op-amp responds only to the difference signal V2-V1

and hence ignores any signal common to both inputs.

i.e., If V1=V2=1V, then the output will be zero.

Infinite open-loop gain A Gain A is called the differential gain

Infinite bandwidth Ideal op-amp will amplify signals of any frequency

with equal gain.



2.1.3 Differential and Common-Mode Signals2.1.3 Differential and Common-Mode Signals

Differential input signal Vid Common-mode input signal VIcm

Figure 2.4 Representation of the signal sources v1 and v2 in terms of their differential and common-mode components.



2.2 The Inverting Configuration2.2 The Inverting Configuration

A

00 v

R i

1) 즉 두 input 차이에 의해서만 증폭되며 이면 어떠한 voltage 가 공급되거나 이다 .

2) 3) 4)

21 v-v 21 vv

R0

Figure 2.5 The inverting closed-loop configuration.



Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.

Equivalent circuit



• 만약 Vo 가 어느 일정한 값을 가지면 Vx=V2-V1=Vo/A = 0 , • That is, because the gain A approaches infinity, V1 =

V2• Virtual short circuit means that whatever voltage is at

2 will automatically appear at 1 because of the infinite gain A

• Virtual Ground:• Terminal 2 is connected to ground; thus V2=0 and

V1=0.• 터미널 1 을 Virtual ground 되었다고 말한다 .

21210

R

v

R

vii oI

12 R

v

R

v Io 1

2

R

R

v

vG

I

o G : closed-loop gain

See pp. 69.

Vo = - R2/R1 VI

1) 만약 가 어느 일정한 값을 가지면 , 그러나 이므로 전류는 흐르지 않는다 .

이를 Virtual Ground(Virtual Short Circuit)Virtual Ground(Virtual Short Circuit) 라고 부른다 .

iR

ov 000

V

A

VVX



2

00

1

0

2

0

1210

RAv

v

RAv

v

R

Vv

R

vvii

IxxI

)()111

(21

1120

12210

1 ARR

RARRv

R

v

ARRARv

R

v II

2) 만약 이면 AA

vvx

0

ARRR

R

RARR

ARR

Rv

vG

I /)1(1)(

1

1

2

1

2

112

21

1

0

2.2.2 Effect of Finite Open-Loop Gain2.2.2 Effect of Finite Open-Loop Gain

Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.

Closed-loop gain

See pp. 71

Percentage error 1

)1(

1

)1(1

)1(

121

2

1

2

RRA

ARR

ARR

G

GG

ideal

practicalideal


INHA Univ.INHA Univ.Example 2.1Example 2.1

Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.

See pp. 72

Percentage error

2.1) R1 = 1 ㏀ , R2 = 100 ㏀

0.099999.900.1-0.10%99.90105

0.099999.000.1-1.00%99.00104

0.090890.830.1-9.17%90.83103

V0/AV0VII G IA

100)/(

)/(

12

12

RR

RRG


INHA Univ.INHA Univ.2.2.3 Input and Output Resistances2.2.3 Input and Output Resistances

vIRi = R I - (R 2 / R 1 ) * v I

To avoid the loss of signal strength, voltage amplifier are required to have high

input resistance. (Section 1.5)

Fan-out 을 크게 하기 위하여 를 크게 하면 도 비현실적으로 크게

하여야 한다 . 최고 10 ㏁ 이상이면 전류가 너무 적고 현실적이지 못하다 .

=> Solution: Example 2.2

0

11

out

I

I

I

Iin

R

RRv

v

i

vR

iR 2R


INHA Univ.INHA Univ.Example 2.2: pp. 73Example 2.2: pp. 73

Figure 2.8 Circuit for Example 2.2. The circled numbers indicate the sequence of the steps in the analysis.

Virtual ground 개념을 사용하면

11 R

vi I

324

04 // RRR

vi

32

3

324

02 // RR

R

RRR

vi

,21 이므로ii

324342

3

32

3

32

324

0

1 RRRRRR

Rv

RR

R

RRR

Rr

v

R

v oI

)1(2

4

3

4

1

2 R

R

R

R

R

R

v

v

I

o

( R1=1 ㏁ , R2=1 ㏁ , R4=1 ㏁ , R3=10.2 ㏀ 이면 = -100 이

된다 . )


INHA Univ.INHA Univ.2.2.4 An important Application2.2.4 An important Application - The Weighted Summer - The Weighted Summer

Figure 2.10 A weighted summer.

See pp. 76

)( 22

11

0

2

2

1

121

nn

fff

fn

nn

vR

Rv

R

Rv

R

Rvo

R

V

R

V

R

V

R

Viiii

만약 이면 fn RRRR 21

)( 210 nvvvv


INHA Univ.INHA Univ.2.3 Noninverting Configuration2.3 Noninverting Configuration

Fig. 2.12 The noninverting configuration.

Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is indicated by the circled numbers.


INHA Univ.INHA Univ.Voltage FollowerVoltage Follower

Fig. 2.14 (a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit model.

Unity-gain amplifier (or Voltage follower) R2=0 and R1=

VO=VI, Rin= , Rout=0

10

111

2

R

R

v

v

I

o

Io vv


INHA Univ.INHA Univ.2.4 Difference Amplifiers2.4 Difference Amplifiers

Figure 2.16 A difference amplifier.

1

1

243

4

R

vvi

vRR

Rv

21

21

43

32

2121

1 11

RR

RR

RR

Rv

RRv

R

v

R

v o

ov

만약 1/1

/1

43

21

RR

RRvo ov이면

in

dCM

CMd

R

vv

vv

vvvv

21

12

2

2R

vvo

1243

21

1

2

/1

/1vv

RR

RR

R

R

121

2 vvR

R

212 vv

2d

CMv

v

i

vv 12



Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.



Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain Acm ; vO / vIcm.



Fig. 2.19 Finding the input resistance of the difference amplifier for the case R3 = R1 and R4 = R2.



The differential open-loop gain of an op-amp is finite and decreases with frequency.

Although the gain is quite high at dc and low frequencies, it starts to fall off at a rather low frequency (10 Hz in Fig. 2.22)

Uniform -20-dB/decade gain rolloff is typical of internally compensated op-amps.

2.5 Effect of Finite Open-loop Gain and 2.5 Effect of Finite Open-loop Gain and Bandwidth on Circuit PerformanceBandwidth on Circuit Performance

Figure 2.22 Open-loop gain of a typical general-purpose internally compensated op amp.

Consider some of the important nonideal properties of the op-amp.

Frequency Dependence of the Open-Loop Gain


INHA Univ.INHA Univ.2.5 Effect of Finite Open-loop Gain and 2.5 Effect of Finite Open-loop Gain and Bandwidth on Circuit PerformanceBandwidth on Circuit Performance

Figure 2.22 Open-loop gain of a typical general-purpose internally compensated op amp.

)(

/1)(

jwA

ws

AsA

b

o

jw

wAjwAwwif bo

b )(

bt wAw 0

)()()( jwAs

wsA

jw

wjwA tt

unit gain bandwidth

b

o

wjw

A

/1

f

f

w

w tt


INHA Univ.INHA Univ.2.5.2 Frequency Response of Closed-Loop 2.5.2 Frequency Response of Closed-Loop AmplifiersAmplifiers

)/1/(1

1

/

)/1/()1(

11

/

)(

)(

/)/1(1

/

)(

)(

12

12

121

2

12

12

12

RRws

A

RR

RRws

RR

A

RR

sv

sv

ARR

RR

sv

sv

toto

i

o

i

o

dBw3

dBt ww

R

Rif

38

1

2

10

10

Figure 2.23 Frequency response of an amplifier with a nominal gain of +10 V/V.

Inverting amplifier

From Eq. (2.5)

12 /1 RR

wt

srad /11

108


INHA Univ.INHA Univ.Noninverting

)/1/(1

/1

)(

)(

/)/1(1

/1

12

12

12

12

RRwsRR

sv

sv

ARR

RR

v

v

t

I

o

I

o

10

1010

1

8

38

2

1

dBt ww

R

Rif

20dB

w3b

From Eq. 2.11

dc gain = 1+R2/R1

srad /107



2.6 Large-Signal Operation of Op-Amps2.6 Large-Signal Operation of Op-Amps Study the limitations on the performance of op-amp

circuits when large output signals are present. Output Voltage Saturation

Power supply 가 ±15V 시 output voltage 가 ±13V 에서 saturate 되면 ±13V 를 rated output voltagerated output voltage 라고 부른다 .

Figure 2.25 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at ±13-V output voltage and has ±20-mA output current limits. (b) When the input sine wave has a peak of 1.5 V, the output is clipped off at ±13 V.



Slew RateSlew Rate

0

1

2

12

|)1(

)1/(1

1

tt

otwo

t

I

o

dv

dvSReVv

RR

ws

RR

v

v

t

Figure 2.26 (a) Unity-gain follower. (b) Input step waveform. (c) Linearly rising output waveform obtained when the amplifier is slew-rate limited. (d) Exponentially rising output waveform obtained when V is sufficiently small so that the initial slope (vtV) is smaller than or equal to SR.

Slew rate limiting: specific maximum rate of change possible at the output of a real op-amp

=> Slew Rate (SR)

sVwt /

tws1

1



2.6.4 Full-Power Bandwidth2.6.4 Full-Power Bandwidth Op-amp slew-rate limiting can cause nonlinear

distortion in sinusoidal waveforms

wtVwdt

dvwtVV i

IiI cossin

SRVw i

만약 이면 output waveform 이 Distorted 된다 .

Figure 2.27 Effect of slew-rate limiting on output sinusoidal waveforms.



o

oM

oM

V

V

SRf

SRVw

max

max

2

fM : full-power bandwidth in op-amps data book

- slew-rate limiting 에 기인하여 Op-amp 의 rated output voltage 와 같은 amplitude 를

가지고 있는 output sinusoid 가 distortion 을 보여주기 시작할 때의 주파수

Exercise 2.22 Rated output voltage = 10v, SR= 1V/us sV /1

V

sVfM 102

/1

만약 이면Mff 5

M

Mo f

fVV

510

At a frequency higher than M, the maximum amplitude of the undistorted output sinusoid

w

wV Momax

V2

KHz9.15



2.7 DC Imperfections2.7 DC ImperfectionsOffset Voltage

VOS (Offset Voltage)

: Output 을 zero 로 만들기 위한 input voltage : 내부소자의 불균형에 의해서 발생하며 온도에 따라 변화한

다 . VOS : generally-purpose op amp 에서 Vos 는 1 ~ 5mV

Op-amp data sheets specify typical and maximum values of Vos at room temperature as well as the temperature coefficient of Vos (usually in

d CvdTdVos/:~/

Figure 2.28 Circuit model for an op amp with input offset voltage VOS.

Figure 2.29 Evaluating the output dc offset voltage due to VOS in a closed-loop amplifier.

Output dc voltage



oV

osV 가 DC 이므로

Signal 이 low frequency 인 경우 사용불가

oso VV

Figure 2.31 (a) A capacitively coupled inverting amplifier, and (b) the equivalent circuit for determining its dc output offset voltage VO.

Capacitively coupled amplifierCapacitively coupled amplifier

1

2

11

Rjwc

RVos


INHA Univ.INHA Univ.Input Bias and Offset CurrentsInput Bias and Offset Currents

Figure 2.32 The op-amp input bias currents represented by two current sources IB1 and IB2.

(Input Bias Current) : input 이 zero 일 때 흐르는 input 전류

(Input Offset Current) : input 이 zero 일 때 흐르는 input 전류의 차이

221 BB

BII

I

21 BBos III



)2(/1

,0

))/1((

)1()/(

21

21

12

230

1232

21

1321232

RR

RR

RR

rRVif

RRRRIV

IIIif

RRIIRRIV

Bo

BBB

BBBo

oV식 (1) 에 식 (2) 를 대입하면 ,

Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.

Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R3.


INHA Univ.INHA Univ.2.8 Integrators and Differentiators2.8 Integrators and Differentiators

1) The Inverting Integrator

t

i

I

i

dtvRC

dv

dt

dvC

R

Vdt

dvCi

R

Vi

10

0

01

1

1ii

Frequency 특성

oi

o

wjwjwCRR

jwC

Z

Z

v

v 111

1

2 CR

w1

0

Figure 2.39 (a) The Miller or inverting integrator. (b) Frequency response of the integrator.


INHA Univ.INHA Univ.2) The Op Amp Differentiator2) The Op Amp Differentiator

dt

dvRCV

R

v

dt

dvCi

i

i

0

0

Frequency 특성

CRw

10 o

i

O wjwjwCRjwC

R

V

V

1

Figure 2.44 (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR.

Documents

EE141 Microelectronic Circuits Microelectronic Circuits Ch.2. INHA Univ. 전자회로 1 Chapter 2: Operational Amplifiers 인하대학교 정보통신공학부 2008 년 2 학기