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Extending Rocket Chip with Verilog Peripheral IPs
Wei Song (宋威)Former hardware designer for lowRISC (v0.1 – v0.4)
8th September, 2018
lowRISC Project
• lowRISC is a not for profit organization from the University of Cambridge.– Provide open-source and free SoCs.
– Linux capable.
– Highly customizable.
– Based on Rocket-chip (RV64G).
– Do not enforce the use of Chisel.• Encapsulated Chisel islands of Rocket and caches.
• SystemVerilog top-level and interconnects.
• SystemVerilog AXI interfaces for peripheral IPs.
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lowRISC SoC
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Today’s topic:A generic and extendable AXI interface.
Rocket’s Way of Adding Peripherals
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• Each peripheral is wrapped by a TileLink Node, either an AXI4Port or a dedicated TLNode.
• The peripheral’s parameter is back-
propagated to each L1 cache and the
global device tree.
• L1 cache can check IO access
violations accordingly.
• Example memory map:
bootrom: 0x00000000 – 0x00004000 RXRTC: 0x10000000 – 0x10004000 WRuart: 0x10004000 – 0x10008000 WRbram: 0x20000000 – 0x20800000 WRX
• Access to 0x10009000 would cause a synchronous exception in L1 $.
What lowRISC Expects
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• A single AXI port is exposed.
• Peripherals can be attached to this
single AXI bus using Verilog.
• Peripherals’ parameters are still back-
propagated to the global device tree
and all L1 $.
• Using AXI4MMIOPort provided by Rocket-chip:
bootrom: 0x00000000 – 0x00004000 RXRTC: 0x10000000 – 0x10004000 WRAXI: 0x20000000 – 0x40000000 WRX (shared by UART and BRAM)- UART 0x20000000 – 0x20004000 WR- BRAM 0x30000000 – 0x30800000 WRX
• Access to 0x20009000 would NOT cause any exception in L1 $!
The Problem
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• The AXI4MMIOPort is by default represented by a single node in the device tree and address map.
• To use this node, end user needs to:– Manually calculate the combined address map for the IO bus.
– Manually allocate interrupt lines.
– No direct method to add device into the generated device tree.
• Our solution:– Extend the diplomacy package to implement an AXI4VirtualBusNode
which is the root of a virtual tree representing the IO bus.
– This AXI4VirtualBusNode can automatically derive the parameters, add nodes in the device tree and connect interrupts.
– It also produces an AXI4 port like the AXI4MMIOPort for the external Verilog peripherals.
Overview of Diplomacy
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• Diplomacy is a framework for negotiating the parameterization of protocol implementations.
• Compile time negotiation of parameters.• Every agent is a diplomacy node.• Node is a software entity rather than a real hardware module.
Virtual Bus
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• AXI4VirtualBusNode:Produce an AXI port to the external Verilog and act as the root diplomacy node for the external AXI bus.
• AXI4VirtualSlaveNode:For each peripheral added to the global configuration, the SoC generator adds a slave node accordingly.
• The virtual diplomacy tree back-propagates address map, interrupts for the global device tree similar to normal diplomacy nodes.
Implementation of Virtual Nodes
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• TileLink– MixedNode is the common base class
• (BaseNode, InwardNode, OutwardNode) > MixedNode
– Bus(crossbar)• MixedNode > MixedNexusNode > NexusNode > TLNexusNode
– Peripheral device• MixedNode > SinkNode > AXI4SlaveNode
• lowRISC extension– VirtualNode is the common base class
• (BaseNode, InwardNode, OutwardNode) > VirtualNode• Remove the bundle connection
– Bus(port)• VirtualNode > VirtualBusNode > AXI4VirtualBusNode• Produce a port
– Peripheral device (diplomacy node only)• VirtualNode > VirtualSlaveNode > AXI4VirtualSlaveNode
Global Configuration
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// define a peripheralcase class ExSlaveParams(
name: String,device: () => SimpleDevice,base: BigInt,size: BigInt,resource: Option[String] = None,interrupts: Int = 0,burstBytes: Int = 64, // needs to be set >= 64readable: Boolean = true,writeable: Boolean = true,executable: Boolean = false
)
// a collection of all Verilog peripheralscase class ExPeriperalsParams(
beatBytes: Int,idBits: Int,slaves: Seq[ExSlaveParams]
)
Define the parameters of a single peripheral
Collect all peripherals in a global object
Chip Generator
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trait HasAXI4VirtualBus extends HasPeripheryBus {val mmio_axi4 = AXI4VirtualBusNode(…)
p(ExPeriperals).slaves.foreach( d => {val slave = AXI4VirtualSlaveNode(Seq(AXI4SlavePortParameters(slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(d.base, d.size - 1)),resources = d.resource.map(device.reg(_)).getOrElse(device.reg),…
)),beatBytes = p(ExPeriperals).beatBytes
)))slave :*= mmio_axi4
if(d.interrupts > 0) {val intnode = IntInternalInputNode(…)ibus.fromSync := intnode
})
mmio_axi4 := AXI4Buffer()(AXI4UserYanker()(AXI4Deinterleaver()(AXI4IdIndexer(p(ExPeriperals).idBits)(
TLToAXI4(p(ExPeriperals).beatBytes)(pbus.toVariableWidthSlaves)))))}
AXI port
Generate virtual node for each peripheral
connect port
Adding a UART
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class LoRCCoreplexModule[+L <: LoRCCoreplex](_outer: L) extends RocketCoreplexModule(_outer)
with HasRTCModuleImpwith HasMasterAXI4MemPortModuleImpwith HasAXI4VirtualBusModuleImpwith HasSlaveAXI4PortModuleImpwith HasPeripheryBootROMModuleImp
class WithUART extends Config(Parameters.empty) {SlaveDevice.entries += ExSlaveParams(
name = "uart",device = () => new SimpleDevice("serial",Seq("xlnx,uart16550")),base = 0x41002000,size = 0x00002000, // 8KBinterrupts = 1
)}
class LoRCNexys4Config extends Config(new WithUART ++ new WithBootRAM ++ new WithNBigCores(1) ++ new LoRCBaseConfig)
Add VirtualBus
into the cake
pattern
Write a
configuration
class for the
UART
Use the UART
configuration
Conclusions
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• Diplomacy is a powerful software package to enable compile time parameter negotiation, much powerful than the parameters in SystemVerilog.
• A diplomacy node is not necessarily attached to a Chisel hardware module.
• By extending the diplomacy package with some extension in theRocket-Chip generator, we can easily support automatic device tree generation for Verilog peripherals.
– Diplomacy: 190 lineshttps://github.com/lowRISC/lowrisc-chip/blob/update/src/main/scala/diplomacy/VNodes.scala
– Rocket-Chip generator: 300 lineshttps://github.com/lowRISC/lowrisc-chip/tree/update/src/main/scala/lowrisc
Thank You!
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