finalpdfc3pu

7/27/2019 finalpdfc3pu

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C3PU

TEAM LEADER: IVAN SOVI

LUKA KOVA

SIMON COSSART

FILIP KERI

PROCCESSOR DESIGN FOR RECONFIGURABLE PLATFOR


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WHAT ARE PROCESSORS?

Processors are devices which can processbinary information with basic operations,they are in most of our electronic devices.They are made from several maincomponents like ALU, CU, Registers...


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WHAT ARE SOFT-CORE AND HARD-COR

PROCESSORS?

Soft-Core processor is a processorwhich can change their logic circuits,

their main advantages are:

Limit speed 250 MHz and less

Can be multi-core

Reprogrammable

Their main disadvantage is their

speed, they are slower.

Hard-Core

processors are processors thatheir logics circuits engraved; they have

advantages compared to the Soft-Core:

Fast speed from 100MHz to 1GHz o

Cannot be modified

Optimized


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FPGA

Field Programmable Gate Arrays

Can be reconfigured Based around a matrix of configurable logic blocks (CLBs)

connected via programmable interconnects


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CLB Configurable Logic Block

IOB Input/Output Block

Block RAM Multipliers (general purpose)

DCM Digital Clock Management

Interconnect network

Configuration logic


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CPU COMPONENTSSEQUENTIAL

The basic registers are: The Single register The Tri-register The Register array


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CPU COMPONENTSCOMBINATIONAL

The basic components are: The ALU(Arithmetic-Logic

Unit) The Shifter The Comparator


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CPU ARCHITECTURESIMPLIFIED MODEL

Picture taken from: http://www.spring-alpha.org/images/module_01/talk/mf_vnarch.png
http://www.spring-alpha.org/images/module_01/talk/mf_vnarch.pnghttp://www.spring-alpha.org/images/module_01/talk/mf_vnarch.png


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C3PU ARCHITECTURE

RAM


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INSTRUCTIONS

ALU operations opcode

AND c = a and b 01001

OR c = a or b 01010

NOT c = not a 01100

XOR c = a xor b 01011

ADD c = a + b 01101

SUB c = a b 01110

INC c = a + 1 00111

DEC c = a 1 01100

ZERO c = 0 01111

Shifter operations opcode

SHL Shift 1 bit tothe left

10000

SHR Shift 1 bit to

the right

10001

ROTR Rotate 1 bit

to the right

10010

ROTL Rotate 1 bit

to the left

10011

C

NO

LO

M

LOJM

JM

EN

00011_00000_001_010

opcode


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ASSEMBLY

Our languageAssembly

( C++ & Python )Machine c


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CONTROL UNIT

Unit which coordinates componentsin computer system

It fetches the code of all of theinstructions in the program.

This is used to decode theinstructions that make up a program

when they are being processed, andto determine in what actions must betaken in order to process them


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PIPELINE

RESET

FETCHDECODE

E

Puts the zero valuein all the registers

Retrieves commands fromRAM on the address

from PC registerChecks the opcode

of retrieved command

Perform


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HOW A COMMAND IS EXECUTED IN OUR


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RESULTS

We made a code for our processor to make a Fibonacci sequence

Fibonacci sequence: f[ i ] = f[ i-1 ]+f[ i-2 ] where f[ 0 ] = f[ 1 ] = 1

( 1, 1, 2, 3, 5, 8, 13, 21, 34...)

assembly simulation


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RESULTSSIMULATION

Fibonnacci sequence


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CONCLUSION

Our goal was to make a CPU and we succeeded

We learned a lot of new things, especially about VHDL

Future -> execution on real hardware

Everyone who has an FPGA board can use our processor scode is published on github.com


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QUESTIONS?

Documents

finalpdfc3pu