25. Flip-flops

Flip-flops are basic memory elements in the sequential circuit.

The RS flip-flop may be in the form of cross-coupled NOR gates or NAND gates, as shown below, although the meaning of the inputs changing a bit.

Types of flip-flops: Each of them is used to store one bit of data.

o RS flip-flop (Reset Set)o D flip-flop (Data)o JK flip-flop (Jack Kilby)o T flip-flop (Toggle)

Characteristic table for each flip-flop

A. RS flip-flip

The characteristic table summarizing the behavior of the RS lip-flop is shown below

The characteristic table may be re-drawn in the form similar to the K-map which is shown below

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Thus, the next output value may be written as the following equation and it is called the characteristic equation for the RS flop-flip.

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Clocked R-S Latch (flip-flop)

The clocked operation RS latch now has 3 inputs and 2 outputs.

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B. D flip-flip

The state table summarizing the behavior of the D flip-flip is shown below

The characteristic table is shown below

Thus, the next output value (Q) may be written as the following equation

This equation is called the characteristic equation of the D flop-flip.

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C. JK flip-flip

The characteristic table summarizing the behavior of the JK flip-flop is shown below

The characteristic table is shown below.

Thus, the next output value (Q) may be written as the following equation

This equation is called the characteristic equation of JK flop-flip.

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D. T flip-flip

The state table summarizing the behavior of the T-flip-flop is shown below

The characteristic table is shown below

Thus, the next output value (Q) may be written as the following characteristic equation

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Clock inputs

We consider the clock input which is always present in flip-flops.The clock input determines when the flip-flop “listens” to the inputsWith respect to the clocking behavior of the flip-flops, three types of memory elements (flip-flops) will be considered:

a) Latchesb) Mater-slavesc) Edge triggers

Latches

The latch, or the level-triggered D flip-flop, is shown below.

The primary feedback lines resulting in “memory” are in the output R-S network. The “steering” network at the input forces Q to follow D while C=1, but traps the

last D value when C=0. The input D is connected to both inputs to the steering NAND network on the left,

with the lower input complemented. This way, the RS flip-flop on the right will never have the forbidden input of

R=S=1. Note also the clock input

The above flip-flop is called D flip-flop. It is particularly called the “level-triggered” D flip-flop. It is level-triggered because the flip-flip responds to the input D only while the

clock (C) level is high (or 1)

In summary , in the level triggered D flip-flop, if C=0, the flip-flip is in “store” state, i.e., no change.

If C=1, and if D=1, then the output Q becomes 1. If C=1, and if D=0, then the output Q becomes 0. In other words, the output Q copies the input D while C=1

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The block diagram of D flip-flop

Positive level-triggered D flip-flop Negative level-triggered D flip-flop

The positive level-triggered D flip-flop (left figure), the output changes only during C=1, coping the input value.

In the negative level-triggered D flip-flop (right figure), the output changes only during C=0.

The above latch (level-triggered D flip-flop) can be minimized as shown below. It is 7475.

7475 D flip-flopMaster-Slaves

Consider the attempt to construct a so-called JK flip-flop as shown below.

Provided JK=0, Q will set if J=1 or C=1, or reset if K=1 on C=1. If J=k1 on C=1, then the intent is for the output to flip to its opposite state.

Instead the circuit oscillates, continually reversing its sense. In order to break the loop, we create to copies of the RS as shown below.

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Note that the master is loaded if C=1, and the slave is loaded if C=0.

Edge Triggering

This is the most powerful type of clock control because the JK master slave of the previous example suffers from the flowing problem.

While the master stage is enabled, it listens continually to J and K. Hence, any spurious J or K signal will set or reset the master.

For example, if a pair of unintentional values J=1 and K=0 were listened just before the master clock went low and the corresponding incorrect output Q=1 resulted, it is called the “one’s catching” problem.

We desire a circuit that will take a “snap-shot” of these inputs at a certain instant defined by a transition (or edge) of a clock.

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T flip-flop

The edge-triggered toggle (T) flip-flop, a variant of the edge-triggered D flip-flop is shown below.

This edge-triggered T flip-flop requires only an external wire connection. Note that this T flip-flop is a little different from the T flip-flop described at the

beginning of this section. The flip-flop below is always toggled as soon as it is triggered, while the former T

flip-flop toggles only when the T inputs is 1. Unless otherwise stated, we will use the former T flip-flop as our ordinary T flip-

flop.

The characteristic table of the T flip-flop is shown below.

Ex) For the following positive edge-triggered D flip-flop, complete the following timing diagram. Assume that initially the flip-flop was cleared to zero. Assume also that there is a short propagation delay (about one fifth the duration of clock pulse) for the flip-flop. You should show the propagation delays on the timing diagram.

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Ex) For the following negative edge-triggered T flip-flop, complete the following timing diagram. Assume that initially the flip-flop was cleared to zero. Assume also that there is a short propagation delay (about one fifth the duration of clock pulse) for the flip-flip. You should show the propagation delays on the timing diagram.

Ex) Implement a positive edge triggered JK flip-flop using a positive edge triggered D flip-flop and a few gates.

We first recall the characteristic table of the JK flip-flop, along with its characteristic equation.

We then recall the characteristic equation of the D flip-flop is

By combining the two equations, we obtain the following equation:

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The resulting edge-triggered JK flip-flop, packaged as 74109, is shown below:

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