I. INTRODUCTION

Infrared modulated signals [1] are widely used for short range communication [2]. They are an efficient tool for data exchange when errors are not a critical factor [3]. People use this sort of physical phenomena to communicate with the appliances located nearby to send commands and sometimes limited size data. Most of these signals are sent from a unit called “remote control unit”. In the receiving side, these signals are filtered, conditioned, and decoded in such a way to recover the data embedded in them. One of the important factors that determine the efficiency of data transfer is the availability of what so called “a line of sight” between the sender and the receiver units. This means that the data sent by the transmitting unit, cannot reach the receiving unit if there is any obstacle between the two. This is quite obvious, because the infrared is nothing but light rays transfer in straight lines.

II. ALGORITHMIC STATE MACHINES

The concept of algorithmic state machine [3] [4] is originally based on sequential circuit design methodology. It is a powerful tool to design digital circuits whose next state depends on the present state and the present inputs applied to the circuit. In this method we assume that the circuit has some memory that retains information about the present state. The said memory is referred to as state registers. This information, together with the present input will decide the next state transition of the circuit. For a certain present state, there might be two or more different next states [4]. This is all governed by the input signal(s) applied to the circuit. In this paper we consider the IR sensor output signal to be the present input to the ASM detector.

III. CODE DETECTOR CONSTITUENTS

Besides the ASM detector unit, we need another circuit that converts the infra red based signal into a train of pulses ready for digital processing. The one that we choose in this

paper is TSOP1140 integrated circuit. It is the Vishay Telefunken

"Enhanced Data-Rate" 40 KHz infrared detector module. This detector module can be used for applications operating at 40 KHz, at baud rates up to 3200 bps, and includes a visible light cutoff resin to help eliminate interference from visible light sources. These are prime choice IR photo modules for infrared serial communications. It has a PIN diode and preamplifier assembled on lead frame, the epoxy package is designed as IR filter. The demodulated output signal can directly be decoded the IR-D15 infrared receiver IC.

Besides the infrared unit, the overall design includes a number of supportive modules to aid the ASM unit. These modules include timers, counters, shift registers, etc. The final design is to be converted into a binary file and burned into the Xilinx-Spartan XC3S1000 chip. The Xilinx Spartan XC3S100 is Field-Programmable Gate Array (FPGA) [7]. It is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. It is a member of a family that offers densities ranging from 50,000 to five million system gates. The Spartan-3 family builds on the success of the earlier Spartan-III family by increasing the amount of logic resources, the capacity of internal RAM, the total number of Input and Output channels, and the overall level of performance as well as by improving clock management functions. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications; including broadband access, home networking, display/projection and digital television equipment.

The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs [6] [10]. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

FPGA Based IR Code Recognizer

ALGHAMDI ALI S. 1, 2, 3, Student Member, IEEE & KENAYA RIYADH L.1, Member IEEE, IAENG 1Department of Electrical and Computer Engineering

Lawrence Technological University Southfield, MI 48075, U.S.A

2Saudi Red Crescent Authority 3Ministry of Higher Education, Kingdom of Saudi Arabia

Email: {rkenaya, aalghamdi}@ltu.edu

Abstract: -The advent of FPGA technology made it easy for the engineers worldwide to design, implement, and test giant digital systems. In this research we try to come up with a system that recognizes the infra-red digital signal that is emitted from the SONY 15-2113 infra-red remote control unit. A synchronous state machine system (ASM) is designed to read the IR signals and analyze the data stream and come up with identification to the key pressed. Data conversion and analysis tasks are all assigned to the ASM unit. The ASM unit is not a standalone system, there are other supportive unties like timers and counters attached to it to organize and synchronize its actions and operations. Index Terms— Remote control signals, data recognition, algorithmic state machines, ASM, finite state machine, FSM, FPGA, VHDL..

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IV. SYSTEMS BLOCK DIAGRAM

Fig.1 shows the overall system block diagram. The IR sensor is sitting at the left of the system, whereas the ASM module occupies the center. The said ASM module is implemented via programming the above mentioned XC3S1000 chip which is already mounted on a Digilent Spartan 3-1000 development board.

The development board provides us with necessary indicators that give us a continuous track of the ASM state variables and input/output signal status for diagnosis purposes. It may happen more than once throughout the design and testing processes that the ASM gets stuck in one of the sequential states. To diagnose the said problem, we should have a good state tracking technique to get a clue about the condition(s) that are forcing the state machine to get locked at a certain state. The development board is also equipped with a number of toggle switches that enables us to apply test signals to imitate certain input(s) or feedback variable(s).

The external infrared signals could be generated by any infrared data transmitter. In this paper, the information source selected is the SONY 15-2113 remote control unit.

SONY 15-2113Remote control unit

TSOP1140Infrared sensor

Digilent Spartan 3-1000 Development Board

Xilinx-Spartan XC3S1000

FPGA

Data Port

4 Digit Seven Segment Diplay

8-bit Toggle Switch Array

Memory Module

8-bit LED Array

The Digilent development board has many more modules to show, but what is shown fig.1 is only what our research requires. The 8-bit toggle switch array appears unconnected because it is not used during the normal operation. The use of said toggle switches is limited to troubleshooting and diagnosis purposes.

V. SONY 15-2113 SIGNALS

In this paper we care about detecting the numeric keys 0-9, CH+, CH-, Vol+, and Vol-. The ASM, however, could be expanded to become capable of detecting the rest of the functional keys in the remote control unit. Figs 2.1 to 2.14 show the oscilloscope snapshot of the keys to be detected. The pictures represent the train of ones and zeros that each key generates when pressed. They are simply the messages generated once one of the keys is pressed. Each time division is 2.5 ms and each voltage division is 2 volts. The signal is repetitive, which means that the message repeats itself after each transmission as long as the key is pressed. One can also tell that there is a long period of high level (logic 1) between a transmission and another. Also, there are no two consecutive ones, but we can easily detect more than two consecutive zeros in every transmission. All The above mentioned features give us an idea of what would be the shape of the suggested ASM and how would it detect the key pressed once it receives its message from the infra-red sensor.

Fig 1: ASM based IR code recognizer block diagram.

Fig 2.1. Key 0

Fig 2.2. Key 1

Fig 2.3. Key 2

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VI. ASM DETECTOR ALGORITHM AND STATE DESCRIPTION

In this section we present the detection theory and the strategy applied to reconstruct the data from the received stream of pulses. The principle of detection is based on evaluating the time period for which the received signal stays high. To achieve this goal; we need a precise and fast oscillator to measure the life time of each one of the pulses in the received IR signal. The said oscillator would be providing us with a number of ticks per unit time. This number would be a good description for the pulse life. We can easily conclude that the pulse life is measured by counting the number of oscillator ticks rather than measuring a real time.

Fig 2.4. Key 3

Fig 2.5. Key 4

Fig 2.6. Key 5

Fig 2.7. Key 6

Fig 2.8. Key 7

Fig 2.9. Key 8

Fig 2.10. Key 9

Fig 2.11. Channel up

Fig 2.13. Volume up

Fig 2.14. Volume down

Fig 2.12. Channel down

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The state machine we have designed in this paper consists of 7 states as shown in fig. 3. There is also a number of counters, registers, and delay lines. We herby list the states and the action associated with each one.

State S1: This is the reset state. It is the initial state and the circuit stays in it as long as there is no transmission. The ASM also ends up with this state when it finishes analyzing the current received code. X is the input signal to the ASM and it is the output from the IR detector. When the ASM gets

into this state there will be a number of events generated and a number of state outputs are activated. The ASM activates RDY (ready) signal to inform the external devices that are connected to it (if any), that it is waiting for a new IR transmission and they can start it at any time. COUNT is a 6-bit counter used to count the oscillator’s ticks and it is reset in this state. TMRCNT is another counter whose width is 20 bits.

Fig 3. State diagram of the infra red code detector.

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STAT is the state variable register and used for identifying the current state of the ASM. This register is of paramount importance during the early stages of the design. CLR is the asynchronous reset signal. It is used to initialize the ASM and force it to be in S1 state whenever it is activated. It is apparent that this signal is activated via a push button that initializes the whole system.

Once the transmission starts, the IR sensor pulls the X signal down to zero level. The signal stays low for about 2.5ms before it goes up again in accordance with data flow. The ASM, here, transfers from state S1 to S2 and the detection/identification operation starts.

State S2: This state monitors the 2.5ms low interval and makes sure that the received signal is an IR transmission from the SONY 15-2113 remote control unit. Any noise interference or signal from another supply will cause the ASM to go back to its initial state and starts a new detection process. The 2.5 ms time interval is modeled by a constant hexadecimal number of 1C700. In this state TMRCNT counter is incremented every clock cycle and an arrival of a high level signal is continuously monitored. If logic 1 is detected on the line while TMRCNT accumulation is still less than STRT_TMR value, this is considered as premature arrival of data which could be caused by noise or other IR source. The ASM will go back to state S1.

State S4: The ASM arrives to this state coming from S2 when logic 1 level is detected after TMRCNT accumulation has exceeded STRT_TMR value. Only at this point, the received signal is considered as the beginning of the data stream. In this state, the 32-bit register KEYCD_SGNL logically shifts left its old contents and inserts from the right hand side the current applied data item X. X is the current bit applied to the ASM from the IR detector and considered as part of the message being received. COUNT register is incremented every time the ASM reaches this state. TMRCNT register is reset to “00000” at this state.

State S3: The ASM reaches this state coming from S4 as long as COUNT register is less or equal to BITCNTMX (bit count max). BITCNTMX is a constant with value of 1E hex (30 decimal). This value represents the length of the IR signal to be received.

The ASM keeps switching back and forth between S4 and S3 as long as the IR message is being received. A new bit is added to the message train every time the ASM transfers from S4 to S3. TMRCNT is a time constant that represents the bit life in clock cycles. The ASM stays at S3 as long as the bit life has not yet ended.

State S5: The ASM reaches this state from S4 when COUNT value exceeds the constant BITCNTMX i.e. when the message is completely received. In this state, the ASM prepares itself for the next IR message and waits for a time period of STRT_TMR clock cycles. The TMRCNT counter is reset to zero when ASM changes state from S4 to S5. The reset signal for this counter is a conditional output signal. While the ASM is in state S5, the TMRCNT counter is incremented every clock cycle.

State S6: In this state, the ASM circuit analyzes the code collected and identifies the message received. According to comparisons with previously recorded codes, the ASM decides the identity of the key pressed. In this state, if the received code differs from the prerecorded ones, the ASM will go back to its initial state without doing anything. The last received code is simply an incorrect one. SONY 15-2113 IR unit repeats the IR code as long a key is pressed. Having

received an erroneous code, the ASM would still be able to catch the right one in next transmission.

Table 1 shows the hexadecimal codes for each one of the IR codes to be detected in this paper.

Table 1. SONY 15-2113 IR codes

Key Hex Code 0 952A955F 1 AAAA557F 2 95552ABF 3 A5552ABF 4 92AA955F 5 A9552ABF 6 94AA955F 7 A4AA955F 8 92554A8F or

92554AAF 9 AA552ABF Channel Up AA952ABF Channel Down 954A955F Volume Up A54A955F Volume Down 92A54AAF or

92A54A8F One can easily tell that all the keys have one distinct code

except keys 8 and Volume Down; they both have couple of different codes. It is well known that the IR code changes phase depending on the distance between the sender and receiver units. Also, the direction of transmission (the angle by which the remote unit is directed toward the receiving diode) plays an important role in deciding the phase [8] [4]. There is certain angle that makes the received data completely unreadable. The most two affected codes are the codes of Keys 8 and Volume Down. In our experiments, they have exhibited erroneous detection more than the rest of the codes. For these reasons we have programmed state S6 to be able to detect two different codes for each of the above mentioned keys. We have done this after we made sure that none of the codes are duplicative.

State S7: In this state we create four-digit number by concatenating four pressed keys in a row. This would be very useful for a number of applications where more than one key is to be detected to create a pin number or passcode of four digits (or more). One can notice that state S7 is a locked state. This means that the ASM would stay forever in this state as it reached. In fact, the ASM generates a strobe signal to the external hardware in order to inform it that the received code is analyzed and it is ready to start a new detection. It is obvious here that the ASM is a slave machine and needs a master circuit to coordinate its operation with the other systems constituents. The master circuit rests the ASM and takes it back to its initial state S1 by activating the CLR signal. CLR is an asynchronous signal when activated rests the state register to its initial value.

VII. RESULTS

Table 2 shows the results collected from a number of experiments we have run to test the ASM performance. The table shows the percentage error of recognition. All the keys are given the same transmission conditions including and not limited to distance of the remote control unit from the sensor,

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battery power, and transmission medium conditions of humidity, temperature ...etc.

Table 2. Error rate in the detected codes

Key Code Error % Key 1 0 1 0 2 0 3 0 4 1 5 0 6 1 7 0 8 3 9 1 Channel Up 2 Channel Down 1 Volume Up 2 Volume Down 4

VIII. CONCLUSION AND FUTURE WORK

Algorithmic state machine design strategy is an important technique to control certain sequence of events or to reconstruct information from that sequence. In our example, we had to read the information embedded in an IR-based pulse stream. The ASM did play an important role in detecting the beginning, the end, and the information contents of the above mentioned stream. Coordination with other modules in any digital system is made easier through ASM.

Handshaking between system constituents (strobe and acknowledge signals) are generated and received by ASM. The main obstacle, however, that makes this coordination harder and results in system errors, is the lack of synchronization between different units in the digital system and sometimes between different ASM states. Our future plan is to create synchronization bridges between more than one ASM and use the concept of Mater-Slave in creating a hierarchy of tasks in timely matter.

IX. REFERENCES [1] R. E. Haskell and D. M. Hanna, Learning By Example Using VHDL,

Rochester, Michigan: Oakland University, 2007. [2] T. N. Corporation, "Introduction to Fourier Transform Infrared

Spectrometry,"2001.[Online].Available: http://mmrc.caltech.edu/FTIR/FTIRintro.pdf. [Accessed 11 Fab 2011].

[3] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd ed., New York: McGraw-Hill, 2009.

[4] Naouel Moha, Yann-Ga¨el Gu´eh´eneuc, Anne-Franc¸oise Le Meur, Laurence Duchien, Alban Tiberghien, "From a domain analysis to the specification and detection of code and design smells," 19 May 2009. [Online].Available: http://www.naouelmoha.net/paper/FACS09/Moha09-FACS.pdf. [Accessed 11 MAY 2011].

[5] D. B. Schwarz, "Designing Digital Systems with Algorithmic State Machine Charts," [Online]. Available: http://asaha.com/download/zNTkzODQy. [Accessed 11 May 2011].

[6] J. D. Schipper, "Algorithmic State Machines (ASM’s)," June 2007. [Online]. Available: http://freetechebooks.com/download/algorithmic-state-machine-asm-1.html. [Accessed 05 MAY 2011].

[7] Digilent Inc. XUP and Spartan3 Development Boards, http://www.digilentinc.com/. [8] H. Mendenblic and W. Damman, "SIGNAL FPGA

IMPLEMENTATION OF A DIGITAL MODULATOR FOR DVB-S,"

15 MAY 2005. [Online]. Available: www.d-atv.com. [Accessed 13 NOV 2011].

[9] FPGA Design Tutorial, 2001. [10] T. Hanamoto, M. Deriha, H. Ikeda and T. Tsuji, "Digital Hardware

Circuit Using FPGA for Speed Control System of Permanent Magnet Synchronous Motor," in International Conference on Electrical Machines, Wuhan, 2008.

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