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FPGA Four Hour Workshop
InstructorsInstructors
Craig Kief Jim PlusquellicCraig KiefDeputy Director, COSMIAC
Karl Henry
Jim PlusquellicProfessor, UNM
Ui LuuInstructor, JF Drake State
Bassam MatarInstructor, Chandler‐Gilbert
Instructor, [email protected]
Pete LomeliInstructor, Central Arizona
1
Instructor, Chandler Gilbert [email protected]
Instructor, Central [email protected]
IntroductionsIntroductions• Who are you?
• Where are you from?
• Any FPGA experience?• Any FPGA experience?
• What do you want to learn from this?
Why we are hereWhy we are here
The Big Picture
NumbersNumbersNumber of transistors manufactured1019
Average cost of transistor
Number of IC’s produced this year10‐8
11 p y
Nanometer geometries for latest IC’s1011
28Transistors on latest IC’s
283x109
We have incredible resources at our disposal, and they bring an exploding knowledge & skill y g p g gburden.
Technologies in My LifetimeApplication Specific Processors
Technology Gates Tools Processors Languages Focus
1960's Transistors 101
1970's SSI (7400) 102 8‐bit Fortran Algorithms
1980's PALs (22V10) 103 Scripting 16‐bit Pascal Data Structures1980 s PALs (22V10) 10 Scripting 16 bit Pascal Data Structures
1990's CPLDs 104 Schematic Capture 32‐bit C, C+ Objects
2000's FPGAs 106 HDL, synth, analysis Multi‐core C++, Java Threads, Networks
2010's SOCs 109 HLSTs, IP, Cores SOCs C/HDLs? Partitioning, synching
Human Bandwidth Exceeded: Behavioral Design Human Ingenuity Challenged: CAD Tool Lag
We have the hardware butWe have the hardware, but…“Chipmakers are busy designing microprocessors that mostChipmakers are busy designing microprocessors that most programmers can’t program”
David Patterson, IEEE Spectrum 2010
“… the semiconductor industry threw the equivalent of a Hail Mary pass when it switched from making microprocessors run faster to puttingfrom making microprocessors run faster to putting more of them on a chip - doing so without any clear notion of how such devices would in general be programmed.be programmed.
“The hope is that someone will be able to figure out how to do that, but at the moment, the ball is still in the air.”, ,
Courtesy Patrick Lysaght, Xilinx
2,000K
Logic Cells,
tex-
7
Dramatic Capacity Increases
1,000K
Virt
600K
800K 760K
ex-6
200K
400K332K
150K
355K 410KVirt
e
SpartanSpartan--66
Virt
ex-5
Art
ix-7
Kin
tex-
7
65nm 40/45nm 28nm
V A Courtesy Patrick Lysaght, Xilinx
Declining Interest in EE/CS
Declining Enrollments and ec g o e ts a dGraduates in EE/CS
Method: Immersive hands-on design for every student
Students learn more faster and betterStudents learn more, faster, and better with unrestricted access to design tools…
overall learning improves when …overall learning improves when applied design skills taught early;
overall performance improves …overall performance improves when design skills used frequently;
…and they like it*y
*results published in 2008 and 2009 ASEE proceedings
I never teach my pupils; I only attempt to provide the conditions in which they can learn. Albert Einstein
Low‐cost kits and Free CAD toolsLow cost kits and Free CAD toolsfor every engineering student
Terasic DE0Altera Cyclone III
Digilent Basys2Xilinx Spartan 3E
$79p
$59
Terasic DE1Altera Cyclone II
$125
Digilent Nexys2Xilinx Spartan 3E
$99 $125$99
No Lab Required! Students work on real designs No Lab Required! Students work on real designs at a time and place of their choosing
FPGA’s Across the CurriculumFPGA s Across the Curriculum
What is an FPGAA Field Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinatorial functions such as decoders por simple math functions. In most FPGAs, these programmable logic components also include memory elements, which may be simple flip‐flops or complete blocks of memory.
A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer. These logic blocks and interconnects can be programmed after the manufacturing process by the customer so that the FPGA can perform whatever logical function that is neededcan perform whatever logical function that is needed.
Basic Building BlocksBasic Building BlocksEach slice has four outputs Simplified Slice Structure
Slice 0
outputsTwo registered outputs, two non‐registered outputsT BUFT i t d
Simplified Slice Structure
LUTLUT CarryCarry D QCE
PRE
CLR
Two BUFTs associated with each CLB, accessible by all 16 CLB outputs
Carry logic runs
LUTLUT CarryCarry D PRE
Carry logic runs vertically, up only LUTLUT CarryCarry D
QCE
CLR
p yTwo independent carry chains per CLB
What makes up an FPGA?
Groups of Slices make up a CLBmake up a CLB
S 3E A hSpartan‐3E Archtecture
XilinxXilinx
Largest manufacturer of HW Largest manufacturer of HW Develop hardware and softwareUniversity Program discussed laterUniversity Program discussed later
Wh j FPGA d fWhat projects are FPGAs good for
Aerospace & DefenseRadiation‐tolerant FPGAs along with intellectual property for image processing, waveform generation, and partial reconfiguration for SDRs. AutomotiveAutomotive silicon and IP solutions for gateway and driver assistance systems, comfort, convenience, and in‐vehicle i f t i t infotainment. BroadcastSolutions enabling a vast array of broadcast chain tasks as video and audio finds its way from the studio to production and transmission and then to the consumer. ConsumerCost‐effective solutions enabling next generation, full‐featured consumer applications, such as converged handsets, g g , pp , g ,digital flat panel displays, information appliances, home networking, and residential set top boxes. Industrial/Scientific/MedicalIndustry‐compliant solutions addressing market‐specific needs and challenges in industrial automation, motor control, and high‐end medical imaging. Storage & ServerD t i l ti f N t k Att h d St (NAS) St A N t k (SAN) t Data processing solutions for Network Attached Storage (NAS), Storage Area Network (SAN), servers, storage appliances, and more. Wireless CommunicationsRF, base band, connectivity, transport and networking solutions for wireless equipment, addressing standards such as WCDMA, HSDPA, WiMAX and others. Wired CommunicationsEnd‐to‐end solutions for the Reprogrammable Networking Linecard Packet Processing, Framer/MAC, serial backplanes, and more
Who uses themWho uses them
www.fpgajobs.com
Wh th i t tWhy are they important
They have the ability to revolutionize the way that prototyping is done.All i k i k d i Allows companies to get to market quicker and stay in market longer.
DesignDesign
H FPGA j D i d?How are FPGA projects Designed?
There are many different methodolgies for programming (or designing) with FPGAs
H d D i i L (HDL)Hardware Descriptive Language (HDL)VHDLVerilogg
Schematic CaptureC CodeEDKSystem Generator
d lHDLs: VHDL and Verilog
d D i i f d ibi Hardware Descriptive Languages are ways of describing digital logic. They are not a programming language, they are languages for describing hardware and are the they are languages for describing hardware and are the most popular mechanisms for creating FPGA projects
VHDL – VHSIC Hardware Descriptive LanguageVerilog
Which is best?
HDLs: VHDL and Verilog
Hardware Descriptive Languages are not software. They are not programming languages They describe are not programming languages. They describe HARDWARE.
The next few slides are designed to give you the basics of VHDL and enough information to successfully create projects.
VHDL CodeVHDL Code
The title of the article is "Analysis of the programmable logic usage and assurace survey results“ revision 10.1, sept 25,2002Glenn research center, Cleveland, Ohio.Glenn research center, Cleveland, Ohio.
Quote:It is a serious mistake to equate VHDL programming to software. At best it is fi b t f th t t th i 't d f i firmware, but for the most part there isn't a good name for programming FPGA logic. In a high performance design like ours, the minute you forget that you are designing hardware and think you are writing software, you fail.
VHDL CodeVHDL Code
Forest Level View
Entity DeclarationInputs and outputs for FPGA
Entity Declarationp p
std_logic versus std_logic_vector
‐‐ comments: how you enter comments in VHDL
entity BUZZER is port (
DOOR, IGNITION, SBELT: in std_logic;
WARNING: out std_logic);
end BUZZER;DOOR
IGNITION
SBELT
WARNING
Architecture DeclarationArchitecture Declaration
bLab 1 Overview
Provides you with an introduction to the design tools with a schematic capture environment
Obtaining, licensing and serviceObtaining, licensing and service contract with Xilinx
If you decide to go with Xilinx, we can help you the most (with currently available resources)
Register with XUPGet software
l fPay annual feePut one person in charge
Xili D i FlXilinx Design FlowPlan & HDL RTLCreate Code/Budget
HDL RTLSimulation
SynthesizeFunctionalImplement
Create Code/Schematic
Translate
Map
Synthesizeto create netlist
FunctionalSimulation
Place & Route
Attain Timing Closure
TimingSimulation
GenerateBIT File
ConfigureFPGA
ISEISE
ISE is the software used to make the project we are going lto complete.
W ill hi k i l lid d We will cover this package more in later slides and during the practical exercise.
SynthesisSynthesis
XST is a Xilinx tool that synthesizes HDL designs to create Xilinx specific netlist files called NGC files. pThe NGC file is a netlist that contains both logical design data and constraints that takes the place of b h EDIF d NCF filboth EDIF and NCF files.
There are other 3rd party synthesis engines that are There are other 3 party synthesis engines that are very good but not necessary now
ImplementationNetlist Generated
Consists of three phasesTranslate:Merge multiple design files into a single netlist
Netlist GeneratedFrom Synthesis
. . .gMap: Group logical symbols from the netlist (gates) into physical components (slices and IOBs)Pl & R Pl
Translate
Implement
. . .
Place & Route: Place components onto the chip, connect the components, and extract timing data into reports
Map
pAccess Xilinx reports and tools at each phase
Timing Analyzer, Floorplanner, FPGA
Place & Route
. . .g y , p ,Editor, XPower
Device Implementation Place & RouteDesign Flow
SpecificationG t f th d i
Device Implementation Place & Route
SynthesisSchematicCapture
libraries
HDL
Gates of the design ...
netlist
Verification
... are placed ... ... and routed
Simulation0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1
test vectors
I l t ti
Verification
Translate
Fitting/Place & Route
Implementation
Place & Route
Configuration Once a design is implemented, you must create a file that the FPGA can understand
This file is called a bitstream: a BIT file ( bit extension)This file is called a bitstream: a BIT file (.bit extension)
The BIT file can be downloaded Directly into the FPGA
Use a download cable such as Platform USBTo external memory device such as a Xilinx Platform Flash PROM
Must first be converted into a PROM file
Tool Flow 37
b kWebpack
This is the really great benefit to students. Xilinx makes a free version of their ISE software. This means that students can do entire projects at home and only come p j yto the lab to demo. http://www.xilinx.com/ise/logic_design_prod/webpack.htmAltera has a similar product
WebpackWebpack
P t t B dPrototype Boards
Boards range from er ine pensi e (BASYX $ 9) to Boards range from very inexpensive (BASYX ‐ $59) to very expensive (V8000 ‐ $10k). They key is to get the most board you can for the minimum amount of money y ythat will do what you need.Excellent dependability and student tested.Clint Cole storyClint’s website – www.digilentinc.com
LicensingNode Lock (Ethernet versus Hard Drive Serial Number)Node Lock (Ethernet versus Hard Drive Serial Number)Server LicensingStudent versus LabStudent versus Lab
Educational Materials AvailableEducational Materials Available
Clint’s web site www.eecs.wsu.edu/~ee214Digilent website www.digilentinc.comOur XUP site www.ece.unm.edu/vhdlXUP sitewww.cosmiac.orgQuick start tutorials – launch within ISEWhat we are developing!
Educational Materials AvailableEducational Materials Availablehttp://www.digilentinc.com/classroom/realdigital/
Educational Materials AvailableEducational Materials Available
D t d SWDonated SW
Register with XUPRegister with XUPMention working with usDon’t chase releasesDont chase releases
dHardware – How to get it
i i llInitiallySporadicS i biliSustainability
The NSF TeamThe NSF Team
Who we are and what do we do
Beginners and Advanced WorkshopsWe offer a series of free two‐day workshops for instructors and professors to allow them to be able to learn the basics of establishing FPGA programs at their schools
NSF Grant OverviewNSF Grant Overview
Need for Technicians with FPGA ExperienceFPGA Skill Set Required
The Team’s PlanThe Team s Plan
Develop Instructional MaterialTrain Faculty
Developing CurriculumDeveloping Curriculum
Lab1 – Intro ‐ Matar/LuuLab 2 – Basic Logic Gates Matar/LuuLab 3 – Registers and Buffers KiefLab 4 – Simulation (tie to Lab 7 & 8) Henry/Reutter4 ( 7 ) yLab 5 – Look‐up Tables KiefLab 6 – ALU Matar/LuuLab 7 – Test Bench 1 Henry/ReutterLab 8 –Troubleshooting Henry/ReutterLab 8 Troubleshooting Henry/ReutterLab 9 – Counters KiefLab 10 – Finite State Machines Matar/LuuLab 11 – Sequence Detectors Henry/ReutterLab 12 Shift Registers KiefLab 12 – Shift Registers KiefLab 13 – IP Cores KiefLab 14 – Microprocessor System LomeliLab 15 – Chipscope Pro LomeliL b 6 RS & S i C i i Ki fLab 16 – RS‐232 & Series Communication Kief
Deploying CurriculumDeploying CurriculumWiki
http://vhdl_fpgas.ece.unm.edu
Teaching FacultyTeaching Faculty
Current ScheduleAdvanced FPGA Workshops (two days)
hPhoenix August 11‐12Albuquerque August 15‐16Huntsville August 25‐26g 5
Currently developing next set of dates for introductory coursesIf you have 6 instructors that would come to your facility it might be possible for us to come to your location!it might be possible for us to come to your location!
