-
7/28/2019 fyy1.bak
1/90
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROP
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PII NOT TO REPRODUCE OR
COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
Apple Computer
12345678
12345678
A
B
C
D
DESCRIPTION OF CHANGE
53
MS
50
AUDIO - I/O CONNS,EMC
SYSTEM BLOCK DIAGRAM
GPU - MISC
GPU - M56 CORE PWR
GPU - M56 PCI-E
VR - "S3" 3.3V AND 5V
GPU - VCORE SUPPLY
3841
JD
JD
USB - FLASH CONN
ATA (SATA AND IDE) CONNS
DDR2 - SO-DIMM CONN B (REVERSED)
SB - RTC,LAN,AUDIO,ATA,CPU,LPC
POWER BLOCK DIAGRAM
FIREWIRE - FW323-06
SB - POWERS AND GROUNDSSB - SMB,GPIO,PM,CLKS
NB - CPU INTERFACE
CIRCUITTABLE OF CONTENTS
67
68JD
VR - "S3" 1.8V
SMC - GPU/NB THERMAL SENSOR
28
JD
PAGE
SMC - SMB BUSSES, MISC
SMC - FANS
PCI-E - AIRPORT MINI-PCIE CONN
SMC - FANS
SMC - TPM
80
90
94
4947
TABLE ITEMS & REVISION HISTORY
CLOCKS - GENERATOR
GPU - EXTERNAL DISPLAY CONNS
GPU - TPS
GPU - M56 VIDEO INTERFACES
GPU - GDDR SDRAM B
GPU - GDDR SDRAM A
GPU - M56 FRAME BUFFER
CLOCKS - TERMINATIONS
NB - CONFIG STRAPS
CPU - BUS INTERFACE
POWER CONNECTOR / POWER ALIAS
58
44
49
48
47
51
46
45
62
63
64
65
59
61
58
60
56
55
78
77
76
72
71
70
68
69
66
SB - PCIE,SPI,USB,DMI,PCI
DDR2 - TERMINATION
LAN - YUKONS PCIE INTERFACE
CIRCUIT
JH
JH
JH
JH
MS
NB - DECAPS
NB - POWER 2
12
3
FIREWIRE - DECAPS
SB - DECAPS
NB - DDR2 INTERFACE
SMC - H8S2116
46
44
43
MS
M42
7
JH
JH
JH
JH
JH
95
88
JH
JH
JH
JH
JH
JH
JH
JH
JHM1
M1 87
JH
JH
M42
M1
(M42)
JD
JD
45JD
JD JD
JD
JD
JD
39
40
41
42
JD
JD
JD
42
JD JD
JD
JD
34
JD
29 PS
RT
PS30
33
JD
JD
RT
JD
JD
30
33
31
32
35
34
29
37
28
M1
M1
M1
M1
M1
M1
(M42)
(M42)
M1
JD
25
24
27
26
PS
JD
JD
JD
JD
JD
JD
JD
JD
JD23 JD
JD
PS20
19
22 JD
PS JH
JH
JH
JD
JD
23
21
25
24
22
26
27
20
1818
15
16
14
13
PS
PS
PS17
PS
PS
JH
JH
JH
JH
JH
PS
11
8
12
10
9
MS
MS
MS
JD
JD
JD
JD
JH
13
14
17
9
16
10
NB - GROUNDS
(M42)
RT
JD
5
MS
RT
JD
JD
JD1
2
DRI
JD
JD 2
5
3
4
1
FUNC TEST
M1
M1
M1
91
92M1 93
96
89
M1 86
M1 85
M1
84JH
RP
RP
RP
RP
RP
81
79
83
78
SO
RP
RP
RP
74
73
75
76
77
65
SO
SO
72
66
59
RX
61
54
PAGE
JH
JH
JH
JH
JH
JH
JH
JH JH
RT
RT
RT
RT
RT
RT
RT
RT
RT
RT
RT
PT
PT
JD
RT
RT
RT
RT
PT
PT
MS
MS
JD
MS
MS
JD
JD
GPU - TMDS,INVERTER,EXT VGA
MS
MS
MS
MS
MS
JH
JD
JD
DRI
JD
JD
SMC - LPC+ CONN
15
19PS
NB - VIDEO INTERFACE
JH
11
21 VR - "S0" 1.05V
PCI-E - UNUSED PORTS
JH
87
RT
JD
4
6
CPU - ITP CONN
NB - MISC INTERFACES
JH
73
75
74
JH
PDF
DDR2 - VTT SUPPLY
DDR2 - SO-DIMM CONN A
SB - MISC
VR - CPU CORE
52
SMC - SPI BOOTROM
43
JD
SO
RT6
AUDIO - INTERNAL SPEAKER AMP
53
CPU - PWR & GND
CPU - THERMAL SENSOR
CPU - DECAPS
FIREWIRE - CONNS
38
36
JD
JD
31
VR - "S0" 1.5V
57
VR - "S0" 1.8V
VR - CPU I-V SENSE CKT
AUDIO - DETECT TRANSLATORS
AUDIO - CODEC,VREG,MIC BIAS
PDF
VR - "S0" 1.2V & 2.5V (GRAFIX)
63
60
97
JD
54
RT
67
SB - SMB BUS CONNECTIONS
NB - POWER 1
JD
GPU - M56 GPIO,DVO,MISC
GPU - M56 CLOCKS
GPU - INTERNAL DISPLAY CONNS
M39 - DVT
LAN - YUKONS PWR, MISC
LAN - CONN
USB - CONNS
12/07/0509
SCHEM,M39
06 400374 ENGINEERING RELEASED
051-6950
-
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2/90
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
U3301
CK410
PAGE 33
CLOCKS TERMS
PAGE 34
J6000
LPC+ CONN
PAGE 60
TPMU6700
J2901 ALS+ATS TSENS
J6500,J6501,J6600 FAN CONNS
J6602 ODD TSENS
FANMLB
U1000 CPU TSENS
U6100 GPU+NB TSENS
J6601 HD TSENS
PAGE 11
J1101
CONNITP
PAGE 23
GPIOS
PAGE 24
U6300/01
PAGE 63
SPIBOOTROM
RMT
U5800
J2800J2900
DIMMS CK410M
U3301
AIRPORT
J5300
J5300 (AIRPORT CONN)
PAGE
23
SMB
PAGE
22
USB
B
CO
J4700
PAGEPAGE 48
CTLR
FLASH
U4800
PAGE 49
6
CF
JE500
MEDIA CARD CONNECTOR
SD
5
1
IR
CAMERA
732
PAGE 47
INTERFACEBNDI
3,7
0,2,4
JE350
J5300
40 PAGE 47
USB
CONNECTORS
JE310/JE320/JE330PAGE 67
SMC
PAGE 58
JE000, JE001
4-BIT (3.3V/33MHZ)LPC
PAGE
21
PAGE 44
FW323-06
PAGE 21
SPI
PAGE 22PAGE 22
DMI
S/PDIF
INTERFACE
BNDI
MIC IN
JE350
PAGE 73
J7300
CONNECTOR
LINE IN
PORT B
PORT A
PORT C
PAGE 68
STA9221AUDIO CODEC
PORT F
PAGE 73
J7301
AMP
PAGE 72
J7303
U6800
SPEAKER
PAGE 153
CONNECTOR
COMBO OUT
OPTICAL OUT
LINE OUT
SPEAKERCONNECTOR
AZALIA
21
PCI
PAGE 22
PAGE 46
CONNECTORSFIREWIRE A
0
FIREWIRE A
33MHZ
32-BIT
2 Diff pairs
PORT
PORT
PA
GE21
PAGE 28-29
DIMM
J2800
J2900
TERM
PARALLEL
PAGES 30
PAGE 41
U4101
PAGE 43
JD600
4 Diff pairs
CONNECTORETHERNET
GIG ETHERNET
YUKON
X1 - 1.5GHZ
X1 - 1.5GHZ
1.2V/1.5GHZ
AIRPORT
PAGE 53
MINI-PCIE
#1
PA
GE22
PCI-E
#2-
5
#0
PORT
UATACONNECTOR
PAGE 38
OPTICAL
3.3V/133MHZ
JC901
UATA UATA/133
SATA
PA
GE2
1
SA
TA0
HARD DRIVE
PAGE 38
SATA2
SBCORE (1.05V)
CORE (1.05V)
93 93PAGE PAGE
13
PAGEU8400
GPU
J9700 J9402
PAGE 94
LVDS
(INTERNAL)(TMDS - VGA)
MINI-DVI
PAGE 97
GDDR3
64-BIT
64-BIT
GDDR3
1.8V/700MHZ(?)
1.8V/700MHZ(?)
U9000, U9050
U8900, U8950
PAGES
87
PAGES 87
PAGE
84
NB
CPU
CORE (~1.2V)
PAGE 8
PAGE 7
(1.83/2.17GHZ)
DDR2 - DUAL CHAN
1.8V/667MHZ
64-BIT
PAGE 16-17
PAGE 90
JC900
PAGE 89MAIN
MEMORY
PCIE X16
SATACONNECTOR
PCIE
CONTROL = 2.5V
BUFFER B
FRAME
BUFFER A
FRAME
MISC
CORE
1.2V/800MHZ
2.5GHZ
J0700
FSB
64-BIT
667MHZ
PAGE 12
U1200
PAGE
15
PAGE 14
4-BIT
DMI
PAGE 14
DMI
U2100
System Block Di
051-694
2
-
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3/90
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
12V_S5
12V, 12A
12V_S0 5V_S5 5V_S0
5V, 4A
3_3V_S5
3.3V, 4A
3_3V_S0
12V, 180W, 15A
S5
AC/DC POWER SUPPLY
DC/DC BOARD
PP1V05_S01.05V @ 8.9A
PAGE 81
PPVCORE_CPU_S01.3V @ 36A
PAGE 75
PP1V8_S01.8V @ 8A
PAGE 78
1.2V @ 15A
PAGE 85
PP1V0R1V2_S0_GPU
PAGE 79
1.8V @ 10APP1V8_S3
PP1V5_S01.5V @ 8A
PAGE 80
CPU_CORE
NB_CORE
DRAM_COREDRAM_IO
CPU_AVDDNB_PCIE
NB_DRAM
CPU_FSB
SB_CORENB_FSB
SB_IO
GPU_CORE
GPU_DRAMGDDR_IO
PANEL INVERTERFIREWIRE
FANS
HARD DRIVELCDSPEAKER AMP
PAGE 83FET
PP5V_S3
PP4V5_AUDIO_ANALOG
PAGE 68
4.5V @ ?A
OPTICAL
AUDIO
PAGE 83
PP3V3_S3FET
PAGE 77
PP1V2_S0
PAGE 77
PP1V2_S31.2V @ 2.5A
FET
ENET
ENET_CORE
PP2V5_S0
PAGE 77
2.5V @ 0.9A
NB_GPIO
GPU_GPIO
GPU_PCIE
HARD DRIVE
USB
PP0V9_S00.9V @ 1A
PAGE 31
Power Block Dia
051-
3
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TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
M38
(335S0382)
(335S0384)
M39
(335S0384)
M39 - CTO
M38 / M39
COMMON
124-0338 124-0333 C7501,C8014
CAP,AL,EL,680UF,16V,RAD,10X12.5MM
338S0309 338S0266 IC,ATI,M56LP,GRAFIX CTLR,880PBGA,LFU8400
C7517,C7518,C7910128S0080 128S0078 SANYO 16SVP330M 330UF 16V SMD
LF
126S0076126S0096 SANYO W16CE680KX 680UF 16V LFC7801
197S0020 Y4101 XTAL,25MHZ,50PPM,16PF,3.2X2.5 SMD,LF197S0177
SANYO W6CE330FS 330UF 6.3V LFC699,C940,C1900,C1901,C1968
126S0086 126S0078
4
051-694
Table Items
IC,SB,652BGA CRITICAL343S0385 U21001
BAT,COIN,3V,220MAH,CR2032 CRITICALBT2600742-0048 1
IC,CY28445-5,CLK GEN,68PIN QFN359S0101 U33011 CRITICAL
511S0025 J0700 CRITICAL1 IC,CPU-SKT,479BGA
LBL,SERIAL NUMBER825-6402 CRITICALX141
U58001 CRITICAL338S0274 IC,SMC,HS8/2116,BLANK
IC,ATI,M56P,GRAFIX C TLR,880BGA,LF ATI_B24CRITICAL1338S0266
U8400
IC,TPM,TSSOP,28P U6700341S1789 LEMENU1 CRITICAL
IC,CPU VREG,IMVP,TWO PHASE353S1235 U7500 CRITICAL1
C7517,C7518,C7910CAP,EL,AL,330UF,20%,16V,10X12.7MM,SMD,LF3128S0078
CRITICAL
IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO CRITICALU4101338S0270
1
CPU CRIT ICAL1337S3242 CPU_M00M00-SPEED CPU (QINZ)
IC,945GM,NORTHBRIDGE CRITICAL338S0269 U12001
CRITICAL4 ATI_FB_128M_SAMSUNGIC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA
U8900,U8950,U9000,U9050333S0354
4333S0350
ATI_FB_256M_SAMSUNGIC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA
U8900,U8950,U9000,U9050 CRITICAL
IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA4
U8900,U8950,U9000,U9050333S0351 ATI_FB_256M_HYNIXCRITICAL
U8900,U8950,U9000,U90504 CRITICAL333S0358
ATI_FB_128M_HYNIXIC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA
IC,ATI,M56P,GRAFIX CTLR,880BGA,LF338S0305 CRITICAL1 U8400
ATI_A24
IC,FW32306,1394A LINK,TQFP1338S0279 U4400 CRITICAL
PCB,SCHEM,MLB,M39 20_INCH_LCD051-6950 1 SCH1
341T0004 EFI ROM,M39 20_INCH_LCD1 U6301 CRITICAL
1 SCH1051-6949 17_INCH_LCDPCB,SCHEM,MLB,M38
17_INCH_LCD1 MLB1PCB,FAB,MLB,M38820-1919
PCB,FAB,MLB,M39820-1888 20_INCH_LCD1 MLB1
M38/M39 LOW-SPEED CPU (QINY)1 CRITICALCPU337S3241 CPU_M38
1 17_INCH_LCDEFI ROM,M38341T0003 CRITICALU6301
17_INCH_LCD1 5.11K,1%,1/16W,402,MF-LF114S0287 R8522
M39 HI-SPEED CPU (QHJJ)1 CRITICALCPU CPU_M39337S3243
1 R8522114S0276 4.02K,1%,1/16W,402,MF-LF 20_INCH_LCD
IC,ENET LAN ROM341S1797 1 U4102 CRITICAL
-
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-
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125
125
125
125
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
SILKSCREEN:RUN
PU ON PAGE 76 IS USED
"S3" RAILSON IN RUN AND SLEEP
ONLY ON IN RUN
SILKSCREEN:2SILKSCREEN:1
CHASSIS GND
GND RAILS
"S5" RAILS
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
"S0" RAILS
0
NOSTUFFSM
NOSTUFFSM
74LC125
CRITICAL
TSSOP
CERM10V20%
402
0.1UF
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
OMITSM
OMITSM
4P25R3P5
OMIT
4P25R3P5
OMIT
4P25R3P5
OMIT402
16VCERM
0.01UF20%
NOSTUFF
20%16V
402CERM
0.01UF
NOSTUFF
402
20%16VCERM
0.01UF
NOSTUFF
NOSTUFF
MF-LF1/16W5%10K
402
603MF-LF1/10W5%330
DEVELOPMENT
NOSTUFF
0
1/16WMF-LF402
5%
160R138
OMIT
74LC125
CRITICAL
TSSOP
74LC125
TSSOP
CRITICAL
74LC125
CRITICAL
TSSOP
4025%
68
1/16WMF-LF
402
5%
68
MF-LF
1/16W
5%402
1/16WMF-LF
68
4025%
68
MF-LF1/16W
5%402
68
1/16WMF-LF
4025%
68
MF-LF1/16W
74LVC1G04DBVG4
SOT23-5
10V402
20%0.1UFCERM
4025% 1/16W
MF-LF
68
1/16WMF-LF402
5%
68
DEVELOPMENT
603MF-LF1/10W5%330
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
3305%1/10WMF-LF603
DEVELOPMENT
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
CRITICAL
6.3V
CASE-C1
330UF20%
ELEC
CRITICAL
M-RT-TH1HM9607E-P2
6
051-695
Power Conn / A
PP5V_S5PP12V_S0
PP3V3_S5
PP5V_S0
MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.6MMVOLTAGE=1.5VMAKE_BASE=TRUE
PP1V5_S0
=PP3V3_S5_ROM
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP5V_S0_DEBUG
GPU_PWM_RST_L
=PP3V3_S3_VGASYNC
=PP3V3_S3_USB
=PP12V_S0_AUDIO_SPKRAMPMAKE_BASE=TRUE
PP12V_S0_AUDIO_SPKRAMP
MAKE_BASE=TRUE
PP5V_S0_AUDIO =PP5V_S0_AUDIO
=PP3V3_S3_BT
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
PP5V_S3
VOLTAGE=5V =PP5V_S3_BNDI
=PP5V_S3_USB
=PP3V3_S0_SB_PCI
=PP2V5_S0_NB_VCCA_3GBG
=PP3V3_S0_2V5REG
=PP3V3_S0_AIRPORT
=PP3V3_S0_AUDIO
=PP3V3_S0_CK410
=PP3V3_S0_FAN
=PP3V3_S0_HD_TSENS
=PP3V3_S0_IMVP
=PP3V3_S0_NB
=PP3V3_S0_NB_PM
=PP3V3_S0_NB_TVDAC
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_ODD_TSENS
=PP3V3_S0_PATA
=PP3V3_S0_PCI
=PP3V3_S0_SB
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_TPM
=PPSPD_S0_MEM
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.6MM
PP3V3_S0
PP3V3_S0
=PP1V5_S0_AIRPORT
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCCUSBPLL
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_NB_3GPLL
=PP5V_S5_SB
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP1V05_S0_NB_VTT
=PP5V_S0_MEMVTT
=PP3V3_S3_TPM
=PP3V3_S3_ENET
=PP1V8_S0_MEMVTT
=PP1V8_S3_MEM
=PP1V8_S3_MEM_NB
=PP1V8_S3_MEM_NB
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8VMIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUEPP1V8_S3
MAKE_BASE=TRUEVOLTAGE=1.8VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
P P1V 2_ S3 = PP 1V2 _S3 _L AN
=PP12V_S0_FAN
=PP5V_S0_SB
=PP1V05_S0_CPU
=PPVCORE_S0_NB
=PP1V5_S0_SB
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_PCIE
=PP1V5_S0_CPU
=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_NB
=PPVCORE_S0_CPU
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUEVOLTAGE=1.25VMIN_LINE_WIDTH=0.6MM
PPVCORE_CPU
=PP1V05_S0_FSB_NB
=PP0V9_S0_MEMVTT_LDO
VOLTAGE=0.9VMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.15MM
PP0V9_S0MAKE_BASE=TRUE
=PP0V9_S0_MEM_TERM
ITS_RUNNINGITS_ALIVE
PP3V3_S3
ITS_PLUGGED_IN
PP5V_S5
VOLTAGE=0MIN_LINE_WIDTH=0.6MM
GND_CHASSIS_BNDI
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
GND_CHASSIS_AUDIO_INTERNAL
ZH703P1
ZH702P1
ZH701P1
MIN_NECK_WIDTHMIN_LINE_WIDTHVOLTAGE=0MAKE_BASE=TRUE
GND_CHASSIS_IO_
GND_CHASSIS_RJ45
GND_CHASSIS_VGA
GND_CHASSIS_FIREWIRE
GND_CHASSIS_IO_LEFTMAKE_BASE=TRUEVOLTAGE=0MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
GND_CHASSIS_USB
GND_CHASSIS_AUDIO_EXTERNAL
GND_AUDIO_SPKRAMP
GND_AUDIO
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=12VMAKE_BASE=TRUE
PP12V_S5
=PP12V_S5_CPU
=PP12V_S5_FW
=PP3V3_S5_SB_IO
=PP3V3_S5_SB
=PP3V3_S5_SB_USB
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_3V3_1V5_VCCSU
DEBUG_RST_L
AIRPORT_RST_L
TPM_LRESET_L
ENET_RST_L
PEG_RESET_L
NB_RST_IN_L
SMC_LRESET_L
PLT_RST_L
PP3V3_S5
U600_11
U600_8
U600_3
=PP1V5_S0_NB_VCCAUX
=PPVCORE_S0_SB
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUEVOLTAGE=5VMIN_LINE_WIDTH=0.6MM
PP5V_S0
=PP5V_S0_PATA
MIN_NECK_WIDTH=0.15MM
VOLTAGE=1.05VMIN_LINE_WIDTH=0.3MM
MAKE_BASE=TRUEPP1V05_S0
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.6MMVOLTAGE=12V
PP12V_S0
U600_6
PP3V3_S5
PM_SLP_S3_L
SYS_POWERFAIL_L
PP3V3_S0
PANEL_IDLCD_PWM
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.3VMIN_LINE_WIDTH=0.6MM
PP2V5_S0
=PP3V3_S5_FW
=PP3V3_S5_SMC
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUEPP5V_S5
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
=PP3V3_S5_DEBUG
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MMVOLTAGE=3.3V
PP3V3_S5
=PP3V3_S3_1V2REG
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.3VMAKE_BASE=TRUE
PP3V3_S3
SYS_PWRUP_L
PP12V_S5
MIN_LINE_WIDTH=0.6MMVOLTAGE=0
MIN_NECK_WIDTH=0.2MM
R6021
2
XW601
1 2
XW602
1 2U600
2
7 1
14
3
C6001
2
LED601
1
2
XW604
1 2
XW605
1 2
ZH601
1
ZH602
1
ZH603
1
C6011
2
C6021
2
C6031
2
R6011
2
R6031 2
ZH606
1
U600
5
7 4
146
U600
9
7 10
14
8
U600
12
7 13
14
11
R6121 2
R6111 2
R6141 2
R6151 2
R6161 2
R6171 2
U6012
3
5
4
C6101
2
R6181 2
R6191 2
R6001
2
LED602
1
2
R6051
2
LED600
1
2
C6991
2J600
1
10
11 12
13 14
2
3 4
5 6
7 8
9
83
83
83
83
81
81
81
81
80
80
80
80
79
79
79
79
77
88
88
88
77
77
88
77
88
83
76
76
7683
83
76
76
76
83
76
83
81
66
61
61
59
81
81
66
66
61
81
66
81
80
65
59
59
11
80
80
65
65
88
59
80
65
80
79
59
97
74
41
41
19
19
9
19
8379
79
59
19
97
59
79
41
79
59
83
79
5988
26
88
73
66
20
26
26
43
29
16
16
8
17
25
7676
19
5959
78
26
17
88
88
26
77
26
59
26
59
78
6
76
6
75
25
83
19
72
34
65
19
19
25
25
23
25
25
25
25
29
10
10
25
25
25
1942
28
14
1479
66
7
19
25
25
16
19
19
24
975
12
536
74
74
6
6
16
25
75
81
76
6
58
10
88
6
6
53
6
5
6
5
6
80
24
60
94
97
49
72
68
47
59
47
47
26
17
77
53
68
33
59
66
75
14
19
17
66
38
44
22
24
21
26
24
24
24
24
67
28
6
6
53
24
24
24
19
17
31
67
41
31
5
6
65
77 42
65
25
5
16
25
24
24
19
6
17
13
8
21
19
85
5
3179
30
65
47
73
43
97
46
47
73
72
74
5
60
53
67
42
84
14
58
22
5
6
24
6
38
34
6
5
23
76
6
9494
19
19
77
5
5
77
6
5
-
7/28/2019 fyy1.bak
7/90
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
A3*
A4*
A5*
A6*
A8*
A10*
A11*
A12*
A13*
A16*
A15*
A14*
ADSTB0*
REQ2*
REQ0*
REQ1*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A23*
A22*
A24*
A25*
A26*
A29*
A28*
A27*
A31*
A30*
ADSTB1*
A20M*
FERR*
IGNNE*
STPCLK*
LINT1
LINT0
SMI*
RSVD10
RSVD9
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD8
RSVD7
RSVD6
RSVD11
ADS*
BNR*
BPRI*
DEFER*
DRDY*
DBSY*
BR0*
IERR*
INIT*
LOCK*
RESET*
RS0*
RS1*
RS2*
TRDY*
HIT*
HITM*
BPM0*
BPM2*
BPM1*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
PROCHOT*
THERMDA
THERMDC
THERMTRIP*
RSVD12
RSVD13
RSVD16
RSVD19
RSVD18RSVD17
RSVD20
BCLK0
BCLK1
RSVD15
RSVD14
A7*
A9*
ADDR
GROUP0
XDP/ITP
SIGNAL
S
CONTROL
ADDR
GROUP1
RESERVED
HCLK
THERM
(1 OF 4)
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
GTLREF
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
TEST1
NC
(2 OF 4)
MISC
DATA
GRP0
DATA
GRP2
DATA
GRP1
DATA
GRP3
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
LAYOUT NOTE: 0.5" MAX LENGTH
PIN ACTUALLY DRIVEN BY ITPDUMMY PINNOTE:
PLACE GND VIA W/IN 1000 MILS
SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND
STUB)
WITHOUT T-ING (NO
ICH6-M AND GMCH
PM_THRMTRIP#
SHOULD CONNECT TO
PLACE TESTPOINT ON
0.1" AWAY
CPU SCH AND PCB
SYMBOL NEED TO CHECK
FSB_IERR# WITH A GND
ON ITP SIGNALS?
NO SPACE FOR ITP
CONNECTOR, NEED TERM
CPU_PROCHOT_L TO SMC
AND CPU VR TO INFORM
CPU IS HOT
TRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
LAYOUT NOTE:
1/16W1%
402MF-LF
54.9
NOSTUFF
MF-LF402
5%1/16W
68
1K
MF-LF
402
1%1/16W
2.0K
MF-LF402
1%
1/16W1/16W1%
402MF-LF
54.9
1/16W
402MF-LF
54.9
1%
1/16W1%
402MF-LF
54.9
54.9
4021%
27.4
54.9
4021%
402
27.4
NOSTUFF
402
0
NOSTUFF
1/16W5%
402MF-LF
1K51
1/16W5%
402MF-LF
OMIT
YONAH-SKT
CPUBGA
OMIT
YONAH-SKTCPUBGA
402
1/16W1%
MF-LF
54.9
CPU 1 OF 2-FSB
SYNC_MASTER=MASTER
7
051-6949
FSB_DINV_L
XDP_BPM_L
CPU_PWRGDXDP_TDI
XDP_TCK
XDP_TMS
=PP1V05_S0_CPU
=PP1V05_S0_CPU
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_A_L
FSB_A_LFSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
CPU_STPCLK_L
CPU_NMI
CPU_INTR
CPU_SMI_L
TP_CPU_APM1_L
TP_CPU_APM0_L
TP_CPU_A36_L
TP_CPU_A35_L
TP_CPU_A34_L
TP_CPU_A33_L
TP_CPU_A32_L
TP_CPU_A39_L
TP_CPU_A38_L
TP_CPU_A37_L
TP_CPU_HFPLL
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L
FSB_RS_L
FSB_RS_L
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_THERMD_P
CPU_THERMD_N
PM_THRMTRIP_L
TP_CPU_EXTBREF
TP_CPU_SPARE0
TP_CPU_SPARE6
TP_CPU_SPARE5
FSB_CLK_CPU_P
FSB_CLK_CPU_N
TP_CPU_SPARE1
FSB_A_L
CPU_TEST1
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBN_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBP_L
FSB_DINV_L
CPU_TEST2
CPU_BSEL
CPU_BSEL
FSB_DSTBN_L
CPU_BSEL
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBP_L
FSB_D_L
FSB_DSTBN_L
FSB_DINV_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DINV_L
FSB_DSTBN_L
FSB_DSTBP_L
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_SLPCPU_L
CPU_PSI_L
FSB_DSTBP_L
FSB_IERR_L
=PP1V05_S0_CPU
CPU_GTLREF
=PP1V05_S0_CPU
TP_CPU_SPARE2
TP_CPU_SPARE3
TP_CPU_SPARE4
TP_CPU_SPARE7
CPU_PROCHOT_L
R07031
2
R07041
2
R07051
2
R07061
2
R0720
1 2
R0721
1 2
R0722
1 2
R0719 1 2
R0718 1 2
R0717 1 2
R0716 1 2
R0730
1 2
R07121
2
R07071
2
J0700
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
A6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
J4
W2
Y1
L4
M3
K5
M1
N2
J1
H1
L2
V4
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
AC2
AC1
D21
K3
H2
K2
J3
L5
B1
F3
F4
G3
AA1
C3
B25
T22
D2
F6
D3
C1
AF1D22
C23
AA4
C24
AB2
AA3
M4
N5
T2
V3
B2
A3
D5
AC5
AA6
AB3
A24
A25
C7
AB5
G2
AB6
J0700
B22
B23
C21
R26
U26
U1
V1
E22
F24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
E26
L25
L22
L23
M23
P25
P22P23
T24
R24
L26
H22
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
F23
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
G25
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24AE21
AD21
E25
AE25
AF25
AF22
AF26
E23
K24
G24
J26
M26
V23
AC20
E5
B5
D24
H23
M24
W24
AD23
G22
N25
Y25
AE24
AD26
A2
AE6
D6
D7
C26
D25
R07021
2
59
59
59
59
11
11
11
11
9
9
9
9
59
59
59
8
8
59
59
59
8
8
11
11
11
7
7
12
11
11
59
11
59
59
7
7
12
7
7
7
6
6
12
12
12
12
12
12
12
12
12
21
21
21
21
21
21
12
12
12
21
12
11
12
12
7
7
11
7
11
26
21
34
34
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
75
12
6
6
5
11
215
5
5
5
5
12
12
12
5
12
12
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
12
12
12
12
12
12
12
5
12
12
5
5
21
5
5
5
5
5
12
5
12
12
12
5
5
5
5
5
12
12
12
12
5
5
11
11
11
11
11
5
5
5
5
5
11
10
10
14
5
5
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
5
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
5
5
34
34
5
34
12
12
12
12
12
12
12
12
12
5
12
12
12
12
12
5
12
5
5
12
12
12
12
12
12
12
12
12
12
12
5
12
12
12
12
5
5
5
5
21
21
12
75
5
5
5
5
59
-
7/28/2019 fyy1.bak
8/90
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73(3 OF 4)
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0802-03
TO VCCSENSE_P/N WITH NO STUB
PROVIDE A TEST POINT (WITH NO STUB)
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE
TO CONNECT A DIFFERENCTIAL PROBE
LAYOUT NOTE:
16V20%
402
CERM
0.01UF
6.3V20%
603
X5R
10UF
100
MF-LF402
1%1/16W
100
MF-LF402
1%1/16W
OMIT
CPUBGA
YONAH-SKT
OMIT
CPUYONAH-SKT
BGA
8
051-6949
SYNC_MASTER=MASTER
CPU 2 OF 2-PWR/G
=PP1V5_S0_CPU
=PPVCORE_S0_CPU
=PP1V5_S0_CPU
CPU_VCCSENSE_N
CPU_VCCSENSE_P
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
C0800 1
2
C08011
2
R08031
2
R08021
2
J0700A7
B7
AF20
B9
B10
B12
B14
B15
B17
B18
B20
C9
A9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
A10
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
A12
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
A13
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
A15
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
A17
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
A18
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
A20
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
B26
V6
N6
R21
R6
T21
T6
V21
W21
G21
J6
K6
M6
J21
K21
M21
N21
AF7
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AE7
J0700A4
B8
V25
W1
W4
W23
W26
Y3Y6
Y21
Y24
AA2
B11
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
B13
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
B16
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
B19
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
B21
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
B24
AF19
AF21
AF24
C5
C8
C11
A8
C14
C16
C19
C2
C22C25
D1
D4
D8
D11
A11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
A14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
A16
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
A19
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
A23
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
A26
N26
P3
P6
P21
P24
R2
R5
R22
R25
T1
B6 T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
5911
76
76
76
9
9
9
9
7
8
8
8
8
8
6
6
6
6
75
75
6
6
5
75
75
75
75
75
75
75
-
7/28/2019 fyy1.bak
9/90
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
PLACE INSIDE SOCKET CAVITY
ON L8 (NORTH SIDE SECONDARY)
VCCP CORE DECOUPLING
PRIMARY)
SOUTH SIDE SECONDARY
CAVITY ON L1 (SOUTH SIDE
PLACE 6 INSIDE SOCKET
PRIMARY)
SECONDARY)
SECONDARY)
CAVITY ON L1 (NORTH SIDE
PLACE 6 INSIDE SOCKET
PLACE 8 INSIDE SOCKET
CAVITY ON L8 (SOUTH SIDE
PLACE 8 INSIDE SOCKET
VCC CORE DECOUPLING
CAVITY ON L8 (NORTH SIDE
CPU HEATSINK MOUNTING HOLES
6.3V20%22UF
X5R805
20%6.3V
22UF
X5R805
6.3V20%22UF
X5R805
6.3V20%22UF
X5R805
NOSTUFF
6.3V20%22UF
805X5R
805
NOSTUFF
20%22UF6.3VX5R
20%6.3V
22UF
X5R805
6.3V20%22UF
X5R805
20%6.3V
22UF
X5R805
20%6.3V
22UF
X5R805
20%6.3V
22UF
X5R805
6.3V20%22UF
X5R805
20%22UF
X5R6.3V
805
805
20%6.3V
22UF
X5R
805
NOSTUFF
20%22UF
X5R6.3V
805
NOSTUFF
20%6.3VX5R
22UF
805
NOSTUFF
20%22UF6.3VX5R
20%6.3V
22UF
X5R805
805
20%6.3V
22UF
X5R
6.3V20%22UF
X5R805
805
NOSTUFF
20%22UF
X5R6.3V
805
20%22UF
X5R6.3V
20%22UF
X5R805
6.3V
20%6.3VX5R805
22UF
805
NOSTUFF
20%6.3V
22UF
X5R
20%0.1UF
402
10VCERM
20%6.3V
22UF
X5R805
20%6.3V
22UF
X5R805
6.3V20%22UF
X5R805
6.3V20%22UF
X5R805
805
20%22UF
X5R6.3V
CERM10V
402
0.1UF20% 20%
402
10VCERM
0.1UF
CERM10V
402
0.1UF20% 20%
0.1UF
402
10VCERM CERM
10V
402
0.1UF20%
20%6.3V
22UF
X5R805
805
20%
X5R6.3V
22UF
NOSTUFF
330UF20%6.3VELECCASE-C1
CRITICAL
2.5VTANTD2T
470UF20%
CRITICAL CRITICAL
D2TTANT2.5V20%470UF
D2TTANT2.5V
470UF20%
CRITICAL
D2TTANT2.5V
470UF20%
CRITICAL
D2TTANT2.5V
470UF20%
CRITICAL
D2TTANT2.5V
470UF20%
CRITICAL
4P75R4
OMIT
16V20%
CERM
0.01UF
402
4P75R4
OMIT
16V20%
CERM
0.01UF
402
4P75R4
OMIT
16V20%
CERM
0.01UF
402
4P75R4
OMIT
16V20%
CERM
0.01UF
402
051-69
9
CPU DECAPS & VID
=PP1V05_S0_CPU
=PP1V05_S0_CPU
C PU _H S_ ZH 60 8 C PU _H S_ ZH 60 9CPU_HS_ZH607
CPU_HS_ZH610
=PPVCORE_S0_CPU
C9071
2
C9091
2
C9201
2
C9391
2
C9001
2
C9011
2
C9021
2
C9041
2
C9051
2
C9061
2
C9081
2
C9101
2
C9111
2
C9121
2
C9131
2
C9141
2
C9151
2
C9161
2
C9171
2
C9181
2
C9191
2
C9211
2
C9221
2
C9231
2
C9241
2
C9251
2
C9261
2
C9281
2
C9291
2
C9301
2
C9311
2
C9321
2
C9341
2
C9351
2
C9361
2
C9371
2
C9381
2
C9031
2
C9401
2
C9411
23
C9421
23
C9431
23
C9441
23
C9451
23
C9461
23
ZH607
1
C950 1
2
ZH608
1
C951 1
2
ZH609
1
C952 1
2
ZH610
1
C953 1
2
59
59
11
11
9
9
8
8
7
7
76
6
6
8
5
5
66
6
-
7/28/2019 fyy1.bak
10/90
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2* IO
IO
IO
IN
OUT
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
TEMPORARILY REMOVED BOMOPTION=CPU_TSENS_EXT
CPU THERMAL SENSOR
NOTE: SYMBOL SHOULD BE SHOWN ADT7461A
THEN THIS SHOULD BE S5
IF CPU T DIODE TO BE READ IN OFF STATE,
NOTE:
ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING.
ADD GND GUARD TRACES FOR CPU_THERMD_P/N
LAYOUT NOTE:
LAYOUT NOTE:
PLACE R1002 AND R1018 SUCH THAT THEY SHARE ONE PAD
PLACE R1017 AND R1019 SUCH THAT THEY SHARE ONE PAD
ADT7461
MSOP
CRITICALCPU_TSENS_INT
1/16W
402MF-LF
1%
499
NOSTUFF
0.001UF
50V20%
402CERM
16V10%
402X5R
0.1UF
CPU_TSENS_INT
1/16W
402MF-LF
1%
499
10K
MF-LF1/16W
402
5%1/16W5%
402MF-LF
10K
SM-2MT-BLK-LF
CRITICALCPU_TSENS_EXT
402
1/16W5%
MF-LF
0
CPU_TSENS_EXT
402
0
MF-LF
5%1/16W
NOSTUFF
0
MF-LF402
5%1/16W
10
051-6949
CPU TEMP SENSOR
PP3V3_S0
THRM_THM
=SMB_THRM_CLK
THRM_ALERT_L PM_THRM_L
THERM_DX_P
THERM_DX_N
CPU_THERMD_P
CPU_THERMD_N
THERM_DX_P
THERM_DX_N
CPU_THERMD_EXT_P
CPU_THERMD_EXT_N
=SMB_THRM_DATA
U1000
6
2
3
5
8
7
4
1
C10011
2
R1005
1 2R1002
1 2
C10001
2R1017
1 2
R10011
2
R10001
2
J1000
3
4
1
2
R10181 2
R10191 2
887661594126
58
6
59
23
10
10
7
7
10
10
59
-
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11/90
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IO
IO
IO
IO
IO
IO
OUT
IN
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
ITP TCK SIGNAL LAYOUT NOTE:
CONNECTORS FBO PIN.
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO
ITP700FLEX
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO
CPUS
518S0320
(TCK)
(FBO)
CPU ITP700FLEX DEBUG SUPPORT
(DEBUG PORT ACTIVE)
(DBR#)
(DBA#)
NC
NC
NCINDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET S
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(AND WITH RESET
BUTTON)(DEBUG PORT RESET)
(FROM CK410M HOST 133/167MHZ)
MF-LF
22.6
1%1/16W
402
ITP
ITP
402
1%
22.6
1/16WMF-LF
54.9
1/16W1%
402MF-LF
ITP
16V
402X5R
10%0.1UF
ITP
240
402MF-LF
5%1/16W
ITP
F-RT-SM52435-2872
ITP
1/16W
402
54.91%
MF-LF
680
402
5%1/16WMF-LF
CPU ITP700FLEX SYNC
051-6949
11
SYNC_MASTER=MASTER
XDP_DBRESET_L
XDP_TRST_L
ITPRESET_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_TCK
CPU_XDP_CLK_NCPU_XDP_CLK_P
XDP_TCK
XDP_TMSXDP_TDI
XDP_TDO
=PP1V05_S0_CPU
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
ITP_TDO
=PP1V05_S0_CPU
=PP3V3_S5_SB_PM
FSB_CPURST_LR11001 2
R11021 2
R11031
2
C11001
2
R11041
2
J1101
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
R11011
2
R11061
2
59
59
11
11
9
9
59
59
8
8
11
11
59
59
7
7
12
26
7
7
7
7
6
6
23
7
7
7
7
7
5
34
34
5
5
5
5
7
7
7
5
6
5
-
7/28/2019 fyy1.bak
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IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP
HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11*
HD12*
HD13*
HD14*
HD5*
HD7*
HD8*
HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11*
HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
402X5R
16V10%
0.1uF 2001%
1/16W
MF-LF402
1001%1/16W
MF-LF402
54.91%
1/16WMF-LF
402
402MF-LF
1/16W
1%
24.9
2211%
1/16WMF-LF
402
1%
1/16W
MF-LF402
1000.1uF
402X5R
16V10%
402X5R
16V10%
0.1uF
2211%1/16W
MF-LF
402
54.91%
1/16W
MF-LF
402
1%1/16WMF-LF
402
100
402
MF-LF1/16W
1%
24.9
OMIT
BGA
NB
945GM
SYNC_MASTER=(MASTER) S
NB CPU Interfac
12
051-6949
FSB_D_L
FSB_DSTBN_L
FSB_DSTBN_L
FSB_DSTBP_L
FSB_DSTBP_L
FSB_DSTBP_L
FSB_DINV_L
FSB_DSTBN_L
FSB_DINV_L
FSB_DINV_L
NB_FSB_VREF
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_TRDY_L
FSB_SLPCPU_L
FSB_RS_L
FSB_RS_L
FSB_HITM_L
FSB_LOCK_L
FSB_HIT_L
FSB_DSTBP_L
FSB_DSTBN_L
FSB_DINV_L
FSB_DRDY_L
FSB_DPWR_L
FSB_DEFER_L
FSB_DBSY_L
FSB_CPURST_L
FSB_BREQ0_L
FSB_BPRI_L
FSB_BNR_L
FSB_CLK_NB_N
FSB_CLK_NB_P
NB_FSB_YSWING
NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_XSWING
NB_FSB_XSCOMP
FSB_A_L
FSB_ADS_L
FSB_ADSTB_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_D_L
FSB_REQ_L
FSB_RS_L
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
NB_FSB_XRCOMP
C1211 1
2
R12111
2
R12101
2
R12201
2
R12211
2
R12251
2
R12261
2
C12261
2
C12361
2
R12351
2
R12301
2
R12361
2
R12311
2
U1200
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
H9
C14
D14
C9
E11
G11
F11
G12
F9
E8
B9
C13
J13
C6
F6
C7
AG2
AG1
B7
F1
J1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
H1
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
J6
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
H3
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
K2
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
G1
AB5
AD10
AD4
AC8
G2
K9
K1
A7
C3
J7
W8
U3
AB10
J9
H8
K4
T7
Y5
AC4
K3
T6
AA5
AC5
K13
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
E1
E2
E4
Y1
U1
W1
19
19
19
11
12
12
12
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
34
34
7
7
7
7
7
7
7
7
7
7
7
6
6
6
7
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
7
7
7
7
5
5
5
5
5
5
7
5
7
5
5
5
7
5
5
5
7
7
5
7
7
7
7
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
5
5
5
5
5
7
5
7
5
5
5
-
7/28/2019 fyy1.bak
13/90
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
V
GA
PCI-EXPRESS
GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
SDVO_FLDSTALL#
SDVO Alternate Function
SDVO_TVCLKIN#
SDVO_INT#
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVOB_GREEN
SDVOB_RED
SDVOC_CLKN
SDVOC_BLUE#
SDVOC_GREEN#
SDVOC_RED#
SDVOB_CLKN
SDVOB_BLUE#
SDVOB_GREEN#
SDVOB_RED#
SDVOB_CLKP
SDVOB_BLUE
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP
Otherwise, tie VCCD_LVDS to GND also.
LVDS Disable
VCCD_LVDS must remain powered with proper decoupling.
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
filtering components. Unused DAC outputs should
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
Component: DACA, DACB & DACC
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
connect to GND through 75-ohm resistors.
S-Video: DACB & DACC only
Unused DAC outputs must remain powered, but can omit
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
TV-Out Signal Usage:
Composite: DACA only
TV-Out Disable
CRT Disable
Can leave all signals NC if LVDS is not implemented
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
OMIT
BGA
945GM
NB
402
MF-LF
1/16W1%
24.9
051-6949
13
SYNC_MASTER=(MASTER) S
NB PEG / Video Inter
=PP1V5_S0_NB_PCIE
LVDS_BKLTCTL
LVDS_CLKCTLA
LVDS_BKLTEN
LVDS_CLKCTLB
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_N
PEG_D2R_NPEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_COMP
LVDS_DDC_DATA
LVDS_DDC_CLK
LVDS_IBG
TP_LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDS_VDDEN
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_A_DATA_N
LVDS_A_DATA_N
LVDS_A_DATA_N
LVDS_A_DATA_P
LVDS_A_DATA_P
LVDS_A_DATA_P
LVDS_B_DATA_N
LVDS_B_DATA_N
LVDS_B_DATA_N
LVDS_B_DATA_P
LVDS_B_DATA_P
LVDS_B_DATA_P
TV_DACA_OUT
TV_DACC_OUT
TV_DACB_OUT
TV_IRTNA
TV_IREF
TV_IRTNB
TV_IRTNC
CRT_IREF
CRT_VSYNC_R
CRT_DDC_DATA
CRT_HSYNC_R
CRT_RED_L
CRT_DDC_CLK
CRT_RED
CRT_GREEN
CRT_GREEN_L
CRT_BLUE
CRT_BLUE_L
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
U1200
E23
D23
C26
C25
C22
B22
J22
A21
B21
H23
D40
D38
F34
G38
V34
W38
Y34
AA38
AB34
AC38
H34
J38
L34
M38
N34
P38
R34
T38
D34
F38
T34
V38
W34
Y38
AA34
AB38
G34
H38
J34
L38
M34
N38
P34
R38
F36
G40
V36
W40
Y36
AA40
AB36
AC40
H36
J40
L36
M40
N36
P40
R36
T40
D36
F40
T36
V40
W36
Y40
AA36
AB40
G36
H40
J36
L40
M36
N40
P36
R40
G23
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
A32
A33
B37
C37
B34
B35
A36
A37
E26
E27
F30
G30
D29
D30
F28
F29
A16
C18
A19
J20
B16
B18
B19
R13101
2
196
19
19
19
19
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
84
84
84
-
7/28/2019 fyy1.bak
14/90
SM_CS0*RSVD15
RSVD14
SM_CKE2
RSVD2
RSVD3
RSVD6
RSVD4
RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10
RSVD11
RSVD12
RSVD13
CFG1
CFG0
CFG2
CFG3
CFG4
CFG6
CFG5
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG17
CFG16
CFG15
CFG18
CFG19
CFG20
PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC0
NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0
SM_CK1
SM_CK2
SM_CK0*
SM_CK3
SM_CK1*
SM_CK2*
SM_CK3*
SM_CKE0
SM_CKE1
SM_CKE3
SM_CS1*
SM_CS2*
SM_CS3*
SMOCDCOMP0
SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0
SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR
MUXING
CFG
NC
PM
CLK
DMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
(VSS_MCHDETECT) NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IPU
(LB_DATAP3)
(LB_DATAN3)
(LA_DATAP3)
(LA_DATAN3)
(TV_DCONSEL1)
(TV_DCONSEL0)
(TESTIN#)
(H_PLLMON1)
(H_PCREQ#)
(H_EDRDY#)
(D_PLLMON1)
(D_PLLMON1#)
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPUNC
NC
(H_PROCHOT#)
(H_PLLMON1#)
NC
OMIT
945GM
NB
BGA
5%
1/16WMF-LF
402
100
10K
402
MF-LF1/16W5%
10K
402
MF-LF1/16W
5%
80.6
MF-LF402
1%1/16W
80.6
MF-LF402
1%1/16W
10K
MF-LF402
5%1/16W
14
051-6949
SYNC_MASTER=(MASTER) S
NB Misc Interfac
TP_NB_XOR_LVDS_D27
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_A35
TP_NB_TESTIN_L
TP_NB_XOR_FSB2_H7
NB_TV_DCONSEL0
MEM_VREF_NB_1
MEM_VREF_NB_0
MEM_RCOMP
NB_RST_IN_L
=PP1V8_S3_MEM_NB
DMI_N2S_P
DMI_N2S_P
DMI_N2S_P
DMI_N2S_P
DMI_N2S_N
DMI_N2S_N
DMI_N2S_N
DMI_N2S_N
DMI_S2N_P
DMI_S2N_P
DMI_S2N_P
DMI_S2N_P
DMI_S2N_N
DMI_S2N_N
DMI_S2N_N
DMI_S2N_N
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
NB_CLK100M_GCLKIN_P
NB_CLK100M_GCLKIN_N
MEM_ODT
MEM_RCOMP_L
MEM_ODT
MEM_ODT
MEM_ODT
MEM_CS_L
MEM_CS_L
MEM_CS_L
MEM_CKE
MEM_CKE
MEM_CKE
MEM_CLK_N
MEM_CLK_N
MEM_CLK_N
MEM_CLK_P
MEM_CLK_N
MEM_CLK_P
MEM_CLK_P
MEM_CLK_P
CLK_NB_OE_L
NB_SB_SYNC_L
SDVO_CTRLDATA
SDVO_CTRLCLK
NB_RST_IN_L_R
VR_PWRGOOD_DELAY
PM_THRMTRIP_L
PM_EXTTS_L
PM_BMBUSY_L
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_CFG
NB_BSEL
NB_BSEL
NB_BSEL
NB_TV_DCONSEL1
MEM_CKE
MEM_CS_L
=PP3V3_S0_NB
=PP3V3_S0_NB
PM_DPRSLPVR
U1200
K16
K18
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J18
J26
F18
E15
F15
E18
D19
D16
G16
H32
A26
A27
D41
C40
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
AG33
AF33
K28
D1
C41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
G28
F25
H26
G6
AH33
AH34
T32
J29
A41
A35
A34
D28
D27
R32
F3
F7
AG11
AF11
H7
J19
K30
H28
H27
AY35
AW35
AR1
AT1
AW7
AY7
AW40
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
BA13
BA12
AY20
AU21
AL20
AF10
AT9
AV9
AK1
AK41
R14101
2
R14111
2
R14201
2
R1430
1 2
R14411
2
R14401
2
20
20
19
75
19
19
19
19
16
22
22
22
22
34
34
30
30
30
30
30
30
30
30
30
30
26
59
30
30
14
14
75
5
5
6
6
22
22
22
5
22
22
22
5
22
22
22
5
22
22
22
5
19
19
19
19
5
5
29
29
28
28
29
29
28
29
28
28
29
29
28
29
28
29
28
28
33
22
19
19
5
5
58
23
20
20
20
20
20
20
20
34
34
34
29
28
6
6
23
1234678
-
7/28/2019 fyy1.bak
15/90
SA_DQ1
SA_DQ0
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6
SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA1
SA_MA0
SA_MA2
SA_MA3
SA_MA5
SA_MA4
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR
SYSTEM
MEMORY
A
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_DQ1
SB_DQ0
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6
SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
SB_MA1
SB_MA0
SB_MA2
SB_MA3
SB_MA5
SB_MA4
SB_MA6
SB_MA7
SB_MA9
SB_MA8
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR
SYSTEM
MEMORY
B
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE
POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
NC
NC
NC
NC
OMIT
BGA
945GM
NB
OMIT
BGA
945GM
NB
SSYNC_MASTER=(MASTER)
NB DDR2 Interfac
051-6949
15
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DQS_P
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_CAS_L
MEM_A_BS
MEM_A_BS
MEM_A_BS
MEM_A
