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www.cypress.com Document No. 001-91267 Rev. ** 1

AN91267

Getting Started with PSoC® 4 BLE

Author: Krishnaprasad M V (KRIS)

Associated Project: No

Associated Part Family: CY8C41x7-BL, CY8C42x7-BL

Software Version: PSoC Creator™ 3.1

Related Application Notes: For a complete list of the application notes, click here.

To get the latest version of this application note, please visit http://www.cypress.com/go/AN91267.

AN91267 introduces you to PSoC® 4 BLE, an ARM® Cortex®-M0 based Programmable System-on-Chip (PSoC) that integrates a Bluetooth Low Energy (BLE) radio system. This application note helps you explore the PSoC 4 BLE architecture and development tools and shows you how to create your first project using PSoC Creator™, the development tool for PSoC 4. This application note also guides you to more resources to accelerate in-depth learning about PSoC 4 BLE.

Contents

Introduction ....................................................................... 2 BLE Overview ................................................................... 2

Physical Layer (PHY) ................................................... 3 Link Layer (LL) ............................................................. 3 Host Control Interface (HCI) ......................................... 3 Logical Link Control and Adaptation Protocol (L2CAP) 3 Security Manager (SM)................................................. 4 Attribute Protocol (ATT) ................................................ 4 Generic Attribute Profile (GATT) .................................. 6 Generic Access Profile (GAP) ...................................... 7

PSoC 4 BLE Features ..................................................... 10 Bluetooth Low Energy Subsystem (BLESS) ............... 11 ARM Cortex-M0 and Memory ..................................... 11 Programmable Digital Peripherals .............................. 11 Programmable Analog ................................................ 13 System-Wide Resources ............................................ 14 Programmable GPIOs ................................................ 15

PSoC 4 BLE Development Tools .................................... 16 PSoC Creator ............................................................. 18 BLE Component ......................................................... 19 CySmart PC Application ............................................. 21 CySmart Mobile App .................................................. 22

PSoC 4 BLE Learning Resources ................................... 23 PSoC 4 BLE Datasheet .............................................. 23 Technical Reference Manuals .................................... 23 Learning PSoC Creator .............................................. 23 Application Notes ....................................................... 23 Design Guide .............................................................. 24

Technical Support ...................................................... 24 My First PSoC 4 BLE Design .......................................... 25

About the Design ........................................................ 25 Prerequisites .............................................................. 25 Part 1: Configure the Design ...................................... 26 Part 2: Firmware Design ............................................. 33 Part 3: Program the Device ........................................ 40 Part 4: Test Your Design ............................................ 41 Design Source ............................................................ 43

Summary ......................................................................... 44 Related Application Notes ............................................... 44 Appendix A: BLE Device Family Comparison ................. 45 Appendix B: Cypress Terms of Art .................................. 47 Worldwide Sales and Design Support ............................. 49



Introduction

Bluetooth Low Energy (BLE) is an ultra-low-power wireless standard defined by the Bluetooth special interest group (SIG) for short-range communication. It features a physical layer, protocol stack, and profile architecture, all designed and optimized for the lowest power consumption. BLE operates in the 2.4-GHz ISM band, with a data rate of 1 Mbps.

The Cypress PSoC 4 BLE device is a true programmable embedded system-on-chip that integrates BLE radio, programmable analog and digital peripherals, memory, and an ARM Cortex-M0 microcontroller on a single chip.

PSoC 4 BLE provides a cost-effective alternative to the combination of an MCU and an external BLE radio. In addition to reducing the overall system cost and size, the programmable analog and digital subsystems allow great flexibility, in-field tuning of the design using PSoC Creator, the schematic-based design tool for designing applications with PSoC 4 BLE, and a speedy time to market.

The BLE stack library is integrated with PSoC Creator and is free of cost. It can be easily configured using a simple graphical user interface, allowing you to jump start your BLE design in minutes.

PSoC 4 BLE offers a best-in-class current consumption of 150 nA while retaining the SRAM contents, programmable logic, and the ability to wake up from an interrupt. PSoC 4 BLE consumes only 60 nA while maintaining the wakeup capability in its nonretention power mode. These low-power modes are ideal for low-data rate-BLE designs such as heart rate monitors that are mostly battery-operated.

The capacitive touch-sensing feature in PSoC 4 BLE, known as CapSense®, offers unprecedented signal-to-noise ratio, best-in-class waterproofing, and a wide variety of sensor types such as buttons, sliders, track pads, and proximity sensors that are increasingly gaining popularity in wearable electronic devices such as activity monitors, health, and fitness equipments.

In addition to PSoC 4 BLE, Cypress also offers PRoC™ BLE, a configurable BLE device that mainly focuses on human-interface device designs such as keyboards, mouse, and remote control. See the Getting Started with PRoC BLE application note for details. See Appendix A for a comparison of BLE device families from Cypress.

Apart from PSoC 4 BLE and PRoC BLE, the Cypress PSoC portfolio contains PSoC 1, PSoC 3, PSoC 4 and PSoC 5LP that do not support BLE. These devices offer different system architectures and peripherals. For more information, refer to the Cypress Platform PSoC Solutions Roadmap.

If you are a first-time user of Cypress’s PSoC family of products, it is recommended that you read Appendix B for a list of commonly used terms.

BLE Overview

BLE, also known as Bluetooth Smart, was introduced by the Bluetooth SIG as a low-power wireless standard operating in the 2.4-GHz ISM band. Figure 1 shows the BLE stack.

Figure 1. BLE Architecture

Physical Layer (PHY)

Link Layer (LL)

Host Control Interface (HCI)

Logical Link Control and Adaption Protocol (L2CAP)

Attribute Protocol (ATT) Security Manager (SM)

Generic Attribute Profile (GATT)

Generic Access Profile (GAP)

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Controller

Host

Applications

The BLE stack can be subdivided into three groups:

Controller: A physical device that encodes the packet and transmits it as radio signals. On reception, the controller decodes the radio signals and reconstructs the packet.

Host: A software stack consisting of various protocols and profiles (Security Manager, Attribute Protocol, etc.) that manages how two or more devices communicate with one another.

Application: A use case that uses the software stack and the controller to implement a particular functionality.

The following section provides an overview of the multiple layers of the BLE stack, using standard Heart Rate and Battery Level Services as examples. For a detailed BLE architecture description, see the Bluetooth 4.1 specification or the training videos on the Bluetooth Developer website. If you are familiar with the BLE stack, you can skip this section.



Physical Layer (PHY) The physical layer transmits or receives digital data at 1 Mbps using Gaussian Frequency Shift Keying (GFSK) modulation in the 2.4-GHz ISM band. The BLE physical layer divides the ISM band into 40 RF channels with a channel spacing of 2 MHz, 37 of which are data channels and 3 are advertisement channels.

Link Layer (LL) The link layer implements key procedures to establish a reliable physical link (using an acknowledgement and flow-control-based architecture) and features that help making the BLE protocol robust and low-power. Some of the link layer functions include:

Advertising, scanning, creating and maintaining connections to establish a physical link

24-bit CRC and AES-128-bit encryption for robust and secure data exchange

Establishing fast connections and low-duty-cycle advertising for low-power operation

Adaptive Frequency Hopping (AFH) changes the communication channel used for packet transmission so that the interference from other devices is reduced.

At the link layer, there are two roles that are defined:

Master: A smartphone is an example that configures the link layer in master configuration,

Slave: A heart-rate monitor device is an example that configures the link layer in slave configuration.

PSoC/PRoC BLE devices can operate in either configuration.

The link-layer slave is the one that advertises its presence to another link-layer master. A link-layer master receives the advertisement packets and can choose to connect to the slave based on the request from an application (see Figure 2). In this example implementation, a heart rate monitor application, a heart rate monitor device which is worn by the patient acts as the client and sends the data to a smartphone, which acts as the master. A smartphone app then can display the reading on the smartphone.

PSoC/PRoC BLE devices implement the time-critical and processor-intensive parts of the link layer such as advertising, CRC, and AES encryption in hardware. Link-layer control operations such as entering the advertisement state and starting encryption, are implemented in firmware.

Figure 2 shows the BLE link-layer packet structure and sizes of the individual fields in the link-layer packet. The link-layer packet carries all upper layer data in its payload field. It has a 4-byte Access Address that is used to uniquely identify communications on a physical link, and ignore packets from a nearby BLE device operating in the same RF channel. 24-bit CRC provides data robustness.

Figure 2. BLE Link Layer Protocol

Scan, establish and manage link

Advertise capabilities

Link Master

LinkSlave

Smartphone Heart Rate Monitor

Preamble Access AddressProtocol Data Unit (PDU) CRC

(x24+x10+x9+x6+x4+x3+x1+x0)

1 byte 4 bytes 2 to 33 bytes 3 bytes

Example

FormatLink LayerPacket

Header (1B)

Payload Length (1B) Payload

0x55Random Number (0x8E89BED0)

Protocol Data Unit (PDU)CRC for PDU data

0x60 0x1A Higher Layer Protocol Data Packet

Host Control Interface (HCI) The HCI is the standard-defined interface between the host and the controller. This allows the host and the controller to exchange information such as commands, data, and events over different physical transports such as USB or UART. The HCI requires a physical transport only when the controller and the host are different devices.

In PSoC/PRoC BLE devices, the HCI is just a firmware protocol layer that passes the messages and events between the controller and the host.

Logical Link Control and Adaptation Protocol (L2CAP) L2CAP provides protocol multiplexing, segmentation, and reassembly services to upper-layer protocols. Segmentation breaks the packet received from the upper layer into smaller packets which the link layer can transmit, while reassembly combines the smaller packets received from the link layer into a meaningful packet. The L2CAP layer supports three protocol channel IDs for Attribute Protocol (ATT), Security Manager (SM) and L2CAP control. Bluetooth 4.1 allows direct data channels through L2CAP connection-oriented channels on top of these protocol channels.



The L2CAP and the layers above it are implemented in firmware in PSoC/PRoC BLE.

Figure 3. BLE L2CAP Layer

Security Manager (SM) The SM layer defines the methods used for pairing, encryption and key distribution.

Pairing is the process to enable security features. In this process, two devices are authenticated, the link encrypted, and then the encryption keys exchanged. This enables the securely exchange of data over the BLE interface without being snooped on by a silent listener on the RF channel.

Bonding is the process in which the keys and identity information exchanged during the pairing process are saved. After devices are bonded, they do not have to go through the pairing process again when reconnected.

BLE uses 128-bit AES for data encryption.

Attribute Protocol (ATT) There are two device roles in BLE that you should know to understand ATT and GATT layers:

Server: A Server is the device that contains the data or information. It receives requests from a Client device and responds with data. For example, a heart rate monitor server contains heart-rate information; a BLE HID keyboard server contains user key press information.

Client: A Client is the device that requests and/or receives data from a Server. For example, a smartphone is a Client that receives heart-rate information from the heart-rate server; a laptop is a Client that receives key-press information from a BLE keyboard.

ATT forms the basis of BLE communication. This protocol enables the client to find and access attributes on the Server (for more details about the Client and Server architecture, refer to Generic Attribute Profile (GATT)).

An attribute is the fundamental data container in BLE, which consists of the following:

Attribute Handle: The 16-bit address used to identify and access an attribute.

Attribute Type: This specifies the type of data stored in an Attribute. It is represented by a 16-bit number called Universally Unique Identifier (UUID) defined by Bluetooth SIG.

For example, the 16-bit UUID of the Heart-Rate Service is 0x180D; the UUID for the Device Name Attribute is 0x2A00. Visit the Bluetooth webpage for a list of 16-bit UUIDs assigned by SIG.

Attribute Value: This is the actual data stored in the attribute.

Attribute Permission: This specifies the attribute access, authentication, and authorization requirements. Attribute permission is set by the higher-layer specification and is not discoverable through the attribute protocol.

Figure 4 shows the structure of a Device Name attribute as an example.



Figure 4. Attribute Format and Example

Attr ibute Hierarchy Attributes are the building blocks for representing data in ATT. Attributes can be broadly classified into the following two groups to provide hierarchy and abstraction of data:

Characteristic: A collection of Attributes that exposes the data. A Characteristic consists of the following Attributes:

1. Characteristic Declaration Attribute – This defines the beginning of a Characteristic.

2. Characteristic Value Attribute – This holds the actual data.

3. Characteristic Descriptor Attributes – These are optional Attributes, which provide additional information about the Characteristic Value.

“Battery Level” is an example of a Characteristic in the battery service (BAS). Representing the battery level in percentage values is an example of a Characteristic descriptor.

Figure 5 shows the structure of a Characteristic with Battery Level as an example.

- The first part of a Characteristic is the declaration of the Characteristic (it marks the beginning of a Characteristic) indicated by Battery Level Characteristic in Figure 5,

- Next is the actual Characteristic value or the real data, which in the case of the Battery Level Characteristic is the current battery level. The battery level is expressed as a percentage of full scale, for example ‘65’, ‘90’, etc.

- Characteristic Descriptors provide additional information that is required to make sense of the Characteristic value. For example, the Characteristic Presentation Format descriptor for Battery Level indicates that the battery level is expressed as a percentage. Therefore, when ‘90’ is read, the Client knows this is 90% and not 90 mV or 90 mAh. Similarly, the Valid Range Characteristic descriptor (not shown in Figure 5) indicates that the battery level range is between 0 and 100%.

- A Client Characteristic Configuration Descriptor (CCCD) is another commonly used Characteristic Descriptor that allows a Client to configure the behavior of a Characteristic on the Server. When the Client writes a value of 0x01 to the CCCD of a Characteristic, it enables asynchronous notifications (described in the next section) to be sent from the Server. In the case of a Battery Level Characteristic, writing 0x01 to the Battery Level CCCD enables the battery service to notify its battery level periodically or on any change in battery-level value.

Figure 5. Characteristic Format and Example

Service: The type of Attribute that defines a function performed by the Server. A Service is a collection of Characteristics and can include other Services. The concept of a Service is used to establish the grouping of relative data and provide data hierarchy. See Figure 6 for an example of a Heart Rate Service (HRS).

A Service can be of two types: A Primary Service or a Secondary Service. A primary service exposes the main functionality of the device while the secondary service provides additional functionality. For example, in a heart rate monitoring device, the Heart Rate Service (HRS) is a primary service and Battery Service (BAS) is a secondary service.

A Service can also include other Services that are present on the Server. The entire included Services become part of the new Service.



Figure 6. BLE Heart Rate Service Example

The term Profile in BLE is a collection of Services and their behavior that together performs a particular end application. A Heart Rate Profile (HRP) is an example for a BLE profile that defines all the required Services for creating a heart-rate monitoring device. See the Generic Access Profile (GAP) section below for details.

Figure 7 shows the data hierarchy using Attributes, Characteristics, Services, and Profiles defined earlier in this section.

Figure 7. BLE Data Hierarchy

Attribute Operations

Attributes defined in the previous section are accessed using the following five basic methods:

Read Request: The Client sends this to the Server to read an Attribute value. For every request, the Server sends a response to the Client. A smartphone reading the Battery-level

Characteristic of a heart rate monitor device (see Figure 5) is an example of a Read Request.

Write Request: The Client sends this request to the Server to write an Attribute value. The Server responds to the Client indicating whether the value was written. A smartphone writing a value of 0x01 to the CCCD of a Battery level Characteristic to enable notifications is an example for Write Request.

Write Command: The Client sends this to the Server to write an Attribute value. The Server does not send any response for a command. For example, the BLE Immediate Alert Service (IAS) uses a Write Command to trigger an alert (turn on an LED, ring a buzzer, drive a vibration motor, and so on) on an IAS target device (for example, a BLE key fob) from an IAS locator (for example, a smartphone).

Notification: The Server sends this to the Client to notify a new value for an Attribute. The Client does not send any confirmation for a notification. For example, a heart-rate monitor device sends heart rate measurement notifications to a smartphone when its CCCD is written with a value of 0x01.

Indication: The Server sends this type of message. The Client always confirms this message. For example, a BLE Health Thermometer Service (HTS) uses indications to reliably send the measured temperature value to a health thermometer collector, such as a smartphone.

Generic Attribute Profile (GATT) The GATT defines the ways in which Attributes can be found and used. The GATT operates in one of the two roles:

GATT Client: The device that requests the data (for example, a smartphone).

GATT Server: The device that provides the data (for example, a heart-rate monitor device)

Figure 8 shows the client-server architecture in the GATT layer using a heart-rate monitoring device as an example. The heart-rate monitoring device exposes multiple Services (HRS, BAS and Device Information Service); each Service consists of one or more Characteristics with a Characteristic value and descriptor as shown in Figure 5.



Figure 8. Client-Server Architecture

After the BLE connection is established at the link-layer level, the GATT Client (which initially knows nothing about the connected BLE device) initiates a process called service discovery. As part of the service discovery, the GATT Client sends multiple requests to the GATT Server to get a list of all the available Services, Characteristics, and Attributes in the GATT Server. When service discovery is complete, the GATT Client has the required information to modify or read the information exposed by the GATT Server using Attribute operations described in the previous section.

Generic Access Profile (GAP) The GAP layer provides device-specific information such as the device address, device name, and the methods of discovery, connection, and bonding. The Profile defines how a device can be discovered, connected, the list of Services available, and how the Services can be used. Figure 10 shows an example of a Heart Rate Profile.

The GAP layer operates in one of the four roles:

Peripheral: This is an advertising role that enables the device to connect with a GAP Central. After a

connection is established with the GAP Central, the device operates as a slave. For example, a heart-rate sensor reporting the measured heart rate to a remote device operates as a GAP Peripheral.

Central: This is the GAP role that scans for advertisements and initiates connections with Peripherals. This GAP role operates as the master after establishing connections with Peripherals. For example, a smartphone retrieving the heart-rate measurement data from a Peripheral (heart-rate sensor) operates as a GAP Central.

Broadcaster: This is an advertising role that is used to broadcast data; this role cannot form BLE connections and engage in data exchange (no request/response operations). This role works similar to a radio station: it sends data continuously without bothering if anyone is listening–it is a one-way data communication. A typical example of a GAP Broadcaster is a beacon, which continuously broadcasts information but does not expect any response.

Observer: This is a listening role that scans for advertisements but does not connect to the advertising device. This is the opposite of the Broadcaster role. This works similar to a radio receiver that can continuously listen for information but cannot communicate back with the information source. A typical example of a GAP Observer is a smartphone app that continuously listens for beacons.



Figure 9. BLE System Design

Figure 9 shows a generic BLE system with Cypress’s CY8CKIT-042 BLE kit as the GAP Peripheral and a smartphone as the GAP Central device. The interaction between BLE protocol layers and their roles on the Central and the Peripheral devices are also described.



Figure 10. BLE Heart-Rate Monitor System

Figure 10 shows an example where a smartphone with a heart-rate app operates as a GAP Central and a heart-rate sensor operates as a GAP Peripheral. In Figure 10, the heart-rate monitoring device implements the Heart-Rate Sensor Profile, while the smartphone receiving the data implements the Heart-Rate Collector Profile.

In this example, the Heart-Rate Sensor Profile implements two standard services. The first is a heart-rate service that comprises three characteristics (the Heart Rate Measurement characteristic, the Body Sensor Location characteristic, and the Heart Rate Control Point characteristic). The second service is a Device Information Service. At the link layer, the heart-rate measurement device is the slave and the smartphone is the master. See the Bluetooth developer portal for a detailed description of the heart rate service and profile.



PSoC 4 BLE Features

The PSoC 4 BLE product family is based on Cypress’s PSoC 4100/4200 family of devices. It has a large set of features, which includes a CPU and memory subsystem, a BLE subsystem, a digital subsystem, an analog subsystem, and system resources, as Figure 11 shows. Figure 11 shows the features available in the CY8C4247-BL device family. Subsets of these features are available in other device families; see Table 6 on page 45.

If you are familiar with PSoC 4100/4200 family of devices, PSoC 4 BLE supports all the features supported by PSoC 4100/4200, and adds the following features:

1. BLE radio with link-layer hardware

2. External crystal oscillator and watch crystal oscillator

3. Four opamps (as compared to two in PSoC 4100/4200 family) that are active in deep-sleep mode

4. 128 KB flash and 16 KB SRAM (as compared to 32 KB flash and 4 KB SRAM in PSoC 4100/4200 family)

The following sections briefly describe each feature. For more information, see the PSoC 4 BLE family device datasheet, technical reference manual (TRM), and application notes listed in the PSoC 4 BLE Learning Resources section.

Figure 11. PSoC 4 BLE Architecture (CY8C4247-BL)



Bluetooth Low Energy Subsystem (BLESS) The BLE subsystem contains the physical layer (PHY) and the link-layer engine with an embedded AES-128 security engine.

The physical layer consists of Digital PHY and RF Transceiver that transmits and receives GFSK packets at 1 Mbps over the 2.4-GHz ISM band compliant with BLE Bluetooth Specification 4.1. The baseband controller is a composite hardware/firmware implementation that supports both master and slave modes. The key protocol elements such as HCI and link control are implemented in firmware, while time-critical functionalities such as encryption, CRC, data whitening, and access code correlation are implemented in hardware.

The BLESS is Bluetooth 4.1 compliant with support for all features of Bluetooth 4.0 specification and some additional features of Bluetooth 4.1 specification such as low-duty-cycle advertising, LE ping and L2CAP connection-oriented channels. The BLESS block also contains an external crystal oscillator (ECO) and watch crystal oscillator (WCO) that are required for generating an accurate RF frequency and accurately keeping the time between successive connection intervals on the BLE link respectively. The ECO and the WCO from the BLESS block can also be used as high-frequency and low-frequency clock sources for the PSoC 4 BLE system. See Clocking System section on page 14 for details.

The BLESS supports five functional power modes: deep-sleep, sleep, idle, transmit, and receive.

Note The power modes discussed in this section are specific to the BLESS block. For PSoC 4 BLE system power modes, see Low-Leakage Power Modes.

Deep-Sleep Mode The deep-sleep mode is the lowest-power functional mode supported by the BLESS. In this mode, the radio is off. This mode is entered for maximum power saving during an advertising or connection interval after the packet transmission and reception is complete. The ECO can be turned off in this mode for power saving; the WCO, which is the low-frequency clock, is on for maintaining the BLE link-layer timing reference logic. The CPU controls the entry to and exit from this state.

Sleep Mode In sleep mode, the radio is off. The block maintains all the configurations. The ECO and WCO are turned on, but the clock to the core BLESS logic is turned off. The CPU controls the entry to and exit from this state.

Id le Mode The idle mode is the preparation state for the transmit and receive states. In this state, the radio is turned off but the link-layer clock is enabled for the link-layer logic so that the CPU starts the protocol state machines.

Transmit Mode The transmit mode is the active functional mode; all blocks within BLESS are powered on. The link-layer clock is enabled to complete the logic within the link layer and RF-PHY. In this mode, RF-PHY gets 1-Mbps serial data from the link layer and transmits the 2.4-GHz GFSK-modulated data to the antenna port. BLE enters the transmit mode from the idle mode.

Receive Mode This mode enables the BLESS to move into the receive state to perform BLE-specific receiver operations. RF-PHY translates the 1-Mbps data received from the RF analog block and forwards it after demodulation to the link-layer controller.

A summary of BLESS power modes and operational sub-blocks is shown in Table 1.

Table 1. BLESS Power Modes

BLESS Power Mode ECO WCO

RF Tx

RF Rx

BLESS Core

Deep-Sleep Off On Off Off Off

Sleep On On Off Off Off

Idle On On Off Off On

Transmit On On On Off On

Receive On On Off On On

ARM Cortex-M0 and Memory PSoC 4 BLE has a 32-bit ARM Cortex-M0 CPU, capable of operating at the maximum frequency of 48 MHz, providing a 43-DMIPS performance. The CPU supports single-cycle 32-bit multiplication. PSoC 4 BLE has 16 KB of SRAM and 128 KB of flash memory that can service most of the BLE application use; the flash includes a read accelerator. The device also provides 512 bytes of supervisory flash area for you to store user-specific data such as BLE device address and encryption keys.

Programmable Digital Peripherals PSoC 4 BLE provides a rich set of digital peripherals including programmable serial communication blocks (SCBs), Timer Counter PWMs (TCPWMs), and programmable logic blocks called universal digital blocks (UDBs).

Programmable SCBs PSoC 4 BLE has independent run-time programmable SCBs with I2C, SPI, or UART. The SCB supports the following features:

Standard SPI master and slave functionality with Motorola®, Texas Instruments®, and National Semiconductor® protocols



Standard UART functionality with smart-card reader, Local Interconnect Network (LIN), and Infrared Data Association (IrDA) protocols

Standard I2C master and slave functionality

SPI and EZI2C mode, which allows operation without CPU intervention

Low-power (deep-sleep) mode of operation for SPI and I2C protocols (using an external clock)

For more information, refer to the PSoC 4 SCB Component datasheet.

Programmable TCPWMs PSoC 4 BLE has four programmable 16-bit TCPWM blocks. Each TCPWM can implement a 16-bit timer, counter, PWM, or quadrature decoder. TCPWMs provide complementary outputs and selectable start, reload, stop, count, and capture event signals. The PWM mode supports center-aligned, edge, and pseudo random operations.

For more information, refer to the PSoC 4 TCPWM Component datasheet.

Universal Digi tal Blocks (UDBs) UDBs are programmable logic blocks that provide functionalities similar to CPLD and FPGA blocks, as Figure 12 shows. UDBs allow you to create a variety of digital functions such as timer, counter, PWM, pseudo random sequence (PRS), CRC, shift register, SPI, UART, I2S, and custom combinational and sequential logic circuits.

Each UDB has two programmable logic devices (PLDs), each with 12 inputs and 8 product terms. PLDs can form registered or combinational sum-of-products logic. Additionally, an 8-bit single-cycle arithmetic logic unit (ALU), known as a datapath, is present in each UDB. The datapath helps with the efficient implementation of functions such as timer, counter, PWM, and CRC.

UDBs also provide a switched digital signal interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control.

Figure 12. Universal Digital Block Diagram

You do not have to master any hardware description language (HDL) to use UDBs. PSoC Creator, Cypress’s development tool for PSoC 4 BLE, can generate the required function for you from a schematic.

For more information, refer to the following application notes.

AN62510 Implementing State Machines with PSoC 3, PSoC 4, and PSoC 5LP

AN82156 PSoC 3, PSoC 4, and PSoC 5LP Designing PSoC Creator Components with UDB Datapaths

AN82250 PSoC 3, PSoC 4, and PSoC 5LP Implementing Programmable Logic Designs with Verilog

Appl icat ions The use of programmable digital peripherals in BLE applications is shown in Table 2.

Table 2. Applications of Programmable Digital Peripherals

Applications Digital Peripherals

Sensor Hub I2C (digital sensor interface), PWM (actuators), I2S (voice input)

Health and Fitness

PWM (user interface), Counter (waveform peak measurement), SPI (external memory interface)

Industrial UART (modbus), Counter (event counting)

Home Automation

PWM (garage door control), PWM (lighting control)



Programmable Analog PSoC 4 BLE provides the industry’s best-in-class analog integration. The analog system includes continuous time block mini (CTBm) blocks, a fast 12-bit SAR ADC, low-power comparators, capacitive touch-sensing (CapSense), and segment LCD direct drive.

Continuous Time Block mini (CTBm) PSoC 4 BLE contains two CTBm blocks; each CTBm block consists of two programmable opamps and a switch matrix. You can configure each opamp individually as a comparator, voltage follower, or an opamp with external feedback. The CTBm block will continue to function even in deep-sleep mode.

For more information, refer to the following Component datasheets:

PSoC 4 Opamp

PSoC 4 Voltage Comparator

SAR ADC with Hardware Sequencer PSoC 4 BLE has a 12-bit, 1-Msps SAR ADC with input channels that support programmable resolution and single-ended or differential input options. The number of GPIOs limits the number of channels.

The SAR ADC has a hardware sequencer that can perform an automatic scan on as many as eight channels without CPU intervention. The SAR ADC also supports preprocessing operations such as accumulation and averaging of the output data on these eight channels.

You can trigger a scan with a variety of methods, such as firmware, timer, pin, or UDB, giving you additional design flexibility.

For more information, refer to the PSoC 4 Sequencing Successive Approximation Component datasheet.

Low-Power Comparators PSoC 4 BLE devices have low-power comparators capable of operating in all system power modes except the stop mode. In a power-sensitive design, when the device goes into low-power modes, you can use the low-power comparator to monitor analog inputs and generate an interrupt that can wake up the system.

For more information, refer to the PSoC 4 Low-Power Comparator Component datasheet.

Capacit ive Touch Sensing (CapSense) Capacitive touch sensors use human-body capacitance to detect the presence of a finger on or near a sensor. Capacitive sensors are aesthetically superior, easy to use, and have long lifetimes.

The CapSense feature in PSoC 4 BLE offers unprecedented signal-to-noise ratio; best-in-class liquid tolerance; and a wide variety of sensor types such as buttons, sliders, track pads, and proximity sensors.

A Cypress-supplied software Component makes capacitive sensing design very easy; the Component supports an automatic hardware-tuning feature called SmartSense™ and provides a gesture-recognition library for trackpads and proximity sensors.

Two current DACs (IDACs), one 7-bit and one 8-bit, in the CapSense block are available for general-purpose use if capacitive sensing is not used. The comparator in the CapSense block is also available for general-purpose use.

For more information, see the PSoC 4 CapSense Design Guide.

Segment LCD Direct Driver Most low-power, portable, handheld devices such as glucose meters, multimeters, and blood pressure monitors use a segment LCD to display information. Segment LCDs require an external driver to interface with a microcontroller. PSoC 4 BLE includes an integrated low-power LCD driver that can directly drive segment LCD glass.

PSoC 4 BLE can drive LCDs with as many as four common and thirty-two segment electrodes. The segment LCD driver can retain a static display in deep-sleep mode with a system current consumption as low as 7 µA.

For more information, see AN87391 PSoC 4 Segment LCD Direct Drive.

Appl icat ions The use of programmable analog peripherals in different BLE applications is listed in Table 3.

Table 3. Applications of Programmable Analog Peripherals

Applications Analog Peripherals

Health and Fitness

Opamp - TIA (heart-rate measurement)

Opamp – Follower (analog- reference buffer)

ADC (sampling heart-rate signal)

CapSense (user interface on a wrist band)

Segment LCD (display on a wrist band)

Sensor Hub ADC (analog sensor interface)

Analog Mux (multiple-sensor input)

Opamps (signal amplifier)

Segment LCD (UI)



Applications Analog Peripherals

Industrial ADC – differential mode (temperature measurement)

IDAC (temperature-sensor drive)

Low-Power Comparator (wakeup on threshold detection)

Opamp – PGA (4-20 mA current-loop system)

Home Automation

Opamp – PGA (motion sensor, light sensor)

Comparator (door sensors)

ADC and Opamp filter (smoke detector)

System-Wide Resources This section explains the system-wide resources available for all peripherals in PSoC 4 BLE.

Low-Leakage Power Modes PSoC 4 BLE offers the following power modes1:

Active mode: This is the primary mode of operation. In this mode, all peripherals are available.

Sleep mode: In this mode, the CPU is in sleep mode, SRAM is in retention, and all the peripherals are available. Any interrupt wakes up the CPU and returns the system to active mode.

Deep-Sleep mode: In this mode, the high-frequency clock (IMO) and all high-speed peripherals are off. Optionally, the low-frequency clocks (32-kHz ILO and WCO) and low-speed peripherals are available. Interrupts from low-speed, asynchronous, or low-power analog peripherals can cause a wakeup. The current consumption in this mode is 1.3 µA.

Hibernate mode: This power mode provides a best-in-class current consumption of 150 nA while retaining SRAM, programmable logic, and the ability to wake up from an interrupt generated by a low-power comparator or a GPIO.

Stop mode: This power mode retains the GPIO states. Wakeup is possible from a fixed “WAKEUP” pin. The current consumption in this mode is only 60 nA.

You can use a combination of sleep, deep-sleep, and stop modes in a battery-operated BLE system to achieve best-in-class system power with longer battery life. 1 These are PSoC 4 BLE device power modes and are different from power modes

described in Bluetooth Low Energy Subsystem (BLESS) section

Table 4 shows the dependency between PSoC 4 BLE system power modes and BLESS power modes. All these dependencies are automatically handled by simple APIs;

see Main Loop and Low-Power Operation section on page 39 for an example.

In a typical BLE application such as heart-rate monitoring, the PSoC 4 BLE device will be in active mode while measuring the heart rate, in sleep mode while BLE radio is transmitting or receiving packets, in deep-sleep mode between consecutive BLE connection intervals and in hibernate or stop mode on BLE advertisement timeout.

Table 4. PSoC 4 BLE Power Modes

BLESS Modes

PSoC 4 BLE System Power Modes

Active Sleep Deep-Sleep

Hibernate Stop

Transmit

Receive

Idle

Sleep

Deep-Sleep

Powered

Power Supply and Monitor ing PSoC 4 BLE is capable of operating from a single 1.9-5.5-V supply. There are multiple internal regulators to support the power modes, including the active digital regulator, quiet regulator, deep-sleep regulator, hibernate regulator, and RF regulators.

PSoC 4 BLE has three types of voltage-monitoring capabilities: power-on reset (POR), brownout detection (BOD), and low-voltage detection (LVD).

Clocking System PSoC 4 BLE has the following clock sources:

Internal main oscillator (IMO): The IMO is the primary source of internal clocking in PSoC 4 BLE. The CPU and all high-speed peripherals can operate from the IMO or an external crystal oscillator (ECO). PSoC 4 BLE has multiple peripheral clock dividers operating from either the IMO or the ECO, which generate clocks for high-speed peripherals. The IMO can generate clocks in the range of 3 MHz to 48 MHz in 1-MHz increments with an accuracy of ±2%.

Internal low-speed oscillator (ILO): The ILO is a very-low-power 32-kHz oscillator, which primarily generates clocks for low-speed peripherals operating in deep-sleep mode except BLESS (see WCO).

External crystal oscillator (ECO): The external crystal oscillator with a built-in tunable crystal load capacitance is used to generate a highly accurate



24-MHz clock. It is primarily used to clock the BLE subsystem that generates the RF clocks. The high-accuracy ECO clock can also be used as a clock source for the PSoC 4 BLE device’s high-frequency clock (HFCLK).

Watch crystal oscillator (WCO): The 32-kHz WCO is used as one of the sources for LFCLK (along with ILO). WCO is used to accurately maintain the time interval for BLE advertising and connection events. Similar to ILO, WCO is also available in all modes except Hibernate and Stop modes.

Figure 13 shows the clocking architecture of a PSoC 4 BLE device.

Figure 13. PSoC 4 BLE Clocking System

IMO

ILO

EXTCLK

LFCLK

Prescaler SYSCLK

Divider 0(/16)

PER0_CLK

Divider 9(/16)

Fractional Divider 0(/16.5)

Fractional Divider 1(/16.5)

ECO

WCO

HFCLK

PER15_CLK

Divider/2n (n=0..3)

Device Securi ty PSoC 4 BLE provides a number of options to protect the flash memory from unauthorized access or copying. Each row of flash has a single protection bit; these bits are stored in a supervisory flash row.

Programmable GPIOs The I/O system provides an interface between the CPU and the peripherals and the outside world. PSoC 4 BLE has up to 36 programmable GPIO pins. You can configure the GPIOs for CapSense, LCD, analog, or digital signals. PSoC 4 BLE GPIOs support multiple drive modes, drive strengths, and slew rates.

PSoC 4 BLE offers an intelligent routing system that gives multiple choices for connecting an internal signal to a GPIO. This flexible routing simplifies circuit design and board layout.



PSoC 4 BLE Development Tools

Figure 14 shows a general ecosystem of hardware and software tools required for functioning of BLE designs using PSoC 4 BLE devices. The BLE development kit (red board in Figure 14) acts as a BLE peripheral that can either communicate with a CySmart iOS/Android app or CySmart PC application that acts as a BLE central device. CySmart PC application also requires a BLE USB dongle (black board in Figure 14) for its operation. The development system setup required for programming and debugging BLE designs is shown in Figure 15.

Figure 14. BLE Functional Setup



Figure 15. BLE Development Setup

As Figure 14 and Figure 15 show, the following software and hardware tools are required to get started with a PSoC 4 BLE-based design:

1. PSoC 4 BLE Development Kit

2. PSoC Creator 3.1 or later IDE with the BLE Component

3. CySmart PC application or iOS/Android app

The following sections will give you a brief introduction to all the items mentioned above.



PSoC 4 BLE Development Kit

CY8CKIT-042 BLE or BLE Pioneer Kit shown in Figure 16 is a BLE development kit from Cypress that supports both PSoC 4 BLE and PRoC BLE family of devices. This kit consists of pluggable PSoC 4 BLE (and PRoC BLE) modules that connect to a pioneer baseboard. The kit can either be powered with battery or through the USB interface.

The pioneer baseboard and RF module combination enables you to develop battery-operated low-power BLE designs that work in conjunction with standard, Arduino Uno connector-compliant shields, and additional PSoC 4 BLE device capabilities such as CapSense user interface on the pioneer baseboard.

The pioneer baseboard has an on-board programming and debugging interface, making BLE design debugging through the PSoC Creator IDE quick and easy. The BLE pioneer kit also has an additional header that supports interfacing with Pmod™ daughter cards from third-party vendors such as Digilent®. The kit also consists of a BLE USB dongle that acts as a BLE master and works with the CySmart PC application to provide a BLE master emulation platform on non-BLE Windows systems.

The kit consists of a set of BLE example projects and documentation that help you get started with developing your own BLE applications. Visit www.cypress.com/go/CY8CKIT-042-BLE to get the latest updates on the kit and download the kit design, example projects, and documentation files.

Figure 16. BLE Pioneer Kit

PSoC Creator PSoC Creator is a state-of-the-art, easy-to-use integrated design environment. It offers a unique combination of hardware configuration and software development based on standard schematic entry, as Figure 17 shows. You can develop applications in a drag-and-drop design environment using a library of pre-characterized, production-ready Components.

You can customize each Component using a configuration window. To open the configuration window, double-click the Component or right-click the Component and select “Configure.”



Figure 17. PSoC Creator Schematic Entry and Components

Each Component comes with a detailed Component datasheet. To open the datasheet, right-click the Component and select “Open Datasheet”. For details, see the PSoC Creator home page.

BLE Component The BLE Component provides a comprehensive GUI-based configuration window to quickly design applications that require BLE connectivity. The Component incorporates a Bluetooth Core Specification v4.1-compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying BLESS hardware via the stack.

The Component supports the SIG-adopted GATT-based profiles and services as well as custom BLE profiles and services, and it allows the configuration for various GAP and GATT roles. The Component generates the necessary code for a particular profile and service operation, as configured in the GUI, abstracting the underlying BLE stack and hardware configuration so that you can concentrate on the system design.

The BLE Component also provides profile APIs to design BLE solutions without requiring manual stack-level configuration. The exception to this is the L2CAP configuration specified in Bluetooth v4.1, which allows advanced users to configure the L2CAP layer of the stack.

The GUI configuration windows for the BLE Component are shown in Figure 18. For a BLE peripheral application shown in the My First PSoC 4 BLE Design section on page 25, the BLE stack consumes approximately 60 KB of flash and 10 KB of SRAM. For a detailed description of the BLE Component usage and memory consumed for different profiles and roles, see the BLE Component datasheet. Refer to application notes AN91184 and AN91162 for a step-by-step description of how to use the BLE Component to develop applications based on standard and custom BLE profiles. The My First PSoC 4 BLE Design section will walk you through a step-by-step configuration of the BLE Component for creating a simple BLE application.

In addition to the BLE component, PSoC Creator also provides a list of analog, digital, and communication Components that you can use in your design. These additional Components are not described in this application note; refer to the PSoC Creator Component catalog and datasheet of the Components for details.



Figure 18. BLE Component Configuration Windows



CySmart PC Application CySmart is a Windows application that emulates a BLE master using the BLE USB dongle provided with the BLE pioneer kit; see Figure 14. It is installed as part of CY8CKIT-042 BLE pioneer kit installation and can be launched with the right-click options in the BLE Component. It provides a platform for you to test your PSoC 4 BLE peripheral implementation over GATT or L2CAP connection-oriented channels by allowing you to discover and configure the BLE services, characteristics, and attributes on your BLE peripheral.

The common list of operations that you can perform with the CySmart PC application includes, but is not limited to:

Scan BLE peripherals to discover available devices which you can connect to.

Discover available BLE attributes including services and characteristics on the connected peripheral device.

Perform read and write operations on characteristic values and descriptors.

Receive characteristic notifications and indications from the connected peripheral device.

Establish a bond with the connected peripheral device using BLE security manager procedures.

Establish a BLE L2CAP connection-oriented session with the peripheral device and exchange data per the Bluetooth 4.1 specification.

Figure 19 and Figure 20 show the user interface of the CySmart PC application. For more information on how to setup and use the CySmart tool, see the CySmart user guide from the Help menu.

Figure 19. CySmart PC Application Master Device Tab

Advertisement and Scan Response Data

Discovered Device List

Log Window

Trusted Device List



Figure 20. CySmart PC Application Peripheral Device Attributes Tab

CySmart Mobile App In addition to the PC application, you can download the CySmart mobile app for iOS or Android from the respective app stores. This app uses iOS’s Core Bluetooth framework and Android’s built-in platform framework for BLE respectively to configure your BLE-enabled Smartphone as a BLE central device that can scan and connect to BLE peripheral devices.

The mobile app supports SIG-adopted BLE standard profiles through an intuitive GUI and abstracts the underlying BLE service and characteristic details. In addition to the BLE standard profiles, the app also demonstrates a custom profile implementation using Cypress’s simple LED and CapSense demo examples. Figure 21 shows a set of CySmart app screenshots for the heart-rate-profile user interface. For a detailed description of how to use the app with BLE pioneer kit example projects, see the BLE pioneer kit user guide.

Figure 21. CySmart Heart Rate Profile



PSoC 4 BLE Learning Resources

This section provides a list of PSoC 4 BLE learning resources that can help you to get started and to develop complete applications with PSoC 4 BLE. You can also use the Document Manager (Help > Document Manager) in PSoC Creator to view these resources.

PSoC 4 BLE Datasheet The PSoC 4 datasheet lists the features and electrical specifications of all PSoC 4 BLE device families.

PSoC 4 BLE Datasheet

Technical Reference Manuals The TRMs provide detailed descriptions of the internal architecture of the PSoC 4 BLE device.

PSoC 4 BLE Technical Reference Manuals

Frequently Asked Questions (FAQs) The PSoC 4 BLE/PRoC BLE FAQs webpage provide a list of frequently asked questions about Cypress’s BLE devices, development tools, technology, solution and reference designs.

PSoC 4 BLE/PRoC BLE FAQs

Learning PSoC Creator Visit the following page to download the latest version of PSoC Creator.

PSoC Creator home page

Launch PSoC Creator and navigate to the following items:

Quick Start Guide: Choose Help > Documentation > Quick Start Guide. This guide gives you the basics for developing PSoC Creator projects.

Simple Component example projects: Choose File > Open > Example projects. These example projects demonstrate how to configure and use PSoC Creator Components.

Starter designs: Choose File > New > Project > PSoC 4100/4200-BL Starter Designs. These starter designs demonstrate the unique features of PSoC 4 BLE.

System Reference Guide: Choose Help > System Reference > System Reference Guide. This guide lists and describes the system functions provided by PSoC Creator.

Component datasheets: Right-click a Component and select “Open Datasheet.” Visit the following page for a list of all PSoC 4 BLE Component datasheets: PSoC 4 BLE Component Datasheets.

Application Notes Application notes assist you with understanding specific features of the device and designing your PSoC application. Visit the following page for a complete list of PSoC 4 BLE application notes.

PSoC 4 BLE Application Notes

For example, here are a few application notes that can help you get started with developing PSoC 4 BLE applications.

AN54460 PSoC 3, PSoC 4, and PSoC 5LP Interrupts

AN82156 PSoC 3, PSoC 4, and PSoC 5LP Designing PSoC Creator Components with UDB Datapaths

AN68272 PSoC 3, PSoC 4, and PSoC 5LP UART Bootloader

AN86233 PSoC 4 Low-Power Modes and Power Reduction Techniques



Design Guide Visit the following page to download the PSoC 4 CapSense Design Guide, which shows how to design capacitive touch-sensing applications with the PSoC 4 family of devices.

PSoC 4 CapSense Design Guide

Technical Support If you have any questions, our technical support team is happy to assist you. You can create a support request using the following link.

Cypress Technical Support

Cypress Developer Community

If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 8 at the prompt.

You can also use the following support resources if you need quick assistance.

Self-help

Local Sales Office Locations



My First PSoC 4 BLE Design

This section gives you a step-by-step process for building a simple BLE pioneer kit-based design with the PSoC 4 BLE device using PSoC Creator.

About the Design This design implements a BLE peripheral device that acts as a “Find Me Target” implementing Immediate Alert Service (IAS) and connects to a BLE central device. Alert levels triggered by the central device are indicated by varying the state of an LED on the BLE pioneer kit. A PWM is used in the design to drive the LED based on the received alert level, as Figure 22, a PSoC Creator schematic, shows. Two status LEDs indicate the state of the PSoC 4 BLE device and a push button input pin wakes up the device from the low-power hibernate mode.

Figure 22. My First PSoC 4 BLE Design

Prerequisites Before you get started with the implementation, make sure you have a CY8CKIT-042 BLE pioneer kit and have installed the following software:

PSoC Creator 3.1 or later with PSoC Programmer 3.21.0 or later

CySmart PC application or iOS/Android app

There are four main steps to successfully create your first PSoC 4 BLE design:

1. Configure the design in PSoC Creator schematic page.

2. Write the firmware to initialize and handle BLE events.

3. Program the PSoC 4 BLE device on the BLE pioneer kit.

4. Test your design using the CySmart PC application or mobile app.



Part 1: Configure the Design This section takes you on a step-by-step guided tour of the design process. It starts with creating an empty project and guides you through schematic design entry. You can skip this section if you simply wish to try the example project provided with this application note without going through the build process.

1. Install PSoC Creator 3.1 or later on your PC.

2. Start PSoC Creator, and from the File menu, choose New > Project, as Figure 23 shows.

Figure 23. Creating a New Project

3. Choose the project template PSoC 4100/4200-BL

Design, and give the project a name such as “BLE_FindMe” as Figure 24 shows. Choose an appropriate location for your new project, and then click OK.

Figure 24. Naming the New Project

4. Go to Project > Device Selector and select the device. If you are using a development kit, read the part number from the kit or refer to the kit user guide for the part number. Figure 25 shows an example selection of CY8C4247LQI-BL483 for the CY8CKIT-042 BLE Pioneer Kit.

Figure 25. Device Selection

5. Creating a new project generates a project folder with a baseline set of files. You can view these files in the Workspace Explorer window, as Figure 26 shows. Open the project schematic file TopDesign.cysch by double-clicking it.

Figure 26. Opening TopDesign Schematic



6. In the project schematic, you can create analog, digital, and communication designs by dragging and dropping Components and wiring them. For our current design, we need five Components: BLE, PWM, Clock, Interrupt and Pin as Figure 22 shows.

7. Drag one Bluetooth Low Energy (BLE) Component from the Component Catalog onto the schematic, as Figure 27 shows.

Figure 27. Location of the BLE Component

8. Double-click the BLE Component on the schematic to configure it as a “BLE Find Me Target” with the following properties:

GAP peripheral role with Find Me Target (GATT Server) configuration

GAP Device Name set to “Find Me Target” and Appearance set to Generic Keyring. This configures the device name and type that will appear when another device attempts to discover your device.

Limited advertisement mode with an advertising timeout of 30 seconds and fast advertisement interval of 20 to 30 ms. Fast advertising allows quick discovery and connection but consumes more power due to increased RF advertisement packets.

Advertisement Packet with Immediate Alert Service enabled and Scan Response Packet with Local Name, Tx Power Level, and Appearance fields enabled, Advertise IAS, Appearance, and the Device Name fields.

GAP security set to the lowest possible configuration that does not require authentication, encryption, or authorization for data exchange (Mode 1, No Security)

Figure 28 to Figure 34 show the BLE Component screenshots for this configuration.

Note You do not need to change the default configuration of the BLE Component in the General and Profiles tabs for this design.

Figure 28. BLE Component General Configuration

Figure 29. BLE Component Profiles Configuration



Figure 30. BLE Component GAP General Settings

Figure 31. BLE Component GAP Advertisement Settings

Figure 32. BLE Component GAP Advertisement Packet

Figure 33. BLE Component GAP Scan Response Packet

Figure 34. BLE Component GAP Security Settings



9. Drag one PWM (TCPWM mode) Component from the Component Catalog onto the schematic, as Figure 35 shows.

Figure 35. Location of the PWM Component

10. Double-click the PWM Component on the schematic to configure the Component properties, as Figure 36 shows. Change the name of the Component to PWM. Click the PWM tab, and set the period value to 200 and the Compare value to 0 to initially generate a constant high drive on line_n output of the PWM that drives the Alert_LED (= Alert_LED off). Disable the interrupts in the PWM Component.

Figure 36. Configuring the PWM Component

PWM requires an input clock for its operation. Drag and drop a Clock Component onto the schematic, and configure the frequency to 2 kHz, as Figure 37 and Figure 38 show. The PWM period of 200 with this input clock results in a PWM output time period of 100 ms.

Figure 37. Location of the Clock

Figure 38. Configuring the Clock Component



11. Drag and drop a Digital Output Pin Component. Change the name to Alert_LED as Figure 39 and Figure 40 show.

Figure 39. Location of the Digital Output Pin Component

Figure 40. Renaming a Pin Component

12. Select the wire tool, as Figure 41 shows, or press “W” on your keyboard.

Figure 41. Selecting the Wire Tool

13. Wire the Components together, as Figure 42 shows.

Figure 42. Wiring the Schematic

14. Similarly, add two more Digital Output Pin Components named Advertising_LED and Hibernate_LED to your design (see Figure 39 and Figure 40) with HW Connection unchecked and Initial drive state set to High(1) as Figure 43 and Figure 44 show. These pins will be used to drive the BLE advertising- and device hibernate-state LEDs. The LEDs on CY8CKIT-042 BLE are active LOW, i.e., high pin-drive state turns off the LEDs and low pin-drive state turns them on.

Figure 43. Advertising LED Configuration

Figure 44. Hibernate LED Configuration



15. Drag and drop a Digital Input Pin Component. Change the name to Wakeup_SW, uncheck the HW Connection option and set the Drive mode to Resistive pull up as Figure 45 and Figure 46 show. Enable Rising edge interrupt for this pin as Figure 47 shows. Because the switch SW2 on CY8CKIT-042 BLE is pulled down to ground when pressed, the resistive pull-up pin drive mode is required to detect a switch press event. The rising-edge interrupt is triggered when the switch is pressed and released.

Figure 45. Location of the Digital Input Pin Component

Figure 46. Digital Input Pin Configuration

Figure 47. Digital Input Pin Interrupt Configuration

16. Finally, drag and drop an Interrupt Component. Change the name to “Wakeup_Interrupt” and wire it to the Wakeup_SW pin’s irq output as Figure 48, Figure 49 and Figure 50 show.

Figure 48. Location of the Interrupt Component

Figure 49. Renaming an Interrupt Component



Figure 50. Wiring the Interrupt and Pin Components

17. After completing the schematic configuration, your

design should look similar to Figure 51.

Figure 51. Schematic Configuration

Note Blue dotted lines, the arrow mark, the LED symbol, and other text description in Figure 22 are only present for description purpose and are not mandatory for the functioning of your design.

18. Open the file BLE_FindMe.cydwr (Design-Wide Resource) file from Workspace Explorer and click the Pins tab. You can use this tab to select the device pins for the outputs (Advertising_LED, Hibernate_LED, and Alert_LED) and inputs (Wakeup_SW).

If your development kit has onboard LEDs and a switch, refer to the kit user guide for the required pin assignments. Figure 52 shows the pin configuration to connect the Advertising_LED, Hibernate_LED, and Alert_LED pins to the green, the red, and the blue LEDs, and the Wakeup_SW pin to the switch SW2 on the BLE pioneer kit respectively.

Figure 52. Pin Selection

If you are using your own board or a development kit with no LEDs and switch, select the appropriate pins. You can connect external LEDs and switch to the selected pins, as Figure 22 on page 25 shows.

19. Similarly, on the Clocks tab under the BLE_FindMe.cydwr file, configure the IMO to 12 MHz as Figure 53 shows.

Figure 53. Clock Configuration

20. Select Generate Application from the Build menu.

Notice in the Workspace Explorer window that PSoC Creator automatically generates source code files for the BLE, PWM, Clock, Digital Output Pin, Digital Input Pin, and Interrupt Components, as Figure 54 shows.

Figure 54. Generated Source Files



Part 2: Firmware Design There are four main firmware blocks that are required for designing BLE standard-profile applications using PSoC Creator:

1. System initialization

2. BLE stack event handler

3. BLE service-specific event handler

4. Main loop and low-power implementation

We will discuss details of these blocks with respect to the design that we configured in the previous section.

System Ini t ia l izat ion When the PSoC 4 BLE device is reset or wakes up from the hibernate mode, the firmware first performs the initialization which includes starting the PWM and enabling global interrupts. After the system is initialized, the firmware initializes the BLE Component, which internally initializes the complete BLE subsystem.

As a part of the BLE Component initialization, you must pass the event-handler function which should be called to receive events from the BLE stack. The BLE stack event handler shown in Code 2 is registered as a part of the BLE initialization. If the BLE Component initializes successfully, the firmware registers another event handler for the Immediate Alert Service (IAS)-specific events and switches control to the main loop thread. Figure 55 and Code 1 show the flowchart and the firmware source code for system initialization.

Figure 55. System Initialization Flowchart



Code 1. System Initialization Firmware

BLE Stack Event Handler The BLE stack within the BLE Component generates a list of events to provide the BLE interface status and data to the application firmware through the BLE stack event handler registered by you. The event handler must handle a few basic events from the stack such as device connection, turning on the stack, and configuring the stack appropriately to successfully establish and maintain the BLE link. For the Find Me Target application that we are creating, the BLE stack event handler must process all the events described in Table 5. The firmware and the flowchart for handling BLE stack events are shown in Figure 56 and Code 2.

Table 5. BLE Stack Events

BLE Stack Event Name Event Description Event Handler Action

CYBLE_EVT_STACK_ON BLE stack initialization completed successfully.

Start advertisement and reflect the advertisement state on the LED.

CYBLE_EVT_GAP_DEVICE_DISCONNECTED BLE link with the peer device is disconnected .

Restart advertisement and reflect the advertisement state on the LED.

CYBLE_EVT_GAP_DEVICE_CONNECTED BLE link with the peer device is established .

Update the BLE link state on the LED..

CYBLE_EVT_TIMEOUT BLE stack generic timeout event. Configure the device in hibernate mode if an advertisement timeout event is received.

#include <Project.h> int main() { CYBLE_API_RESULT_T apiResult; CyGlobalIntEnable; PWM_Start(); apiResult = CyBle_Start(StackEventHandler); if(apiResult != CYBLE_ERROR_OK) { /* BLE stack initialization failed, check your configuration */ CYASSERT(0); } CyBle_IasRegisterAttrCallback(IasEventHandler); }



Figure 56. BLE Stack Event Handler Flowchart

Code 2. BLE Stack Event Handler Firmware

#define LED_ON (0u) #define LED_OFF (1u) void StackEventHandler(uint32 event, void* eventParam) { switch(event) { case CYBLE_EVT_STACK_ON: case CYBLE_EVT_GAP_DEVICE_DISCONNECTED: /* Start BLE fast advertisement for 30 seconds and update link * status on LED */ CyBle_GappStartAdvertisement(CYBLE_ADVERTISING_FAST); Advertising_LED_Write(LED_ON); PWM_WriteCompare(LED_NO_ALERT); break; case CYBLE_EVT_GAP_DEVICE_CONNECTED: /* BLE link is established */ Advertising_LED_Write(LED_OFF); break;



BLE Service-Speci f ic Event Handler The BLE Component also generates events corresponding to each of the services supported by your design. For the Find Me Target application that we are creating, the BLE Component will generate IAS events that will let the application know if the Alert Level characteristic is updated with a new value. The flowchart and the firmware for handling BLE IAS events are shown in Figure 57 and Code 3.

case CYBLE_EVT_TIMEOUT: if(*(uint8 *) eventParam == CYBLE_GAP_ADV_MODE_TO) { /* Advertisement event timed out, go to low power * mode (Hibernate mode) and wait for an external * user event to wake up (reset) the device again */ Advertising_LED_Write(LED_OFF); Hibernate_LED_Write(LED_ON); PWM_Stop(); Wakeup_SW_ClearInterrupt(); Wakeup_Interrupt_ClearPending(); Wakeup_Interrupt_Start(); CySysPmHibernate();

/* Code execution never reaches here, wakeup from hibernate * is through device reset */

} break; default: break; } }



Figure 57. BLE IAS Event Handler Flowchart



Code 3. BLE IAS Event Handler Firmware

#define NO_ALERT (0u) #define MILD_ALERT (1u) #define HIGH_ALERT (2u) #define LED_NO_ALERT (0u) #define LED_MILD_ALERT (100u) #define LED_HIGH_ALERT (200u) void IasEventHandler(uint32 event, void* eventParam) { /* Alert Level Characteristic write event */ if(event == CYBLE_EVT_IASS_WRITE_CHAR_CMD) { uint8 alertLevel; /* Data structure that is returned as eventParam */ CYBLE_IAS_CHAR_VALUE_T *charValue = (CYBLE_IAS_CHAR_VALUE_T *)eventParam; /* Extract Alert Level value from the data structure */ alertLevel = *((charValue->value->val)); switch(alertLevel) { case NO_ALERT: PWM_WriteCompare(LED_NO_ALERT); break; case MILD_ALERT: PWM_WriteCompare(LED_MILD_ALERT); break; case HIGH_ALERT: PWM_WriteCompare(LED_HIGH_ALERT); break;

default: break; } } }



Main Loop and Low-Power Operat ion The main loop firmware in your design must periodically service the BLE stack-processing event and configure the BLESS block and the PSoC 4 BLE system into low-power mode between consecutive connection intervals. The main-loop flowchart and the firmware are as shown in Figure 58 and Code 4.

Figure 58. Firmware Main Loop Flowchart

Code 4. Firmware Main Loop Firmware

for(;;) { CYBLE_STATE_T bleState; /* Single API call to service all the BLE stack events. Must be * called at least once in a BLE connection interval */ CyBle_ProcessEvents(); bleState = CyBle_GetState(); if(bleState != CYBLE_STATE_STOPPED && bleState != CYBLE_STATE_INITIALIZING) { /* Configure BLESS in DeepSleep mode */ CyBle_EnterLPM(CYBLE_BLESS_DEEPSLEEP); /* Configure PSoC 4 BLE system in sleep mode */ CySysPmSleep(); /* BLE link layer timing interrupt will wake up the system */ } }



Part 3: Program the Device This section shows how to program the PSoC 4 BLE device. If you are using a development kit with a built-in programmer (BLE pioneer kit, for example), connect the kit board to your computer using the USB cable. For other kits, refer to the kit user guide.

Note The source project for this design is in PSoC Creator 3.1 or later under File > Example Project > select Keyword as Find Me > BLE_FindMe.

If you are developing on your own hardware, you need a hardware debugger, for example, a Cypress CY8CKIT-002 MiniProg3. In PSoC Creator, select Debug > Select Debug Target, as Figure 59 shows.

Figure 59. Selecting Debug Target

1. In the Select Debug Target dialog box, click Port Acquire, and then click Connect, as Figure 60 shows. Click OK to close the dialog box.

Figure 60. Connecting to a Device

If you are using your own hardware, make sure the Port Setting configuration under Select Debug Target window for your programming hardware is configured as per your setup.

2. In PSoC Creator, select Debug > Program to program the device with the project, as Figure 61 shows.

Figure 61. Programming the Device

3. You can view the programming status on the PSoC Creator status bar (lower-left corner of the window), as Figure 62 shows,

Figure 62. Programming Status



Part 4: Test Your Design This section describes how to test your BLE design using the CySmart PC application and mobile apps. The setup for testing your design using the BLE pioneer kit is shown in Figure 14.

1. Connect the BLE USB dongle to your Windows machine. Wait for the driver installation to complete.

2. Launch the CySmart PC application; it automatically detects the BLE USB dongle. Click Refresh if the BLE dongle does not show up in the Select BLE Dongle Target pop-up window. Click Connect as shown in Figure 63.

Figure 63. CySmart BLE Dongle Selection

3. Select Configure Master Settings and restore the values to default settings as shown in Figure 64.

Figure 64. CySmart Master Settings Configuration

4. Press reset or SW2 switch on the BLE pioneer kit to start BLE advertisements from your design.

5. On the CySmart application, click Start Scan. Your device name should show up in the Discovered Devices list.

6. Click Stop Scan and then click Connect to establish a BLE connection between the CySmart tool and your device.

7. Once connected, discover all the attributes on your design from the CySmart application and write a value of 0, 1, or 2 to the Alert Level characteristic under the Immediate Alert service, as Figure 65 shows. Observe the state of the LED on your device change per your Alert Level characteristic configuration.



Figure 65. Testing with CySmart PC Application



Similar to the CySmart PC application, you can also use the CySmart iOS or Android app to establish a BLE connection with your design and perform read or write operations on BLE service characteristics.

1. Turn on Bluetooth on your iOS or Android device.

2. Launch the CySmart app.

3. Press reset or the SW2 switch on the BLE pioneer kit to start BLE advertisements from your design.

4. Your device will automatically show up in the CySmart app scan screen. Select your device to establish a BLE connection.

5. Select the “Find Me” profile from the carousel view.

6. Select one of the Alert Level values in the Find Me profile screen and observe the state of the LED on your device change per your selection.

A step-by-step configuration screenshot of the CySmart mobile app is shown in Figure 66.

Figure 66. Testing with CySmart Mobile App

Design Source Unlike other Cypress application notes, the functional PSoC Creator project for this application note is not distributed on the application note webpage, but is part of PSoC Creator example projects. You can find the functional PSoC Creator project for this design in PSoC Creator 3.1 or later by selecting File > Example Project, and then selecting Keyword as Find Me > BLE_FindMe.



Summary

This application note explored the basics of BLE protocol and PSoC 4 BLE device architecture and development tools. PSoC 4 BLE is a truly programmable embedded system-on-chip, integrating BLE radio, configurable analog and digital peripheral functions, memory, and an ARM Cortex-M0 microcontroller on a single chip. Because of the integrated features and low-leakage power modes, PSoC 4 BLE is an ideal choice for battery-operated wearable, health, and fitness applications.

This application note also guided you to a comprehensive collection of resources to accelerate in-depth learning about PSoC 4 BLE.

Related Application Notes

AN92424 - Getting Started with PRoC BLE

AN91446 – Antenna Design Guide

Coming soon:

AN91184 – PSoC 4 BLE Designing BLE Applications

AN91162 – PSoC 4 BLE Creating Custom Profiles

AN92584 – PSoC 4 BLE/ PRoC BLE Measuring Power Consumption

AN94667 - BLE Crystal Oscillator Selection and Tuning Techniques

About the Author

Name: Krishnaprasad M V (KRIS).

Title: Applications Engineer Staff

Background: Krishnaprasad has a BSEE from National Institute of Engineering, Mysore, India



Appendix A: BLE Device Family Comparison

Table 6 summarizes the features and capabilities of the BLE device family from Cypress.

Table 6. BLE Device Families

Features

Device Family

CY8C41x7-BL CY8C42x7-BL CYBL10X6X

BLE Subsystem BLE radio and link-layer hardware blocks with BLE 4.1- compatible protocol stack

BLE radio and link-layer hardware blocks with BLE 4.1-compatible protocol stack

BLE radio and link-layer hardware blocks with BLE 4.1-compatible protocol stack

CPU 24-MHz ARM Cortex-M0 CPU with single-cycle multiply

48-MHz ARM Cortex-M0 CPU with single-cycle multiply

48-MHz ARM Cortex-M0 CPU with single-cycle multiply

Flash Memory 128 KB 128 KB 128 KB

SRAM 16 KB 16 KB 16 KB

GPIOs Up to 36 Up to 36 Up to 36

CapSense Up to 35 sensors Up to 35 sensors Up to 35 sensors

CapSense Gestures On selected devices On selected devices On selected devices

ADC 12-bit, 806 ksps SAR ADC with sequencer

12-bit, 1 Msps SAR ADC with sequencer

12-bit, 1 Msps SAR ADC with sequencer

Opamps 2 programmable opamps that are active in deep-sleep mode

4 programmable opamps that are active in deep-sleep mode

None

Comparators 2 low-power comparators with the wakeup feature

2 low-power comparators with the wakeup feature

None

Current DACs One 7-bit, and one 8-bit One 7-bit, and one 8-bit None

Power Supply Range 1.9 V to 5.5 V 1.9 V to 5.5 V 1.9 V to 5.5 V

Low-Power Modes Deep-sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA

Deep-sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA

Deep-sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA

Segment LCD Drive 4-COM, 32-segments LCD drive on selected devices

4-COM, 32-segments LCD drive on selected devices

4-COM, 32-segments LCD drive on selected devices

Serial Communication 2 independent serial communication blocks (SCBs) with programmable I2C, SPI, or UART

2 independent SCBs with programmable I2C, SPI, or UART

1 or 2 independent SCBs with programmable I2C, SPI, or UART

Timer Counter Pulse-Width Modulator (TCPWM)

4 4 4

Universal Digital Blocks (UDBs)

None 4, each with 8 macrocells and one datapath. Can be used to synthesize additional digital peripherals (Timer, Counter, PWM) or communication interfaces (UART, SPI)

None

Additional Digital Peripherals (I2S, PWM)

None Yes (UDB-based digital peripherals On selected devices)

Yes (Fixed-function blocks on selected devices)

Clocks 3-MHz to 24-MHz IMO

32-kHz ILO

24-MHz ECO

32-kHz WCO

3-MHz to 48-MHz IMO

32-kHz ILO

24-MHz ECO

32-kHz WCO

3-MHz to 48-MHz IMO

32-kHz ILO

24-MHz ECO

32-kHz WCO



Features

Device Family

CY8C41x7-BL CY8C42x7-BL CYBL10X6X

Power Supply Monitoring

Power-on reset (POR) Brown-out detection (BOD) Low-voltage detection (LVD)

POR BOD LVD

POR BOD LVD

Package 56-QFN (7.0 × 7.0 × 0.6 mm) and

68-WLCSP (3.52 ×3.91 × 0.55 mm)

56-QFN (7.0 × 7.0 × 0.6 mm) and

68-WLCSP (3.52 ×3.91 × 0.55 mm)

56-QFN (7.0 × 7.0 × 0.6 mm) and

68-WLCSP (3.52 ×3.91 × 0.55 mm)



Appendix B: Cypress Terms of Art

This section lists the most commonly used terms that you might hear while working with Cypress’s PSoC family of devices.

PSoC – PSoC is a programmable, embedded design platform that includes a CPU, such as the 32-bit ARM® Cortex™-M0, with both analog and digital programmable blocks. It accelerates embedded system design with reliable, easy-to-use solutions, such as touch sensing and enables low-power designs.

PSoC 4 BLE – A PSoC 4 IC with an integrated BLE radio that includes a royalty-free BLE protocol stack compatible with the Bluetooth 4.1 specification.

PSoC Creator – PSoC 3, PSoC 4, and PSoC 5LP Integrated Design Environment (IDE) software that installs on your PC and allows concurrent hardware and firmware design of PSoC systems, or hardware design followed by export to other popular IDEs.

Components – Free embedded ICs represented by an icon in PSoC Creator software. These are used to integrate multiple ICs and system interfaces into one PSoC Component that are inherently connected to the MCU via the main system bus. For example, the BLE Component creates Bluetooth Smart products in minutes. Similarly, you can use the Programmable Analog Components for sensors.

Component Configuration Tools – Simple graphical user interfaces in PSoC Creator that embedded in each Component. It is used to customize the Component parameters and is accessed by right-clicking a Component.

PSoC Programmer – PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer is integrated with PSoC Creator to program PSoC 3, PSoC 4, PRoC, and PSoC 5LP designs.

MiniProg3 – A programming hardware for development purposes that is used to program PSoC devices on your custom board or PSoC development kits that do not support a built-in programmer.



Document History

Document Title: Getting Started with PSoC® 4 BLE - AN91267

Document Number: 001-91267

Revision ECN Orig. of Change

Submission Date

Description of Change

** 4564230 KRIS 11/07/2014 New Application Note



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© Cypress Semiconductor Corporation, 2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

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Getting Started with PSoC 4 BLE - cypress.21ic.comcypress.21ic.com/Public/Document/应用笔记/AN91267_001-91267.pdf · Software Version: PSoC Creator™ 3.1 Related Application