HARP: Hard-Wired Routing Pattern FPGAs Cristinel Ababei , Satish Sivaswamy ,Gang Wang , Kia Bazargan...
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HARP: Hard-Wired Routing Pattern FPGAs Cristinel Ababei , Satish Sivaswamy ,Gang Wang , Kia Bazargan , Ryan Kastner , Eli Bozorgzadeh ECE Dept. ECE Dept. Comp. Science Dept. Univ. of Minnesota Univ. Of California Univ. of California Minneapolis Santa Barbara Irvine MN – 55455 CA – 93106 CA – 92697
HARP: Hard-Wired Routing Pattern FPGAs Cristinel Ababei , Satish Sivaswamy ,Gang Wang , Kia Bazargan , Ryan Kastner , Eli Bozorgzadeh ECE Dept
HARP: Hard-Wired Routing Pattern FPGAs Cristinel Ababei ,
Satish Sivaswamy ,Gang Wang , Kia Bazargan , Ryan Kastner , Eli
Bozorgzadeh ECE Dept. ECE Dept. Comp. Science Dept. Univ. of
Minnesota Univ. Of California Univ. of California Minneapolis Santa
Barbara Irvine MN 55455 CA 93106 CA 92697
Slide 2
Introduction FPGAs Vs ASICs Lower NRE costs Shorter time to
market Num of units Total cost ASIC FPGA NRE cost Eli:You may want
to skip this slide
Slide 3
Problems with FPGAs Circuit Delay: Delay increases due to
programmable switches in the FPGA routing architecture Area:
Configuration cells and programmable resources incur substantial
area penalty Power: Typically not suited for low power applications
PerformanceCost ASIC FPGA ASIC FPGA Time to market ASIC FPGA We
need to improve
Slide 4
Motivation Interconnects account for 60% of delay, 75% of area
and 80% of power [ Microsystems Tech. Lab @ MIT ] Are we providing
too much flexibility? S N W E W N S E Island style routing
architecture connection block switch block S W N E
Slide 5
Our Goal Reduce the number of switches by hard-wiring some
intersections Create a mixture of hard wired and flexible switches
HARP switches Maintain high degree of routability HARP
switchbox
Slide 6
Outline Routing Pattern Analysis HARP based design flow HARP
distribution Simulations Conclusion
Slide 7
Pattern Analysis Route of a multi-terminal net is a Rectilinear
Steiner tree Pattern is a junction in the RST Idea is to form
patterns inside switchboxes - HARPs Source Sink 1 Sink 2 Sink 3
Sink 4
Slide 8
Pattern Analysis Statistical Analysis of routing profiles helps
guide HARP insertion Place and route benchmark circuits and
determine frequency of various patterns Single segment and
multi-segment architectures are considered
Slide 9
Pattern Types 11 Possible connection patterns inside switch
boxes Source Sink2 Sink3 Sink1 Sb A Sb C Sb B - Not connected
Slide 10
Pattern Length Pattern length: How much each HARP extends along
different directions Identify valid pattern Trace along valid
directions from the switchbox Minimum length among all directions
is the pattern length Source Sink2 Sink3 Sink1 Sb A Sb C Sb B - Not
connected 4 6 length 4
Slide 11
Results of Pattern Analysis For multi-seg architecture, % of ,|
decreases and % of L increases
Slide 12
Results of Pattern Analysis Percentages of patterns remains
almost the same Architecture seems to have a bigger impact than the
routing algorithm
Slide 13
Results of Pattern Analysis Distribution for Horizontal and
vertical Patterns percentage Pattern length
Slide 14
Proposed Design Flow Joint Pattern usage Analysis VPR Place and
route Statistical Pattern Finder (VPF ) MCNC circuits HARP
Architecture design Place & Route on HARP Traditional
Architecture definition Compare delay Area & Power HARP-based
Routing Architecture Design Flow
Slide 15
Routing Architecture Design with HARPs HARPs are associated
with a length, type and location Length is related to channel
segmentation Subset switch box and virtex like channel segmentation
is used in this work Challenge is to distribute HARPs inside
switchboxes
Slide 16
Routing Architecture Design New switchbox design includes HARPs
besides flexible switches L L T T V H
Slide 17
FPGA Routing Architecture Routing architecture is represented
as a routing graph Routing segments, IO pins represented as nodes
Switches are represented as edges Wire 2 Wire 1 Wire 3 Wire 4 LUT
in 1in 2 out Source Wire 3Wire 4 Wire 2 Wire 1 in 1in 2 Sink
Slide 18
Routing Architecture Routing graph construction changes with
HARPs Only those edges that form the pattern are present in the
routing graph A B C D Normal Switch B A A B D D C C HARP switch C A
B D
Slide 19
Routing Architecture HARPs are not allowed to connect back to
back Dangling branches add capacitance Avoid forming large trees of
patterns LT dangling branch SB A B
Slide 20
HARP distribution Populate pattern distribution array with
symbolic entries for different patterns Scan FPGA chip and look at
candidate locations for HARP insertion Select a pattern from P and
an orientation for the pattern For HARPs, insert only those edges
that form the pattern into the routing graph and save switch info.
All edges are inserted for flexible switches C VLHTLV T HL
Slide 21
Modeling Changes Capacitance of HARPs include capacitance of
all segments forming it When only some segments of a HARP are used,
the rest are invalidated Area, delay model of VPR is used Flexible
power model developed by Kara Poon et.al. is used CLB SB To sinks
Is invalidated CLB out Hard-wired L
Slide 22
Simulation Results Area X 10 6 Delay X 10 -7 5% Improvement in
Area 22% Improvement in Delay
Slide 23
Simulation Results Channel Width Energy X 10 -7 30% Improvement
in Energy 16% increase in Channel Width
Slide 24
Routing Architecture Relax constraint of not allowing HARPs to
connect back to back HARP overlap SB 1 SB 2 SB 1 HARP SW SB1 flex.
SW
Slide 25
Simulation Results Delay X 10 -7 Area X 10 6 Delay improvement
is 24%
Slide 26
Simulation Results Channel width Energy X 10 -7 Improvement in
Energy is 32% Channel width increases by 20%
Slide 27
Limitations and Future work The patterns are distributed
randomly inside switchboxes Switchbox layout is an issue as tiling
cannot be applied here Future work is to develop a switchbox that
can be laid out by tiling and replicating SB1 SB2 SB1 SB2
Slide 28
Conclusion HARP: Explores the possibility of reducing the
number of switches by hardwiring certain switches Delay benefit ~
24% Energy savings ~ 30% Area reduction ~5% Thank You