Hasler IIT Lecture01 A

8/10/2019 Hasler IIT Lecture01 A

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.?@ ;0)#1'1("0 A*0'%):"#

8/B9 %14

C500*#(

@5D(=0*1="&,

!E F4GHIHF

9"E J4KJFL3M0.4 0.5 0.6 0.7 0.8 0.9

1A

Gate voltage (V)

Draincurrent(A)

10nA

1nA

10pA

100nA

100pA

.'1/)(


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Diffusion of Charge over Barrier

V 4UT)

(Saturation, IR~0, Vds> Von)

I = %f

%r


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Measured Channel Current

0.4 0.450.5 0.550.6 0.650.70.750.8 0.850.910-11

10-10

10-9

10-8

10-7

10-6

Gate voltage (V)

Draincurrent(A)

!E F4GHIHF

9"E J4KJFL3M

0.6 0.65 0.7 0.75 0.8 0.85 0.910-12

10-11

10-10

10-9

10-8

10-7

Source voltage (V)

Draincurrent(A)

_;E KG4HL/-

C500*#( 3"0 7)(* @`**U C500*#( 3"0 @"50


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Measured Channel Current


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.?@^V; ;*/U .",*&'#8 3"0 C'0


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View of Scaling FET Devices

2F

F

6F

2F

F

6F

Key steps to Shrinking an FET

Shrink lateral dimensions (lithography)

To keep gain constant (VA constant),

decrease size of depletion regions (x2)

increase substrate doping (x4)

Then, to keep !(sub VT slope) constant,

decrease size of gate oxide

F minimum channel length

Tox (min) ~ 2nm (FET)

~ 5-6nm (FG FET)

(multiple oxides available)

Classic Scaling (1971 )

Shrink

x2

What if we dont follow the steps?

!decreases.

If starting != 0.75,

for x2 shrink, != 0.67



Decreased gain (effective L changes),

punchthrough (effective L ~ 0)


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@]M. C*&& W)1'

c

c

c

c

c

c

c

c

9#J

9#K

9#e

9#L

]*), C'0


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W)1'< d)(


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A]M. C*&& W)1'


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W)1'< ]?. C"#


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W)1'< V2]?. C"#


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Floating-Gate Circuit BasicsCapacitor-Based Circuit Design

Resistors and Inductors define the

circuit dynamics

Capacitors are the natural elements

on silicon ICs

GND

9"5(

-8

GND

9"5(

-)

-D

CJ

CK

-8

GND-8%

GND-8 %

-)

-D

CJ

CK

Basic MOSFET Transistor

Basic FG MOSFET Transistor


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;>U*1 "3 9#(*80)(*, C)U)


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_- 2="("'#b*


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V&*Y 3

JFH/-

@


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Creates a DC Measurement

of classic C-V curves

Gain = "Vout/ "V1

= - C1/ Cf

V1

V2

V3

V4

C4

C1

C2

C3

Cf

Vref

Vout

-1.5 -1 -0.5 0 0.5 10

0.5

1

1.5

2

2.5

3

3.5

4

Gate-to-well voltage (V)

Capaci

tance(pF)

Accumulation

Depletion

6"` ("


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VV2]?. C*&&1(EEPROM = Electrically Erasable PROM)

Modification of the cell for programming

Eliminate need for UV

Early cells: Tunneling to program and erase (80s, early 90s)

Flash EEPROM: Tunneling to program, and

Injection for block erase

Most current cells use injection and tunneling

p-substrate

n+n

+p+

bulkcontact

drainsource gate


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Electron Transport in a subthreshold nFET


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.*)150*/*#(1 )#, .",*&'#8 "3 6"($

V&*


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f0':#8 9#,'%',5)& A*%'


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U^V; 6"($V&*


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Scaling of EEPROM devices

[1] N. Shibata, et. al, A 70 nm 16 Gb 16-Level-Cell NAND flash Memory, JSSC, vol. 43, no. 4, 2008 (ScanDisk / Toshibha)

[2] T. Futatsuyama1, et. al, A 113mm2 32Gb 3b/cell NAND Flash Memory, ISSCC 2009.

[3] C. Trinh1, et. al, A 5.6MB/s 64Gb 4b/Cell NAND Flash Memory in 43nm CMOS, ISSCC 2009 (ScanDisk / Toshibha)

[4] R. Zeng1, et. al, A 172mm2 32Gb MLC NAND Flash Memory in 34nm CMOS, ISSCC 2009 ( Intel & Micron)

Wide use: Memory Sticks, Flash Cards (i.e. SD), etc.

Most approaches store multiple levels per cell (2, 4, 8, 16!1-4 bits/ cell)

Typical Densities: 70nm Flash 1-2 G cells / cm2 (production)

45nm Flash 6-7 G cells / cm2 (production)

32nm Flash ~ 10 G cells / cm2 (development)

(densities include all support infratructure / readout / programming)

All cells report > 10 year lifetime for storage,

consistant with 5-6nm oxide thicknesses (and our FG measurements as well)

(45nm and below has some modified dielectrics),

with ns read access times and ms (or less) individual cell write times

(consistant with our history of FG devices)


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Hasler IIT Lecture01 A