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CMOS Ultra Low Noise LNA IC

Designs for Radio Astronomy

Jim Haslett and Leo Belostotski

Department of Electrical and Computer

Engineering

The University of Calgary, Alberta, Canada

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7/27/2006Copyright 2006 by J.W. Haslett and L.

Belostotski, University of Calgary 2

Outline

International SKA Project Overview

CMOS LNA Design Overview NFmin, Gain and Linearity

Technology Scaling Design Examples and Measurements

Conclusions

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The International Square Kilometer

Array Project

Next Generation Radio Telescope

Two orders of magnitude increase insensitivity over existing facilities at meter tocentimeter wavelengths

1 million square meter collecting area 100times larger than the Very Large Array near

Socorro, New Mexico Will probe the gaseous component of the early

universe

Interferometric array of individual antennas,

synthesizing an aperture of several thousandkilometers

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Countries Involved in SKA Design

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SKA Scenarios

LNSD (USA), LAR (Canada), KARST (China), Cylinders (Australia), AA

(Netherlands), NT (Australia, India, S. Africa)

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The Latest Reference DesignAperture Plane

Array at lower

frequencies

Parabolic Focal

Plane Array athigher

Frequencies

Donut shaped

core 100kmacross-aperture

plane array in the

middle, parabolic

array next, then

spiral arms out to

a few thousand

kilometers

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The Latest Reference DesignAperture Plane

Array at lower

frequencies

Parabolic Focal

Plane Array athigher

Frequencies

Donut shaped

core 100kmacross-aperture

plane array in the

middle, parabolic

array next, then

spiral arms out to

a few thousand

kilometers

Aperture Array

Focal Plane Array

Focal Plane Arrays

100 km

1000s of km

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The SKA Project-Major Challenges

Need LNA noise figures of the order of 0.3 dB orbetter from 700 MHz to 1.5 GHz (broadband)

Antenna to LNA connection critical

Must operate at ambient temperature-COST!

Need low power consumption-particularly in theCanadian scenario, where the antenna array is

suspended Ideally would like CMOS in order to integrate with

the rest of the signal chains

Noise from gate leakage current an issue-thermalor shot noise?

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The SKA Project-Noise Background

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Minimum Achievable Noise Figure in

Two Port Circuits is is thermal noise of thesource admittance Ys

en is input-referredequivalent noise voltage

in is input-referred

equivalent noise current

en and in are correlated withcorrelation coefficient c

Noisy Two-Port

22

2

s n s n

s

i i Y eF

i

+ +=

Total output noise powerF

Output power duetosignal source

=

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Minimum Achievable Noise Figure

min

2

2

min

1

0 , 0 .

.[4

,

2 ]

opt opt

S S

S S S opt opt o

n op

pt

nn

nS opt

t c

S

Minimizenoise factor bycalculating

F Fto find G and to find BG B

Y G jB Y G jB

ewhereR

kT f

Ingeneral

F

RF F Y Y

G

R G G

= =

= + =

= + +

= +

=

= +

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Fminvs Tmin

Radio Astronomers use

noise temperature in

Kelvins rather than noise

figure in dB

minmin

1

1

noise

ref

ref

TF

T

T

F T

= +

= +

Noise Figure,

dB

Noise

Temperature, K

0.7 50.7

0.3 20.7

0.15 10.2

0.07 4.7

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Noise Performance of Transistors Used

for Radio Astronomy

From Sander

Weinreb, Caltech

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Transistors for Radio Astronomy

There is a strong desire to use MOS transistors for this

application, running at ambient temperature if possible

dramatically lower cost if cryogenic cooling not needed

fully integrated signal processing chain

At present, there is virtually no literature showing measured

very low noise CMOS LNAs for radio astronomy applications

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MOS Noise Generators

The conductance gg isnoiseless in this equivalentcircuit. It can often beneglected in noise

calculations if

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MOSFET Fmin

2

min

2

1 2 [ ] 1 (1 )5n opt c TF R G G c

= + + = +

is a strong function of device parameters and biasminF

The optimum source admittance for minimum MOS noise figure turns

out to be

where . The optimum source admittance is a parallel R-L

circuit, but with an inductive component that is inversely proportional

to frequency, making it difficult to match over a broad bandwidth.

22

(1 ) [1 ]5 5opt gs gsY C c j C c

=

m

do

g

g =

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MOS Transistor Noise Performance

90 nm TSMC CMOS

90nm TSMC Data

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MOS Transistor Noise Performance

P.H. Woerlee, M.J. Knitel, R. van Langevelde, D.B.M. Klassen, L.F. Tiemeijer, A.J. Scholten and A.T.A.

Zegers-van Duijnhoven, RF CMOS performance Trends, IEEE Transactions on Electron Devices, vol. 48,

no. 8, pp.1776-1782, August 2001.

Note the

minimum at

approximately0.15mA/um,

regardless of

process

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Common Practice in Astronomy

Use classical noise minimization at thehigh frequency edge, and obtain Fminby using high quality passives to get

Yopt. Has been used mainly for HEMT

devices such as GaAs and InP

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The Problem with the Classical

Approach

Only works narrowband No power match, resulting in loss of gain

and some polarization issues

The challenge: How can we get a real input impedance in

CMOS while still working nearFmin?

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Achieving a Resistive Input Impedance

Shunt input resistor to CS stage Unacceptably high noisefigures for many applications

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Shunt-Series Amplifier often used for broadband circuits

Noise Figure substantially less thanshunt circuit but noise figure toolarge and power hungry

These ignore

Rs, RL

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Common Gate Amplifier (Some IP3 issues)

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Inductor Degenerated Circuit

The addition of a source

degeneration inductor to thecommon source stage does not

affect the minimum noise

figure (if it is lossless), but it

facilitates a real inputimpedance so that we can get a

power match.

We can also add Lg to change

resonant frequency, withoutpenalty if lossless.

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Inductor Degenerated Circuit

1( )

.

1

2

1

2 2

min s g s T s

gs gs

s T s

S

o gs s

gs S s d m gs m S s

m Tmeff m S

gs o S o S

gZ s L L L L at resonancesC C

and wechooseR L for power match

Q factor of theinputnetwork QC R

At resonancev Q v soi g v g Q v

gand G g Q

C R R

Thenoverall voltagega

= + + +

=

= =

= = =

= = =

( )

meff Lin G R

Itisinterestingtonotethat gainisindependent

of transistor width butnot gateoverdrive

=

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Optimizing the Inductor Degenerated

Circuit for Narrowband ApplicationsLeonid Belostotski and James W. Haslett, Noise

Figure Optimization of

Inductively-Degenerated CMOS LNAs with

Integrated Gate Inductors IEEE TransactionsOn Circuits And Systems-I: Regular Papers, Vol.

53, no. 7, pp.1409-1422, July 2006.

This paper corrects the previous literature and

describes a method of optimizing thenarrowband source degenerated LNA to achieve

power match and minimum noise figure while

accounting for important parasitics, in particular

gate resistive losses due to gate finger

resistance and gate inductor losses.

Note the addition of Cex: G. Girlando and G. Palmisano, Noise Figure and Impedance Matching in RFCascode Amplifiers, IEEE Transactions on Circuits and Systems, Vol. 46, pp. 1388-1396, Nov. 1999.

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Optimizing the Inductor Degenerated Circuit

Design Strategies:1). Classical optimization

- lowest noise figure for a given transistor with a given bias

- no tools to size and bias transistor at optimum

- does not guarantee power match to 502). Shaeffer and Lee, 1997

- finds optimum Q of input network that allows LNA to nearly achieve

minimum noise figure

- does not address the loss of the gate inductor or other gate parasitics

such as gate finger resistance, that may dominate the noise figure

3.) Andreani and Sjoland, 2001

- designs for minimum achievable noise figure in CMOS using an

external gate source padding capacitance

4.) Belostotski and Haslett, 2006- designs for minimum achievable noise figure under a series of

constraints, including lossy gate inductor and other gate parasitics

O i i i h I d D d Ci i

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Optimizing the Inductor Degenerated Circuit

Belostotski, L. and J. W. Haslett, Noise Figure Optimization of Inductively-Degenerated CMOS LNAs with Integrated

Gate Inductors IEEE Transactions On Circuits And Systems-I: Regular Papers, Vol. 53, no. 7, pp.1409-1422, July 2006.

Introducing constraints while including all gate parasitic resistances:

1). PC (Power Constrained) optimization

- lowest noise figure but LNA gain may be low

- may require more than one design cycle2). PGC (Power and Gain Constrained) optimization

- lowest noise for a given gain

- single design cycle

3). PGRC (Power, Gain and Source Resistance Constrained) optimization

- does not guarantee the lowest noise

- noise figure approaches that of PC optimization when Q of the gate

inductor is very large

Belostotski, L. and J.W. Haslett, On Selection of Optimum Signal Source Impedance for Inductively-Degenerated CMOS

LNAs, IEEE Canadian Conference on Electrical and Computer Engineering, Ottawa, Canada, pp. 1435-1440, May 2006.

O d C

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Optimizing the Narrowband Circuit

TSMC

180nmCMOS

[1] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier,

IEEE J ournal of Solid-State Circuits, vol. 32, no. 745-759, May 1997.

B db di h N b d Ci i

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Broadbanding the Narrowband Circuit

Hu, R. "An 8-20-GHz Wide-band LNA Design and the Analysis of Its Input Matching Mechanism," IEEE Microwave

and Wireless Components Letters, vol. 14, no. 11, pp. 528-530, November, 2004. (GaAs)

Exploiting Cgd and choosing ZL appropriately allows the circuit to bebroadbanded


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Broadbanding the Narrowband Circuit

Belostotski, L., J.W. Haslett and B. Veidt, Wide-band CMOS Low Noise Amplifier for Applications in RadioAstronomy, IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006, pp.1347-1350

Exploiting Cgd andchoosing ZLappropriately

allows the circuit

to bebroadbanded

NOTE


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Equivalent Circuit With Capacitive Load CL,

including the Rds

of the input transistor. Dotted

components result if a cascode transistor is used, where gm of the cascode transistor is

assumed to be the same as gm of the input transistor.

Broadbanding the Narrowband CircuitThese two

components are

large, so that the

Ygd network

resonates at a

lower frequencythan the Zgsnetwork. Past the

resonant point, this

branch looksinductive and

dependent on CL.

Belostotski, L., J.W. Haslett and B. Veidt, Wide-band CMOS Low Noise Amplifier for Applications in Radio Astronomy, IEEE

International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006, pp.1347-1350

B db d LNA D i S

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Start with a source degenerated narrowband LNA with avery large load capacitor connecting the output to a cascode

transistor.

Choose the quality factor of the input network formed by Lgand Zgs based on bandwidth requirements, essentially setting

the bandwidth.

Design the LNA to resonate at the high band edge. Thecircuit can be designed to approach Fmin here.

CL is then reduced to bring the power match to the middle of

the band (changing CL does not affect the noise figure).

Model all components accurately to finalize the design.

Broadband LNA Design Strategy

B db d LNA D i E l

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Belostotski, L., J.W. Haslett and B. Veidt, Wide-band CMOS Low Noise Amplifier for Applications in Radio Astronomy, IEEE

International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006, pp.1347-1350

Broadband LNA Design Example

180 nm CMOS Design Example: Noise Figure, NF, and minimum noise figure, Fmin, of the LNA

at each of the 4 design steps. Curves 1 are of the LNA matched at 1.4 GHz. Curves 2 are of theLNA tuned to center of the band by the reduction ofCL. Curves 3 are of the LNA with accuratemodels for passive components. Curves 4 are of the LNA with short channel noise parameters.

Passives and Interconnect Modeling

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Passives and Interconnect Modeling

and Design are Critical Must size metal traces, vias and gate fingers to

handle the relatively large currents-required

modification of the transistor layout Source inductor was generated as a slab style

inductor

Net gate finger resistance, including vias, must beminimized-contributes directly to noise figure

All interconnect must be modeled as transmissionlines-stability issues

Bond pads are shielded and modeled as well Substrate coupling must be minimized by shielding

interconnect

Transistor Layout triple well

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Belostotski, L.

Transistor Layout-triple well

Multiple Transistor Connections

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Belostotski, L.

Multiple Transistor Connections

Die Photo Differential Shielded LNAs

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90 nm CMOS

Die Photo Differential Shielded LNA s

Shielded LNANon-Shielded

LNA

Test Structures

Test Setup

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Test Setup

Test Setup

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Test Setup

Our Latest Measurements

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Our Latest Measurements

This verifies that CMOS running at ambient

temperature can be a viable solution for the SKA

Measurements

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Measurements

Measurements

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Measurements

Frequency=

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Future Work-Increasing Source

Resistance

R >50 improves the noise figure

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Rs>50 improves the noise figure

Parameters

for 180nm

CMOS

=2/3

=4/3

c=0.395jPD=50mW

Vod0.1V

f0=1.4GHz

Qind=5

Rs=155

Rs,0=50

Why does Rs>50 improve the noise

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y s p

figure? Look at optimum Q of the input network for

clues

Rs=155

stRCQ

1

( ) constantsRQ

Rs,0=50

Why does R >50 improve the noise

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Why does Rs 50 improve the noise

figure?2. Since Qopt is constant, then increasing Rs decreases Ct and

decreases the noise figure since

higherT,LNA=gm/Ct lower NF higher Lg but its noise contribution is less significant at

high Rs3. Other terms affecting the noise figure experience only slight

change

+=

2

,

2

01

LNAT

m

s

gR

R

RF

( )22 2

2

21 1 2 1

5 5

gs gs

s

t t

C CQ c

C C

= + +

where R=Rs+Rg and

Advantages of a non-50 LNA

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Advantages of a non 50 LNA

1. Power saving for the same Q of input network2. Power can be traded-off with the noise figure

3. Noise contribution of the gate inductor is reduced

4. When integrated with antenna, high impedance

antennas required which are easier to design

5. Removes the need for lossy matching circuit between

antenna and LNA when antenna is designed atoptimum Rs

6. Ceramic filters, commonly placed between an LNA and

an antenna, favour input/output impedance higher than50

Disadvantages of a non-50 LNA

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d g 50 N

1. Equipment with non-50 impedance is

required

2. Fewer choices for off-the-shelf filters and

antennas

3. Noise contribution of LNA biasing network

and substrate becomes dominant at high

signal source resistance

Conclusions

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1. Next generation radio telescope project

described

2. CMOS LNA design strategies presented

3. Technique for broadbanding the narrowband

source degenerated cascode LNA circuit

described

4. Latest measurements on very low noise90nm CMOS LNA presented

References

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Acknowledgement

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g

Natural Sciences and Engineering Research

Council of Canada

Alberta Provincial Governments iCORE

program

Dominion Radio Astrophysical Observatory,NRC

CMC Microsystems TRLabs

Documents

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