HiPEACinfo 46

Spring 2016

Computing

Systems Week

Porto

46APPEARS QUARTERLY | APRIL 2016INFO

Security, the IoT and high-availability cloud

Technology Transfer Awards special

Creating a successful technology spin-off

HiPEAC16 keynote speakers discuss security, the IoT and cloud computing

HiPEAC Technology Transfer Award winners

What’s new in European research

10 13 18

contents

3 Welcome

Koen De Bosschere

4 Policy corner

Crossing virtual borders with the Digital Single Market

Sandro D’Elia

6 News

10 HiPEAC voices

HiPEAC16 keynote speakers on security, the IoT and

cloud computing

Ruby B Lee, Krisztián Flautner and Valentina Salapura

13 Technology Transfer special


Said Hamdioui, Giorgos Dimitrakopoulos, Roman Trobec and Aleksandra Rashkovska

17 Innovation Europe


Jon Perez, Cristina Zubia, Georgios Karakonstantis, Josip Knezović and Sabri Pllana

20 Tech Transfer: success stories

From research to business: the emmtrix story

Timo Stripf, Frederik Riar and Juergen Becker

23 SME snapshot

Verifying real-time embedded software at Rapita Systems

Jamie Pearce

24 Industry focus

Infineon TriCore microcontrollers: turbocharging

the automotive sector

Rafael Zalman and Knut Hufeld

25 Peac performance

Extreme Value Theory / Matching processors to big

data needs

Petar Radojković, Paul Carpenter, Jaume Abella, Francisco J. Cazorla and John Goodacre

28 HiPEAC futures

Career talk: Linda Dewar, EPCC

HiPEAC collaboration grants: Portuguese-German

expertise delivers more efficient video decoding

HiPEAC internships: On Thales’ radar, from Sofia to Paris

Three-minute thesis: Harnessing GPUs to optimize

bioinformatics analytics

Best FPGA-related master’s thesis 2015

HiPEAC is the European network on high performance and embedded architecture and compilation.

hipeac.net

HiPEAC4 has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreement no. 687698.

Cover photo: Martin Lehmann

Editor: Madeleine Gray

Email: [email protected]

@hipeac

hipeac.net/linkedin

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HiPEACINFO 462

From research to business:the emmtrix story


Technology opinion: Matching processors to big data needs

20 23 26

It was with deep sadness that I learned that Nacho Navarro, one of the most active

partners of HiPEAC suddenly passed away at the age of 58 on 28 February. Nacho joined

HiPEAC on the day it started in 2004. He participated in almost all the events HiPEAC

organized over the years, and he very rarely missed a steering committee meeting. I

remember him as bon vivant, optimistic, friendly, and always willing to organize an

event in his home town of Barcelona. He is probably the person who arranged the great-

est number of events for our network, and he was the perfect local organizer. I vividly

remember how he managed to find a solution for the ACACES summer school a few

weeks after the earthquake in L’Aquila in 2009. I also have very fond memories of his

memorable celebration of 10 years of HiPEAC in 2014 in Barcelona. Nacho was an inte-

gral part of HiPEAC, and HiPEAC has lost one of its biggest supporters in Europe. This

is how I want to remember him. He will be missed. May he rest in peace.

You will no doubt have noticed that we have changed the look-and-feel of HiPEAC info.

In future, we want it to be a magazine rather than a newsletter, bringing you the best

stories from the network and showing the world what our 1700 members have to offer.

The HiPEAC community should get out of its comfort zone and connect more actively to

other communities. We own the expertise and the technology to help solve some of

society’s most urgent challenges like the ageing population, healthcare, the environ-

ment, energy, mobility and education. Rather than waiting until people knock on our

door and ask for help, we should knock on their doors and ask them how we can help

them. The HiPEAC newsletter is just one of a range of ways in which we will be reaching

out to new audiences.

Many of you will read this newsletter when you arrive at the HiPEAC spring computing

systems week in Porto. This is the first computing systems week of HiPEAC4. It is again

packed with technical events. Organizing a networking event always requires lots of

energy from the local organizer, and I would therefore like to thank our Portuguese

members for hosting the event this time.

Koen De Bosschere, HiPEAC coordinator

welcome

HiPEACINFO 46 3

These are testing times for Europe. Wars

are raging on our doorstep, causing

numerous refugees to arrive on the conti-

nent, and the temptation to build walls

and close borders is strong everywhere.

Terrorism is becoming a constant fear, and

for the first time there is the real possibil-

ity that a member state will leave the

European Union, while the economy is

still plagued with high unemployment in

many regions and a fragile banking sys-

tem. It is not the first crisis, and will not be

the last, but things are definitely not easy.

The European Union is responding to this

crisis with many different measures, some

of them directly linked to a sector with

which we’re more familiar: digital tech-

nologies. In Euro jargon many of these

measures go under the name Digital

Single Market, or DSM (in Brussels acro-

nyms grow fast – probably due to the

weather).

The main thing that keeps Europe together

is the single market: the guarantee that

people, goods and money can move around

the European Union freely. An interesting

point is that the free movement of goods,

which is obvious for oranges, furniture or

shoes, is not so obvious for digital goods:

for example, if you have a contract for

British satellite TV in the UK, you cannot

watch the Premier League with the same

subscription in Greece. Other issues are

fragmented data protection rules, differ-

ing copyright regimes, lack of access to

broadband and geo-blocking of online

content. The digital economy is growing

very fast and all these virtual borders are

real problems for citizens and businesses.

That's why DSM is needed: it is a set of

actions which will gradually remove the

‘digital borders’ which still exist across

Europe. It is based on three areas: giving

better online access to digital goods and

services, creating a regulatory environ-

ment where digital networks and services

can prosper, and using digital technolo-

gies as a driver for economic growth. A

specific action will be dedicated to leader-

ship in industrial digital technologies, and

this is where you can see the link between

high-level European policy and the daily

work of the HiPEAC community.

In practical terms, over the next few years

the European Commission will push for

leadership in digital technologies for

European industry, and this will be done

by supporting the emergence of digital

industrial platforms. All sectors of the

economy will be affected: from ‘high tech’

areas, like aerospace or energy, to some

markets which are highly visible to con-

sumers, like the automotive sector, and

also sectors which have traditionally been

considered ‘low tech’, such as agriculture

and construction.

Crossing virtual borders with the Digital Single MarketWhat is the Digital Single Market and what does it mean for the computing systems sector in Europe? Sandro D’Elia, HiPEAC project officer in the Complex Systems and Advanced Computing Unit at the European Commission, explains.

“The digital economy is growing fast and

virtual borders are real problems for citizens

and businesses”

“The European Commission will push

for leadership in digital technologies for

European industry”

Policy Corner

Sandro D’Elia discussing digital platforms at HiPEAC16

HiPEACINFO 464

For the HiPEAC community there are two

main consequences.

• One: funding opportunities in the coming

years will be focused on the areas where

industrial applications are possible; this

means, for example, advanced com puting

and cyber-physical systems, manu facturing

applications, numeric simu la tion for

products and production processes,

innovative applications in areas such as

food production or civil engineering.

• Two: the creation of platforms will be the

preferred approach to support industrial

applications (instead of one-shot solu-

tions). And here, it should be clear that a

platform, in this context, is not just a

piece of software with a public API, but a

set of technologies that will become the

foundation for a market, where many

different actors can provide added value

and carry out real business. The aim here

is not to create another consumer ‘app

store’, but a market oriented towards

industry which can strengthen the lead-

ership of European players in areas of

high economic value like transport, criti-

cal applications, automotive, aerospace

and manufacturing machines.

The overall objective is to strengthen

Euro pean industry, creating value and

jobs. HiPEAC is one element of this strat-

egy: you have the know-how to build digi-

tal platforms, you know the technology

and you teach digital technologies to the

scientists and engineers who will enter the

job market in future.

But the task before us is not easy, because

thinking in terms of platforms – and not

only in terms of technical solutions – requires

a different mindset: it requires thinking big,

in economics as well as in technological

terms, considering issues like standards,

certifications, compatibility and of course

market evolution. Although challenging,

this task is essential because there is no

‘plan B’: European industry needs digital

platforms to stay competitive and to cre-

ate decent jobs. Otherwise the next digital

revolution will be driven by somebody

else, and we might not like the results.

Crossing virtual borders with the Digital Single Market

Policy Corner

MORE INFORMATION:

https://ec.europa.eu/priorities/digital-single-market_en

https://ec.europa.eu/digital-agenda/en/news/updated-view-european-commission-digitising-european-industry-initiative

https://ec.europa.eu/digital-agenda/en/digitising-european-industry#Latest

https://ec.europa.eu/digital-agenda/en/digitising-european-industry#Article

A video of Sandro D’Elia discussing digital platforms is available on the HiPEAC YouTube channel: http://bit.ly/HiPEAC16_YouTube

Digitising industry graph

“The aim is not to create another consumer ‘app store’, but a market oriented towards industry which can strengthen the leadership of European players in areas of high economic value”

HiPEACINFO 46 5

With over 650 participants, the 11th edition of

the HiPEAC conference was the most success-

ful yet. This year’s edition, held in Prague from

18-20 January, featured a wealth of sessions:

32 workshops, nine tutorials and 37 papers, all

published in the ACM journal Transactions on

Architecture and Code Optimization (TACO).

Keynote talks by Ruby B Lee (Princeton Uni-

versity), Krisztián Flautner (ARM) and Valen-

tina Salapura (IBM) discussed security-aware

architecture, the Internet of Things and high-

availability cloud.

As HiPEAC coordinator Koen De Bosschere of

Ghent University explained, the conference

programme covered the ‘four challenges of

computing systems’, as set out in the HiPEAC

Vision: performance, low power, complexity

and security. The new instalment of the pro-

ject, HiPEAC4, was also launched, offering new

recruitment, communication and impact anal-

ysis services to the HiPEAC community.

During the conference, HiPEAC project officer

Sandro D’Elia of the Complex Systems and

Advanced Computing Unit at the European Com-

mission, said that HiPEAC was ‘at the core of

the [Commission’s] Digitising Europe strategy’.

This year marked the first time the conference

was held in Prague, described by Martin Palkovic,

local organizer and director of IT4Innovations,

as ‘the perfect place’ to hold the conference:

‘Prague is in the centre of Europe, it’s a city with

cultural heritage and also a hub for science and

technology,’ he said. Jirí Kadlec, ICT programme

committee delegate for the Czech Republic,

concurred, saying: ‘The success of the confer-

ence provides an additional positive argument

for the Czech national funding authorities when

securing resources for national public funding

of top class research.’

The HiPEAC team would like to thank the con-

ference sponsors, without whose generous

support the conference could not have been

such a success.

Photos from the event can be found in the

event photo album (http://bit.ly/HiPEAC16-

photos), while the conference video is

available to view on the HiPEAC YouTube

channel: http://bit.ly/HiPEAC_YouTube.

Check out our interviews with the keynote

speakers from p10 onwards.

In Memoriam Nacho Navarro, 1958-2016◆ Mateo Valero, with the contribution of

many others who cared about Nacho

Nacho was born and raised in Barcelona.

He studied at the Universitat Politècnica

de Catalunya – Barcelona Tech and in 1985

joined the university as a lecturer before

becoming associate professor and later

leading the group on accelerators for HPC

at the Barcelona Supercomputing Center.

Nacho was part of HiPEAC from the begin-

ning and was an extremely active member

of the network, organizing and participat-

ing in many events over the years.

Although he would never acknowledge it

thanks to his humble nature, Nacho was a

truly remarkable person: highly intelligent,

patient and incredibly kind, he always

made time to listen and was ready to help.

His profound humanity was evident in eve-

rything he did, shining a spotlight on

others while putting himself last. He had

friends all over the world about whom he

cared deeply, and he touched a great

number of people’s lives. For the last 35

years, ever since he was a student of mine

at the computer science faculty, he has

been the person closest to me at the uni-

versity. We will miss Nacho enormously.

A memorial website has been created

for Nacho, where you can leave messages

of commemoration and condolence:

http://inmemoriam.bsc.es

Eleventh HiPEAC conference in Prague a resounding success

HiPEAC news

HiPEACINFO 466

One of the aims of HiPEAC4 is to reach beyond the network’s traditional audiences and attract

new members, particularly those from business who stand to benefit from HiPEAC expertise in

high-performance and embedded architecture and compilation. To help amplify the HiPEAC

community, we’ve been taking HiPEAC on the road over the last few months, focusing

particularly on attracting industry representatives and upcoming talent to the network.

The first stop was Embedded World, the major international trade fair for embedded systems,

which this year took place in Nuremberg from 23-25 February. Here, we discussed the benefits

of HiPEAC membership with over 65 companies in the embedded computing sector.

From 15 to 17 March, HiPEAC hosted a booth at the Design, Automation and Test in Europe

(DATE) conference, the largest computing systems conference in Europe, with a highly regarded

academic programme of talks. In addi tion to information about the network and HiPEAC gifts,

the booth featured presentations, videos and flyers from projects related to HiPEAC, including

FiPS, ADEPT, Eyes of Things, VINEYARD, CLERECO, TULIPP and RETHINK big. It attracted a number

of visitors, among them PhD students interested in finding out how HiPEAC could help them.

Other projects coordinated by HiPEAC members also hosted booths at the event, including

TETRACOM, PROXIMA, SAFURE, MANGO, EuroLab4HPC and ExaNode.

HiPEAC Jobs – #1 for HPC and embedded systems opportunities in Europe◆Maureen Simpson,

HiPEAC Recruitment Officer

Endlessly scrolling through jobs listings

when you’re seeking employment can be a

tedious and time-consuming task, espe-

cially when 95% of what’s on offer isn’t

right for you. Thankfully there is an answer

– it’s HiPEAC Jobs. On HiPEAC Jobs you’ll

find the best range of relevant job oppor-

tunities; whether you’re looking to take

that first step on the career ladder, or are

looking to progress your career further in

Europe, we have the jobs to suit.

For HiPEAC members looking to recruit,

HiPEAC Jobs provides an easy and highly

effective way to reach high-quality can-

didates who are actively looking for oppor-

tunities in high-performance computing

(HPC) and embedded systems in Europe.

HiPEAC Jobs offers opportunities to raise

your employer brand and promote your

jobs for free to a specialist audience. Our

Jobs Board attracts top level talent, day in

and day out.

www.hipeac.net/jobs

Follow @hipeacjobs for the latest vacancies

HiPEAC goes on the road

A number of visitors, including PhD students,

came to find out more about HiPEAC at DATE.

Copyright: DATE/EDAA

Domenik Helms, OFFIS, sets out the FiPS

project’s approach to energy-efficient

super computing. Photo credit: Nils

Koppaetzky

HiPEAC news

HiPEACINFO 46 7

Architecture experts gather in Barcelona to ride on Moore’s LawOn 17 and 18 March, leading researchers in computer architecture

converged in Barcelona to participate in the Riding on Moore Law’s

(RoMoL) 2016 Workshop. The event brought together internation-

ally recognized researchers in this field, including five winners of

the prestigious Eckert Mauchly award (popularly known as the

Nobel for computer architecture). Conference sessions centred on

topics such as computer architecture, runtime systems and pro-

gramming models, generating discussions on how to achieve

strengthened co-operation and improved interoperability and co-

design opportunities between the runtime system and the underly-

ing hardware.

After the workshop, a memorial event was held in tribute to Nacho

Navarro. At this event, colleagues and friends shared experiences

and anecdotes from their years with Nacho.

Photos from the event can be viewed on the Barcelona Supercom-

puting Center (BSC) Facebook page: http://bit.ly/RoMoL_photos

Presentations and the full programme can be viewed on the RoMoL

2016 website: http://romol2016.bsc.es

MILS Community◆Holger Blasum, SYSGO

You may have heard of MILS during the HiPEAC conferences in 2015

(Amsterdam), and 2016 (Prague), where workshops were organized.

MILS (Multiple Independent Levels of Security) is a template for split-

ting up complex systems into components with controlled resource

access and information flow using virtualization by a separation kernel

which manages applications by dividing them into partitions. Depend-

ing on configuration, this kind of division can be made robust enough

to ensure that if a partition is captured (by a virus or a targeted attack,

for example), the whole system is not compromised.

In addition to the second workshop, in Prague we had a community

get-together, where we discussed topics ranging from Common Criteria

certification, hardware (testing versus compliance), how to agree on

common definitions, a possible catalogue of known (published) MILS

systems and how to complement other standardization efforts. As a

next step, we agreed to refine a mind-map-style roadmap; currently this

has three main branches: development, computer-aided assurance and

assurance by certification.

The MILS Community is an informal interest group for architecture-

based security for the exchange of ideas about potential directions for

meaningful work, in an industrial or research context. Currently, the

main means of communication is a public mailing list (http://lists.

euromils.eu/mailman/listinfo/mils). Later, we intend to have regular

physical or online meetings as well. For now, please feel free to sub-

scribe to the mailing list, regardless of whether you specialize in soft-

ware or hardware.

‘MILS allows you to build up complex systems consisting of COTS [com-

mercial off-the-shelf components] you can buy easily on the market

which provide assurance that the system is functioning as intended.

Because in general security is not composable, you have to really go

deep into every single component, but thanks to MILS you can buy

these certified components and from them you can build a certified,

safe and secure system.’ Sergey Tverdyshev, SYSGO

A video of SYSGO’s Sergey Tverdyshev discussing MILS is available on

the HiPEAC YouTube channel: http://bit.ly/HiPEAC_YouTube

“MILS is a template for splitting up complex systems into components with controlled resource access and information flow”

HiPEAC news

HiPEACINFO 468

HiPEAC Distinguished Service Award 2015

During the HiPEAC conference social

event in Prague on 19 February, HiPEAC

member Kevin Hammond of the University

of St Andrews was awarded a Distin-

guished Service Award for his active par-

ticipation in the project. Since 2008, Kevin

has organized four thematic sessions,

three workshops, one tutorial and two pro-

ject meetings. Congratulations on this

well-deserved award!

Publication: System-Level Design Methodologies for Telecommunication◆by Nicolas Sklavos, Michael Hübner, Diana Goehringer and Paris Kitsos

Written by HiPEAC members, this book

provides a comprehensive overview of

modern network design, from specifica-

tion and modelling to implementation and

test procedures, including the design and

implementation of modern networks on

chip, in both wireless and mobile applica-

tions. Topics covered include algorithms

and metho dologies, telecommunications

hardware (including networks on chip),

security and privacy, wireless and mobile

networks and a variety of modern applications, such as Voice over

Long-Term Evolution (VoLTE), the voice service aspect of wireless com-

munication, and the Internet of Things.

This publication:

· Provides a comprehensive summary of modern network design, from

specification to implementation.

· Offers a detailed explanation of different network technologies for

telecommunications, including wireless and mobile protocols.

· Discusses issues of security and privacy as they relate to wireless

and mobile networks.

· Covers architectures, design, implementation platforms and

optimizations for network on chip.

For further information, and to order your copy, visit the Springer

website: www.springer.com/gp/book/9783319006628

Dates for your diary Spring School on Polyhedral Code Optimizations and Numerical Simulation9-13 May 2016, St Germain au Mont d’Or, near Lyon, France

http://mathsinfohpc.sciencesconf.org

European HPC Summit week9-12 May 2016, Prague, Czech Republic

https://exdci.eu/events/european-hpc-summit-week

23rd Reconfigurable Architectures Workshop23-24 May 2016, Chicago, IL, USA

http://raw.necst.it

2016 IEEE International Symposium on Circuits and Systems (ISCAS)22-25 May 2016, Montreal, Canada

http://iscas2016.org

ISC High Performance 201619-23 June 2016, Frankfurt, Germany

www.isc-hpc.com

12th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES)10-16 July 2016, Fiuggi, Italy

http://acaces.hipeac.net/2016

International Conference on Embedded Systems Architectures, Modeling and Simulation (SAMOS XVI)18-21 July 2016, Samos Island, Greece

http://samos-conference.com

26th Conference on Field-Programmable Logic and Applications (FPL 2016)29 August-2 September 2016, Lausanne, Switzerland

http://fpl2016.org

IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16)21-23 September 2016, Lyon, France

http://mcsoc-forum.org

Embedded Systems Week 2-7 October 2016, Pittsburgh, PA, USA

www.esweek.org

23rd IEEE International Conference on High Perfor-mance Computing, Data, and Analytics (HiPC 2016)19-22 December 2016, Hyderabad, India

www.hipc.org

HiPEAC news

HiPEACINFO 46 9

data (SIMD)-style of data parallelism (subword-parallelism)

within instructions.

At Princeton, highlights include designing security-aware proces-

sor architectures which provide hardware-enforced isolation

(enclaves) within the existing software ecosystem; designing

novel secure caches that use a 'moving target defense' in hard-

ware to prevent information leakage through cache side-channel

attacks; and designing self-protecting data, secure cloud servers

and CloudMonatt architecture for monitoring the security health

of cloud servers. I also write patents with many of my PhD stu-

dents, and am happy that all the patents have issued so far.

It’s important to take security into account at the architec-

ture level because we can ensure that security-aware features

are implemented into all processors and computing devices,

rather than added as optional after-thoughts. Hardware features

can provide fundamental security features that are, in general,

harder to attack than software - which has been shown to be very

vulnerable. Also, designing security into the computer architec-

ture from the get-go can give us a better chance to achieve secu-

rity without sacrificing performance or power.

Ruby B Lee is the Forrest G. Hamrick Professor in the Electrical

Engineering department at Princeton University. Prior to

Princeton, she served as chief architect at Hewlett-Packard.

Lee is an ACM and an IEEE Fellow, has a PhD from Stanford,

and holds over 120 U.S. and international patents. Known as

a hardware security expert, she has served on various U.S.

committees for improving cyber-security research.

I studied computer architecture because I was fascinated by

what computers could do. When I first took a class in computer

architecture, I was intrigued by how one could identify fundamen-

tal operations and define instruction set architectures (ISAs) and

processor implementations that can perform general-purpose

computing with high performance across so many different appli-

cation domains. Later, I was fascinated by the ability to improve

cyber security, upon which we all depend, by defining fundamen-

tal security features into the computer architecture itself.

My past work includes designing PA-RISC for HP, which

included advanced security and protection features even back

then, and hence was advanced for its time. Also designing mul-

timedia instructions which brought single instruction, multiple

Interviews: HiPEAC16 keynote speakers discuss security, the IoT and cloud computing

The 2016 HiPEAC conference featured keynote talks from leading experts in their field. We were lucky enough to speak to Ruby B Lee, Krisztián Flautner and Valentina Salapura about these three crucial

technology areas for computing architecture.

Ruby B Lee

“Cyberspace is like the wild, wild west in terms of security!”

HiPEAC voices

HiPEACINFO 4610

challenge around integrating robust security in micro controllers

costing less than $1.

Currently there is a lot of technology-related opportunity in

the IoT field. There need to be robust, low-cost and secure

devices in the field. Despite the smallness of these devices, they

need to run sophisticated software to unlock the potential of IoT.

This means that the traditional embedded industries need to

look sideways at other sectors and transplant best practices

around code reuse, open source development, etc. to create solu-

tions faster. Ultimately the big opportunity in IoT is around new

business models that change when and how companies and con-

sumers pay for services.

My favourite potential applications in the IoT are the ‘boring’

ones where technology isn’t front and centre, but is a key enabler

in the background to make it easier to deliver a product or a ser-

vice. Some examples:

• Optimizing the fish or tea farming process automatically. This

falls under the precision farming umbrella and has the potential

to transform the entire farming industry.

• Industrial use cases like concrete curing temperature monitor-

ing enabled by sensors deployed in the concrete itself. This

ensures that the structural integrity of a building can be

increased and monitored over time.

• Real-time tracking with wearables to optimize time to treat-

ment for patients undergoing cardiac trauma.

An interview with Kris Flautner can be viewed on the HiPEAC

YouTube channel: http://bit.ly/HiPEAC_YouTube

Krisztián Flautner is the general manager of ARM’s Internet of

Things (IoT) Business Unit; previously, he was vice-president

of research and development at ARM. He received a PhD in

computer science and engineering, along with a number of

other degrees, from the University of Michigan.

I was interested in computers from an early age and spent a

lot of time on my Commodore 64. Computer architecture was

attractive to me partly because of a number of interesting people

in the field and because its principles seemed to be broadly appli-

cable to other areas as well. Last but not least the computer

architect’s toolbox is straightforward: learn about prediction,

pipelining, caching and indirection and one can feel like an

instant expert.

Highlights of my career to date include running the research

department at ARM, which has been very rewarding – I appreci-

ated the opportunity the company gave me to try and experiment

with ambitious new ideas.

Facilitating the transfer of technology from research centres

to industry is difficult; this is where great research ideas ulti-

mately fail. There are so many variables – such as timing, trust,

ownership – that have to be right for a transfer to succeed. The

best route in my experience is if the product side is involved rela-

tively early in the technology development process so that there

is a shared sense of ownership and trust in the technology itself.

Over the next few years, IoT ecosystems around security,

interoperability and trust will be emerging. There is a major

Krisztián Flautner

“Traditional embedded industries need to look sideways”

HiPEAC voices

user interfaces, rather than just graphical user interfaces com-

mon in PCs at the time.

Technology trends which will have a major influence on my

work include machine learning, proliferation of sensors, wear-

able devices and smartphones with cloud computing.

Security pitfalls which keep me up at night? Cyberspace is like

the wild, wild west in terms of security!

Impacts which my work on multimedia architecture has

delivered include ubiquitous multimedia in low-cost com-

modity products – even with just software (with subword-paral-

lel (SIMD) instructions). It facilitated the possibility of multimedia

HiPEACINFO 46 11

applications are very different; they handle mission critical trans-

actions, and are optimized for security and integrity. For enter-

prise-level applications, areas such as security, stability, scalability,

availability, disaster recovery and so forth require much larger

investments.

Data centre design and operation is experiencing tectonic shifts.

The so-called ‘lights out data centres’ are delivering the automa-

tion that we first predicted with the autonomic computing mani-

festo from IBM. They have very limited human on-site access,

saving energy and reducing human errors. This trend will con-

tinue towards building fully automated self-monitoring, self-

diagnosing and self-healing systems based on analytics, cognitive

computing and machine learning. Increasingly, we are also look-

ing at giving solutions architects more flexibility in combining

system components on a per-application basis, so that the ratio of

computing power, memory, external storage and I/O can be

reconfigured based on application needs.

Three technology trends to watch are all linked to how IT

resources are consumed:

• Mobile computing with its reliance on data centres as the com-

putational ‘brain’, and the Internet of Things are driving a resur-

gence of client/server computing models, but this ‘server’

now is an entire data centre providing services on behalf of

applications.

• Cognitive computing is already huge. When Watson won the

Jeopardy! show, it was the starting shot for a renewed focus on

artificial intelligence. Since then, Siri and OK Google have revo-

lutionized how people consume computing. We are in the pro-

cess of defining system architectures and data centres that can

be optimized for big data, analytics, machine learning and deep

learning.

• With huge amounts of data in the cloud, a focus on cyber secu-

rity and data privacy which has to protect data from cyber-

attacks and hacking will be critical both for consumer and

enterprise customers.

Valentina Salapura is an IBM Master Inventor and System

Architect at the IBM T.J. Watson Research Center. Before join-

ing IBM, Dr Salapura was a faculty member with Technische

Universität Wien, where she also received her PhD degree. She

holds over 120 patents, is an ACM Distinguished Speaker,

Fellow of the IEEE and recipient of the 2006 ACM Gordon Bell

Prize for Special Achievements for the Blue Gene/L supercom-

puter and quantum chromodynamics.

My father was a physicist, so I was surrounded by science from

a young age. I was always interested in how science can improve

people’s lives. Building computer systems always fascinated me,

and I followed the IT trends providing the most powerful

computing.

I worked on several generations of IBM’s BlueGene super-

computers, the systems which held the title of being the fastest

and most power efficient supercomputers for a number of years.

I worked on the architecture of IBM’s Power systems to provide

multiprocessor systems for big data and business analytics.

My favourite application of BlueGene is quantum chromody-

namics (QCD), the theory that models nuclear forces during the

creation of the universe. I was intrigued by the Big Bang as a

child, so this application brings back the fascination that ques-

tions of the origin of the universe hold for a young person.

Another fascinating application I have to mention is drug discov-

ery: understanding the causes of diseases and discovering new

drugs to alleviate human suffering.

Cloud computing is democratizing supercomputers: anybody

can acquire tremendous computing power quickly for a specific

time period, and only be billed for that usage, without requiring

huge upfront capital investment. It offers fertile ground for a new

breed of applications for distributed computing which are opti-

mized around scalability, elasticity and sharing. Business

Valentina Salapura

“Cloud computing is democratizing supercomputers”

HiPEAC voices

HiPEACINFO 4612

OPTIMIZING 3D STACKED INTEGRATED CIRCUIT TEST FLOWS WITH 3D-COSTAR

Said Hamdioui, Delft University of Technology

Selecting an effective test strategy

for a 3D stacked integrated circuit

(3D-SIC) is crucial for overall cost

optimization. In addition, diverse

products and applications require

different quality levels, resulting in

different test flows; these flows may

require different design-for-test (DfT) features, which need to be

incorporated in the various dies early on in the design process.

An appropriate cost model to optimize test flows with their asso-

ciated DfT, while taking into account yields and die production

costs, is therefore of great importance.

Delft University of Technology and IMEC have developed a theo-

retical foundation for 3D-SIC cost modelling, compiled into a

tool called 3D-COSTAR. First announced in 2013 (http://bit.ly/

press_release-3dcostar), the tool was later made available for

public use on the Delft University website: http://bit.ly/3Dcostar.

Production flow from start to finish3D-COSTAR is the first tool to address test flow and test cost opti-

mization for 3D-SICs. The uniqueness of the tool is due to the fact

that its inputs parameters cover the entire 2.5D-/3D-SIC produc-

tion flow (design, manufacturing, test, packaging and logistics),

and that it is aware of the stack build-up (2.5D versus 3D, multi-

ple towers; face-to-face or face-to-back) and stacking process

(die-to-die, die-to-wafer or wafer-to-wafer). The tool produces

three key analysis parameters: 1) product quality, expressed as

defect level (test escape rate) in DPPM (defective parts per mil-

lion); 2) overall stack cost; and 3) breakdown per cost type.

3D-COSTAR allows precise, efficient trade-offs to be made at

an early design stage. For instance, optimizing the test flows

based on yield and cost parameters of an individual product is a


The brains driving new business forward

What do a cost model for integrated circuits, low-power network-on-chip technology and

wearable body sensors have in common? They were all recipients of a HiPEAC Technology Transfer Award

in 2015. Here, winners explain how they took their innovation out of the lab and into the marketplace.

13HiPEACINFO 46

complex optimization problem and strongly application depen-

dent. Different test flows, executed after manufacturing, may

require different design-for-test features, which need to be incor-

porated in the various dies during their early design stages.

The industrial importance of 3D-COSTAR is demonstrated by

analysing trade-offs of different complex optimization test prob-

lems in terms of test, quality and cost. For example, the impact of

pre-bond testing of active dies using either dedicated probe-pads

or directly probing on large-array fine-pitch micro-bumps has

been demonstrated in collaboration with IMEC and Cascade

Microtech. These impressive results were presented at the IEEE

International Test Conference in September 2014 in Seattle,

USA. This work was also nominated by Semiconductor Equipment

and Materials International (SEMI), a global industry associa-

tion, as one of the four most influential Automatic Test Equipment

(ATE) papers of the year in 2014.

Taking 3D-COSTAR to industryIMEC has been using the tool in collaboration with some of lead-

ing companies in 3D-SIC in order to explore and analyse complex

trade-offs in 3D test flows, in terms of both cost and DPPM. For

example, together with IMEC, Cascade Microtech has recently

demonstrated the feasibility of direct probing large-array fine-

pitch micro-bumps to avoid the usage of dedicated pre-bond

pads. Analysis with 3D-COSTAR clearly showed up to 50% over-

all cost benefit of doing micro-bump probing using an advanced

probe cell such as was demonstrated with Pyramid Probe® RBI

technology on Cascade Microtech’s CM300 probe station.

The target market for 3D-COSTAR is all companies involved in

3D- and 2.5D-stacked ICs – that includes just about every semi-

conductor company. We are reaching out to them via papers and

presentations at international conferences and trade-shows, via

IMEC’s strong network of industrial partners, and by making a

version of the tool publicly available via a website of TU Delft.

In my view, to transfer research results you need a deep under-

standing of the real needs of industry and collaborate with indus-

try partners from the very start of the development process. This

allows the solution to be refined so that it meets industry needs.

Technology transfer specialIm

age

copy

righ

t: IM

EC

NETWORK-ON-CHIP FOR THINK SILICON’S ULTRA-LOW-POWER GPU

Giorgios Dimitrakopoulos, Democritus University of Thrace (DUTH)

Based near Patras in Greece, Think

Silicon S.A. develops high-perfor-

mance, ultra-low power graphics

intellectual property (IP) for embed-

ded and mobile applications. The

company currently focuses on devices

for the wearables and Internet of Things (IoT) market, where the

main challenge is extending battery life.

Think Silicon required a power-efficient, scalable Network on

Chip (NoC) technology that would integrate its multicore NEMA

2D and 3D Graphics Processing Units (GPUs) and display proces-

sors. The company was interested in a scalable interconnect solu-

tion that would allow them to seamlessly customize their

available multicore configuration in accordance with customer

requirements, without paying for additional redesigns on a cus-

tomer-by-customer basis. This has a direct positive impact to

time to market, a key factor in decision making particularly for

SMEs targeting the highly evolving IoT market.

Technical advantages over the competitionThe NoC we created, TSNoC, allows NEMA 3D GPU IP to be

automatically integrated to a host System-on-Chip using config-

urable AMBA AXI-based interfaces. TSNoC was tailored to the

increased performance requirements of GPU-specific memory

traffic patterns without exceeding the ultra-low power budget or

the tight space constraints of wearable or IoT devices. To tackle

both challenges, TSNoC is optimized for the traffic and memory

patterns of the NEMA GPU, and leverages the cores’ multi-

threading capabilities to offer fast data delivery.

A proprietary arbitration policy and load-balancing flow-control

protocol allow fair access to the memory controller across all

threads, while any inter-core traffic can be efficiently isolated by

the core-to-memory traffic. TSNoC can support an arbitrary

number of memory ports to handle GPU memory traffic regard-

less of address mapping across ports and across threads. In this

way, software development and thread scheduling inside the

cores is simplified, thus minimizing hardware complexity and

power consumption.

TSNoC is also associated with a rich verification framework, con-

sisting of constrained random transaction generators acting as

AXI Master and Slaves and proper transaction delivery verifica-

HiPEACINFO 4614

WIRELESS, WEARABLE AND USER-FRIENDLY ECG SENSORS

Roman Trobec and Aleksandra Rashkovska, Jožef Stefan Institute, Ljubljana

Our innovation is a miniature device

with an electrocardiogram (ECG)

sensor. This wearable multifunc-

tional body sensor measures differ-

ential surface potential (ECG)

between two proximal electrodes. The moderate resolution ECG

is suitable for long-term personal cardiac activity monitoring, as

well as for clinical use. Besides ECG, other features can be

extracted from the potential measured, such as muscle activity

and respiration. The sensor can also detect information about the

measurement conditions such as movement and temperature,

thus providing information that allows for ambient intelligence.

High quality ECG was first measured by Willem Einthoven at the

beginning of the 20th century with his invention of the string

galvanometer. Today, a range of ECG devices are used in medi-

cine, from the standard 12-lead ECG, where wires are connected

to electrodes placed on 10 locations of the body, to multichannel

ECG body surface mapping systems, to the Holter monitor, where

a lower number of electrodes are connected with wires to a small

portable recorder that obtains a continuous ECG measurement

over several days, and finally to the (wireless) implantable loop

recorder which measures ECG for a period of several years.

Our solution was inspired by the multichannel ECG with 64 elec-

trodes on the surface of the body. We recognized that a significant

amount of information about heart activity could be measured just

through the electric potential between two neighbouring multi-

channel electrodes. Such an approach enables non-invasive meas-

urement with a single channel of bipolar ECG without wires.

tion checkers. Assertion properties and checking are also included

in a distributed manner across the entire design.

Commercializing research results For the last five years, the VLSI lab at Democritus University of

Thrace has focused on the design of NoC architectures. During

this time we had already developed a complete SystemVerilog-

based NoC architecture including highly-parametrizable register

transfer language (RTL) models of NoC components, such as net-

work routers and AMBA AXI4.0-compatible network interfaces.

After reviewing this area, Think Silicon opted to license the NoC

technology developed by the VLSI Lab. The NoC architecture was

then customized to meet the company’s requirements as part of a

one-year development project set out in a contract.

Think Silicon’s portfolio includes GPUs, display processors, graph-

ics accelerators and GPGPU accelerators focusing on ultra-low

power consumption and thus on extension of the battery life. The

licensed NoC technology is embedded inside the graphics IP com-

mercialized by Think Silicon rather than being presented as a

standalone product.

In future, the NoC architecture could be delivered as standalone

IP to systems-on-chip in other areas such as the automotive sector,

data centres, networking or mobile computing. However, achiev-

ing this goal would require a significant amount of effort which

could only be achieved by a dedicated spin-off company.

Business opportunities for European semiconductor researchers In the area of integrated-circuit design and computer architecture,

one of the major problems facing industry is complexity and the

verification of functionality and product quality (performance

and power). Any new feature added or architecture developed

should be adequately verified both in isolation as well as a part of

an already complex system. Hence solutions that can automate

verification or the design of verification-friendly protocols and

architectures would have a clear impact on future products. In my

opinion, this is especially important for SMEs specializing in inno-

vative solutions which lack the resources to carry out proper veri-

fication of their new ideas and whose technology may not be

adopted as quickly as it could be.

Technology transfer special

An early commercial ECG machine

HiPEACINFO 46 15

Additionally, a low-power radio and processor can be placed on

such devices for continuous wireless transmission of data to a

nearby personal digital assistant (PDA), such as a smartphone or

tablet. Using a PDA offers the possibility of WiFi internet access to

a safe storage server for further storage and processing.

Our solution is situated between the Holter monitor and the

implantable loop recorder with the possibility of immediate access

to the measured data. It is therefore most appropriate when heart

rhythm and ECG need to be monitored in an unobtrusive, non-

invasive way for a period of several hours to several days. If the

battery is charged periodically and the electrodes are replaced, the

monitoring period could be prolonged to weeks or even months.

Mainstreaming mHealth: a market opportunityThe project arose in response to the lack of widely accepted

mobile health (mHealth) solutions, despite the world of ubiqui-

tous mHealth-enabling ICT devices. The key weakness of the

approaches implemented so far is that they focus mainly on the

technology, while the importance of its acceptance by users and

health care practitioners is largely neglected.

Our ambition is to bring an mHealth solution into the mainstream

of modern healthcare – a solution which will be supported by

medical experts and users as well as being CE certified. Expected

outcomes include:

• An ergonomically co-designed, widely accepted wireless body

sensor.

• A formal model of holistic health management: clinical models,

domain and data-driven platforms, users’ communication inter-

faces, and personal records with users’ medical history.

• Fully operating pilot systems with more than 100 volunteer test

users.

The ultimate goal is to deliver a medically certified device ready

for mass production and further industrialization.

Wide range of potential usage scenariosIt has been shown that the ECG measurements from the sensor

are suitable for medical use, in particular for detection of arrhyth-

mias where the ECG timing is important. This has been con-

firmed by several clinical evaluations. Using ambient data, it is

possible to determine the conditions in which the measurements

were taken. Hence the sensor can provide solutions for continu-

ous monitoring of heart activity in hospitals, health centres, nurs-

ing homes, older people’s housing, health resorts and similar.

The exceptionally lightweight, unobtrusive design of the sensor

allows it to be used while engaging in sporting activities or dur-

ing intense physical work.

Use of the sensor is not limited by the user’s age, sex, weight, height

or other personal characteristics, or by current health status.

From lab to marketThe work needed to progress an innovation from a laboratory

prototype to the market is often underestimated. First, it’s essen-

tial to have a competent investor who can invest in knowledge,

certification, production and marketing. In our case, the investor

established a spin-off company because doing so allowed owner-

ship of an independent business entity, tax flexibility and career

opportunities for enthusiastic engineers and medical doctors.

However, this requires certification for quality management sys-

tems, which is quite a complex task.

To ensure success, an experienced and devoted team is a must; we

are lucky enough to benefit from a great team for this project.

RESEARCH AND DEVELOPMENT

Roman Trobec, Viktor Avbelj, Uros Stanic, Matjaz Depolli, Aleksandra

Rashkovska, Ivan Tomasic, Tomaz Kristofelc, Klemen Bregar, Gregor Kosec.

INVESTMENT, PRODUCTION AND MARKETING

Boris Simoncic, Jurij Tasic, Marino Samardzija, Bostjan Barbis.

External adviser for CE certification: Uros Tacar.

FOR FURTHER INFORMATION

email [email protected]

Have you successfully transferred research results to industry? Send

your submission to the HiPEAC Technology Transfer Awards. Further

information: www.hipeac.net/research/technology-transfer-awards

Technology transfer special

The compact wireless ECG sensor can transmit data to PDAs such as smartphones

HiPEACINFO 4616

LOW-POWER, SAFE AND SECURE MIXED-CRITICALITY SYSTEMS: THE SAFEPOWER PROJECT

How can we ensure that the

applications ensuring our

trains, planes and automobiles arrive safely and on time use less

power and are sustainable for the future? SAFEPOWER, which

kicked off on 25-27 January at the Spanish Office for Science and

Technology in Belgium, is producing a reference architecture and

platform, complemented by analysis, simulation and verification

tools, to deliver power savings of up to 50% for mixed-criticality

systems. Such systems comprise elements both with and without

safety-critical requirements.

Critical real-time embedded systems, such as those used in the

railway, aerospace, automotive and energy sectors, face disrup-

tion thanks to the emergence of mixed-criticality systems based

on multicore processors. Using less power is increasingly impor-

tant for these systems: it provides a competitive advantage for

systems operating with limited energy supplies, such as battery-

powered systems, allows higher availability and represents a step

towards near-zero emissions in systems comprising many devices.

An added complication with mixed-critical systems is that power

has to be shared among different applications and must be strictly

controlled to prevent unwanted interferences.

The approach and technologies developed, which will take into

account safety and real-time constraints, are to be evaluated by an

industrial advisory board consisting of major organizations in the

field: the European Space Agency, GMV, Xilinx and Technischer

Überwachungs-Verein. Industrial use cases in the railway and aer-

ospace domains, as well as a cross-sector public demonstrator, will

demonstrate the benefits of SAFEPOWER’s innovations.

NAME: SAFEPOWER – Safe and secure mixed-criticality systems with

low power requirements

START/END DATE: 01/01/2016-31/12/2018

KEY THEMES: mixed-criticality systems, low power, safety, security

PARTNERS: Spain: IK4-IKERLAN, CAF Signalling, FentISS; Germany:

Universität Siegen, Oldenburger Institut für Informatik (Offis); Sweden:

Saab, Kungliga Tekniska Högskolan; UK: Imperas

BUDGET: € 4m

WEBSITE: http://safepower-project.eu

SAFEPOWER, UniServer, MANGO and SciChallenge has received funding

from the EU Horizon2020 programme under grant agreement no.687902

UNISERVER TO DEVELOP PLATFORM FOR NEXT-GENERATION CLOUD AND EDGE COMPUTING

Top-tier European research univer-

sities (Queen’s University Belfast,

University of Cyprus, University of

Athens and University of Thessaly

– all represented by HiPEAC mem-

bers) have joined forces with leading low-power processor, server

system and software vendors as well as ambitious SMEs in the

new Horizon2020 project UniServer, which started on 1 February

2016. By following a vertical, full-system research approach, the

project aims to develop a universal energy-efficient system archi-

tecture and software ecosystem for servers targeting both cloud

data centres and edge computing markets.

Innovation Europe


On the technology front, new Horizon2020 projects are researching low-power mixed-critical systems, edge computing and architectures

for future HPC system. Meanwhile, a new project aims to attract more young people into the areas of science, technology and maths.

HiPEACINFO 46 17

Innovation Europe

‘UniServer aspires to deliver, by 2019, a unique, fully working

prototype able to exploit the intrinsic system heterogeneity with

lightweight software mechanisms to improve the energy effi-

ciency and performance of micro-servers,’ explains project coor-

dinator Georgios Karakonstantis.

The software mechanisms will be embedded in the system archi-

tecture with the purpose of exposing the voltage/frequency mar-

gins currently adopted in commercial processor and memory

chips towards the system software. In turn, this information will

be exploited to implement new margin- and fault-aware runtime

and resource management policies, both at the level of the hyper-

visor and higher-level cloud management software such as

OpenStack.

The UniServer project technology will be ported to the world’s

first 64-bit ARM based server-on-chip family built by AppliedMicro

in its X-Gene platforms. ‘The platform will support classic cloud

applications, such as financial trade management and analysis,

while enabling the development of new applications at the edge

of the cloud such as smart traffic control and in-home directed

advertisement,’ adds Karakonstantis.

According to the project’s communication directors, Dimitrios

Nikolopoulos and Dimitrios Gizopoulos, ‘UniServer is an agenda-

setting project for micro-servers aspiring to turn the opportuni-

ties in the emerging Big Data and Internet of Things markets into

real, smarter products that can improve everyday life, while lead-

ing to substantial financial and employment growth.’

NAME: UniServer – Universal Micro-Server EcoSystem by Exceeding

the Energy and Performance Scaling Boundaries

START/END DATE: 01/02/2016-31/01/2019

KEY THEMES: cloud and edge/fog computing, microservers, data

centres, low power

COORDINATOR: Dr Georgios Karakonstantis, The Queen’s University

Belfast

TECHNICAL MANAGEMENT AND COMMUNICATION DIRECTORS:

Professor Dimitrios Nikolopoulos, The Queen’s University Belfast,

Professor Dimitris Gizopoulos, University of Athens

PARTNERS: UK: Queen’s University Belfast; Cyprus: University of

Cyprus, Meritorius Audit Ltd; Greece: University of Athens, University

of Thessaly; US: Applied Micro Circuits Corporation; UK: ARM Holdings;

Ireland: IBM Ireland Ltd; Spain: Worldsensing, Sparsity

BUDGET: €4.8M

WEBSITE: www.uniserver2020.eu/

UniServer has received funding from the EU Horizon2020 programme

under grant agreement no.688540

MANGO EXPLORES RESOURCE-EFFICIENT, RESPONSIVE ARCHITECTURES FIT FOR FUTURE HPC SYSTEMS

The performance/power efficiency

wall is the major challenge faced

by high-performance computing

(HPC) today. According to the MANGO project, which began on

1 October 2015, the root of this problem is the gap between

application demand and the underlying computing architecture:

the closer the computing system matches the structure of the

application, the more efficiently the available computing power

is exploited. To remedy this, the project will set out inherent

architecture-level support for application-based customization.

MANGO aims to achieve resource efficiency in future HPC sys-

tems by exploring new architectures which will also respond to

the non-functional requirements of applications. A growing num-

ber of HPC applications demand some form of time predictabil-

ity, or more generally quality of service, particularly in those

scenarios where correct operation depends on both performance

and timing requirements. Examples of such time-critical applica-

tions include online video transcoding – the server-side conver-

sion of video contents involves computation-intensive operations

on huge amounts of data within near real-time deadlines – and

medical imaging, characterized by both stringent low-latency

requirements and massive computational demand.

Time predictability and quality of service are a relatively unex-

plored area in HPC. While traditional HPC systems are based on

the principle of ‘the faster, the better’, real-time is a feature typi-

cally found in systems used for mission-critical applications,

where timing constraints usually prevail over performance

requirements. In such scenarios, the most straightforward way of

ensuring isolation and time-predictability is through resource

HiPEACINFO 4618

Innovation Europe

overprovisioning, which obviously does not fit with power/per-

formance optimization.

MANGO aims to address this by investigating the architectural

implications of the emerging requirements of HPC applications

and defining high-performance, power-efficient, deeply hetero-

geneous architectures with native mechanisms for isolation and

quality-of-service. It suggests virtual architectures as a means of

partitioning a set of heterogeneous nodes and assigning them to

different applications running concurrently. To achieve this,

MANGO will explore new many-core architectures specifically

targeted at HPC and investigate deeply interrelated mechanisms

at various architectural levels.

Name: MANGO – Exploring Manycore Architectures for Next-

GeneratiOn HPC systems

START/END DATE: 01/10/2015-30/09/2018

KEY THEMES: heterogeneous many-core architectures, HPC, applica-

tions, energy efficiency

PARTNERS: Italy: CeRICT/University of Naples Federico II, Politecnico

di Milano; Croatia: University of Zagreb; France: École polytechnique

fédérale de Lausanne, Thales, Eaton Industries SAS; Spain: Universitat

Politècnica de València; Germany: Pro Design Electronic GmbH;

Netherlands: Philips Medical Systems BV

BUDGET: € 5.8M

WEBSITE: www.mango-project.eu

MANGO has received funding from the EU Horizon2020 programme

under grant agreement no. 671668.

INTERNATIONAL PROJECT TO ATTRACT MORE YOUNG PEOPLE TO SCIENCE AND RESEARCH

Who will be the next Albert Einstein, Marie Curie or Alan Turing?

Using digital technologies and social media, the SciChallenge

project will create a competition to engage more young people in

Europe in the areas of natural science, technology and

mathematics.

Education is the key to successfully shaping the society of tomor-

row, particularly within the areas of science, technology, engi-

neering and mathematics (STEM). However, statistics show that

enrolments in STEM-based degree programmes are decreasing.

This may lead to problems not only for the industrial sector but

also for research and development in a much wider perspective.

SciChallenge is an EU-funded project that aims to break this

trend and get young people interested in education, research and

careers in natural science and technology. The target group is

young people aged 10-20 and the three project keywords are

‘inspire’, ‘contribute’ and ‘share’. An innovative concept for youth

scientific challenges will be created, an online meeting place will

be set up and social media will be used to inspire participants

and share knowledge.

‘SciChallenge will use competitions to get young people to self-

produce digital scientific education materials to be used by their

peers. The idea is that participants, whether individually or in

groups, develop creative digital material such as videos, slides or

infographics and share these online,’ says Sabri Pllana, the

Sweden-based representative for SciChallenge.

Submissions are to be uploaded using social media and collected

on the web platform; winning projects will subsequently be

selected in a number of different categories. The website will also

offer information about education, research and careers, as well

as STEM internship opportunities and taster days.

Contact Sabri Pllana, associate professor in the department of

computer science at Linnaeus University, for further information.

Email: [email protected]

NAME: SciChallenge – Next Generation Science Challenges Using

Digital and Social Media to Make Science Education and Careers

Attractive for Young People

START/END DATE: 01/09/2015-31/08/2017

KEY THEMES: education, research, careers, young people, STEM

PARTNERS: Austria: SYNYO GmbH, Kinderbüro and EUCU NET; Czech

Republic: University of Chemistry and Technology Prague; Sweden:

Linnaeus University; Cyprus: University of Cyprus; Slovenia: Jozef

Stefan Institute; Hungary: BioTalentum; Belgium: European Students’

Union; UK: Teacher Scientist Network

BUDGET: € 1.3m

WEBSITE: www.SciChallenge.eu

SciChallenge has received funding from the EU Horizon2020 pro-

gramme under grant agreement no. 665868

Child’s drawing of a scientist, KinderMuseum workshop 2014

Sabri Pllana representing SciChallenge at HiPEAC16

HiPEACINFO 46 19

How it all beganThe emmtrix spin-off is a product of excellent-rated research in

the EU project ALMA (ALgorithm parallelization for Multicore

Architectures), which set out to solve the programmability prob-

lems of embedded multicore systems. ‘Computer architecture is

becoming increasingly complex, meaning that systems need to be

programmed by experts. ALMA developed technology to pro-

gram embedded multicores based on the well-established, widely

used Scilab (www.scilab.org) and MATLAB (http://bit.ly/math-

works-MATLAB) languages. By supporting these languages, we

enable seamless integration of our parallelization product

emmtrix Parallel Studio (ePS) into existing workflow processes

and at the same time reduce the risks and costs involved in

implementing new programming environments,’ explains Timo

Stripf.

The technology developed during ALMA was successfully demon-

strated on several test cases, including ones in the telecommu-

nication domain and image processing for Fraunhofer, an

application-based research organization. ‘Our test cases show

that we can automatically parallelize applications for different

multicore architectures,’ says Timo. ‘In addition, our tool chain

takes out the complexity of programming, saves critical develop-

ment time and reduces costs of parallel software development by

over 50%,’ he adds.

From research to business:

the emmtrix storyCan successful companies arise out of European projects? The example of emmtrix Technologies

would suggest so. Here, emmtrix founders Timo Stripf, Frederik Riar and Professor

Juergen Becker explain how it started and provide first-hand insights into founding a tech company.

“Our tool chain takes out the complexity of programming,

saves development time and reduces software costs by 50%”

HiPEACINFO 4620

The idea of founding a company came up during the project. On

the way back from a highly successful project review in Brussels,

Professor Juergen Becker, head of the Institute for Information

Processing Technologies at the Karlsruhe Institute of Technology

(KIT) and ALMA project coordinator asked Timo: ‘What do you

think about creating a spin-off based on ALMA technology?’ At

first they thought of it as a bit of a joke; however, following fur-

ther discussion, they realized that there was a real market need

for this technology in Europe and potentially worldwide.

After receiving his PhD, supervised by Professor Juergen Becker,

Timo assembled a team consisting of himself, computer scientist

Michael Rueckauer, electrical engineer Oliver Oey and economist

Frederik Riar from the prestigious business school WHU-Otto

Beisheim School of Management, who brought in the business

perspective. The spin-off emmtrix (short for embedded matrix)

was born. The newly formed team managed to acquire signifi-

cant and highly competitive ‘EXIST-Transfer of Research’ seed

funding, provided by the German Federal Ministry for Economic

Affairs and Energy and the European Social Fund.

Target market and business model‘emmtrix offers technology that significantly simplifies embed-

ded multicore programming and reduces the overall develop-

ment effort, thereby closing the productivity gap between

singlecore and multicore processors. Our customers are compa-

nies that develop software for embedded multicore systems using

MATLAB or Scilab. Typically, these companies are in areas such

as the automotive, image processing, industrial automation and

telecommunications domains,’ Timo explains.

emmtrix uses a licence-based business model in combination

with integration and support services, as well as offering training

and consulting: ‘Future embedded systems will need more and

more cores. As a consequence, multicore programming is becom-

ing increasingly complex and requires resources and expertise

that are not always available within companies,’ says Frederik.

He adds: ‘Companies with internal R&D teams can use our paral-

lelization tools and solutions, while our embedded software

developers can solve individual parallelization challenges for

companies who don’t have such teams.’

How to start a spin-offTimo highlights the importance of making the decision to create

a spin-off out of a research project as early as possible. ‘It is cru-

cial to apply for seed money early,’ he says, expressing the hope

that instruments provided by projects such as TETRACOM will

take root and help more potential entrepreneurs get access to

capital. Timo further advises ‘talking to potential customers who

are not involved in the project: this helps to evaluate whether the

problem being solved in the project applies to a real market’.

Here, Frederik suggests, ‘startup teams should focus on what

makes them unique and how they can grasp their opportunities

in the best and fastest way’. He adds ‘Europe has its success sto-

ries and great programmes. Entrepreneurs should not just look

for capital; they should also take into consideration which poten-

tial programme, investor or partner can give them easier access

to well-established companies, especially in a business-to-busi-

ness setting. It can be tough for a startup to speak to the right

contact in large multinational corporations. In Silicon Valley, for

example, entrepreneurs are brought together with top managers

Frederik Riar (left) and Timo Stripf

Technology transfer: success stories

HiPEACINFO 46 21

and experienced engineers by professional accelerators to solve

problems in close collaboration. This is very important for tech

companies like us: the sooner technology is applied in the real

world, the earlier one can identify problem-solution fit and incor-

porate feedback or, if necessary, make a pivot or strategy shift.’

Timo supports this argument: ‘It is very important to speak to

potential customers in order to understand their needs, espe-

cially when going from proof-of-principle to proof-of-concept. He

explains that the emmtrix ‘strategy is to create demand at the

R&D level so that embedded engineers or parallel software

developers will go to their superiors and tell them about how

emmtrix can solve their problems.’ Frederik adds: ‘When talking

to potential customers, it’s essential to adapt the message to the

audience. Hence we explain to embedded software developers

how our products will make their day-to-day jobs more conveni-

ent, for instance by improving usability or helping them keep

tough deadlines. On the other hand, we show middle and top

management how our technology increases the overall efficiency

of software development and enables them to stay competitive

through faster time-to-market and shorter reaction time to con-

stantly changing customer demands.’

“When talking to potential customers, it’s essential to adapt the message to the audience.”

Perhaps more important than any training or accelerator pro-

gramme is shifting from a research perspective to a business

mindset early on, bearing in mind that these two areas require

very different approaches and priorities. ‘It’s important to assem-

ble a team with complementary skills and backgrounds and to

find a business professional as soon as possible,’ says Timo.

‘Many startups fail due to differences in the team, so it’s impor-

tant to have a transparent decision-making process and a healthy

discussion culture,’ Frederik suggests. ‘Another important aspect

during the market entry phase is to keep customers as close as

possible to have access to latest information about forthcoming

technology and organizational changes,’ he continues. When it

comes to recruiting high-potential employees, Frederik empha-

sizes that ‘start-ups should maintain a non-hierarchical culture

where the best idea wins. We can’t compete with large corpora-

tions on salary, but we can offer responsibility from day one and

steep learning curves’.

Supporting tech transfer through HiPEACHow can HiPEAC support researchers to transfer technology suc-

cessfully? Timo and Frederik suggest organizing best-practice

workshops, such as the ‘Transfer to Industry and Start-ups’ ses-

sion at the 2016 HiPEAC conference, and extending these over

several days. Workshops from business experts on how to develop

a business model or sales and marketing strategies would also be

very beneficial.

‘HiPEAC could for instance set up mentoring programmes for

potential spin-off teams,’ says Timo. He concludes: ‘HiPEAC

already provides an important place for new companies to get

their message out; it’s allowed us to make valuable contacts in

both industry and research. We need more success stories to

motivate people to take entrepreneurial action, as well as more

examples of spin-offs emerging out of European projects; here,

HiPEAC can play an important role by helping to establish a

start-up culture in academia.’

FOR FURTHER INFORMATION

visit the emmtrix website: www.emmtrix.com

DO YOU HAVE A GREAT STORY ABOUT TECHNOLOGY TRANSFER?

Email [email protected] with the details.

LOOKING FOR HIGHLY SKILLED CANDIDATES FOR YOUR START-UP?

Post your vacancies on the HiPEAC jobs portal: www.hipeac.net/jobs

A team with complementary skills is essential

“The sooner technology is applied in the real world, the earlier one can identify problem-solution fit

and incorporate feedback or change strategy.”

Technology transfer: success stories

HiPEACINFO 4622

COMPANY: Rapita Systems Ltd

MAIN BUSINESS: Verification solutions for customers in the avionics

and automotive electronics industries.

LOCATION: York, UK

WEBSITE: www.rapitasystems.com

Founded in 2004, Rapita Systems is a successful spin-out from

the University of York, providing tools and services to the critical

embedded software industry. Based in York, the company has

grown tenfold since being founded, recruiting top experts in reli-

able software. Rapita maintains good connections with the uni-

versity; its chairman is Professor John McDermid who is well

known in the safety world, and many of the company's staff have

PhD-level qualifications from York and other top institutions.

Rapita's vision is to see its tools used in every major aerospace,

automotive and space project. Over the last few years it has been

successful in seeing its technologies adopted across those

domains, especially in aerospace where many of the planes flying

today are tested using the Rapita Verification Suite (RVS). RVS is

a collection of verification tools for real-time embedded software,

including software timing/performance measurement, worst-case

execution time analysis and structural code coverage. In safety-

critical systems, verification and testing form a huge portion of

the cost of a project, often over 50%. RVS automates many man-

ual testing processes, which results in a much lower cost of verifi-

cation, more accurate test results and a better product.

“Rapita's vision is to see its tools used in every major aerospace, automotive and space project”

One of Rapita’s key differentiators from its competitors is its flex-

ible, solution-oriented approach. Rapita helps its customers solve

complex problems on projects with highly constrained resources,

by working closely with engineers and bringing new and

advanced technologies to the industry. In a recent project, Rapita

helped a customer by introducing its RapiCover tool for DO-178B

code coverage for an unusual embedded computer. RapiCover's

lightweight tracing technology reduced the software overhead of

measurements, which allowed the customer to speed up their

testing by a factor of 15 times.

“One of Rapita’s key differentiators from its competitors is its flexible, solution-oriented approach”

Rapita Systems has always been heavily involved in research and

development, focusing on advanced verification techniques for

high-integrity systems. Recognizing that customers can benefit

from this research even before it is fully developed into a prod-

uct, Rapita has created its Early Access Program as a way for

customers to access these technologies. The company's strategy

is to continue its success by making the best products for its cus-

tomers by transforming the latest technologies into successful

industrial reality.

DO YOU WORK FOR A THRIVING TECHNOLOGY SME?

WHAT ARE THE SECRETS OF YOUR SUCCESS?

Contact [email protected] with your story.

SME snapshot


What makes small or medium-sized enterprises (SME) working in the area of high-performance and/

or embedded compilation and architecture successful? Here, Jamie Pearce explains the business strategy which has allowed Rapita Systems, based in

York, UK, to grow from a university spin-off to an established SME.

HiPEACINFO 46 23

One of the most successful automotive processors is the Infineon

TriCore-based microcontroller. Already in its fifth generation,

these 32-bit microcontrollers are based on a unified RISC/MCU/

DSP processor architecture, which provides the best fit for mod-

ern automotive demands. The development of the TriCore family

of microcontrollers closely follows the need of the automotive

industry, with its ever-increasing critical requirements for perfor-

mance, reliability, safety, security, time to market, harsh environ-

ments, etc.

As an example, using AURIX, the latest generation of microcon-

trollers, the customer can reduce the effort required to ensure

safety by 30% while getting a performance increase of 50-100%.

This architecture was specially developed and refined to better

address the needs of the automotive domain in specific applica-

tions, such as the control of combustion engines, electrical and

hybrid vehicles, transmission control units, braking systems,

electric power systems, airbags, advanced driver assistance sys-

tems, etc.

Responding to industry needsThe needs of the automotive sector are typically collected and

addressed through a ‘triangular closed loop’ relationship between

the following participants:

• The original equipment manufacturer (OEM) identifies a need

for new or improved functionality.

• A tier one company, that is, a company which supplies the OEM,

defines the required function within the necessary parameters.

• The semiconductor supplier provides the right components to

enable the new function within the targeted overall constraints

(price, electrical, safety, security, etc.)

As in the research field, innovation and optimization are funda-

mental aspects of the development of the TriCore family. Only

through constant innovation, both in architecture and technol-

ogy, can the microcontrollers respond to the growing needs of

today’s automotive sector. That said, innovative aspects are

always carefully considered and introduced in close collabora-

tion with tier one companies and OEMs in order to ensure com-

patibility with the stringent needs of these customers.

Through the TriCore family of microcontrollers, Infineon gives its

typical automotive customers a competitive business advantage

while ensuring the compatibility of the modern vehicles to ever

more stringent environmental standards (for example, emission

standards). Without the capability of these modern microcon-

troller solutions, the implementation of the current environmen-

tal protection constraints would not be possible.

To get the full benefit of the architectural properties provided by

hardware solutions such as state-of-the-art TriCore microcon-

trollers, modern software approaches are needed. Architectural

features can help meet safety targets more easily while multicore

architectures can boost performance, but they need correspond-

ing software solutions capable of exploiting these features. In

addition to creating the TriCore microcontrollers, Infineon is also

delivering software solutions which allow customers a fast time

to market implementation of their own solutions.

HAVE YOU DEVELOPED TECHNOLOGY IN CLOSE COLLABORATION WITH

INDUSTRY?

Send us your story – email [email protected]

Infineon TriCore microcontrollers: turbocharging the automotive sector

In this feature, we explore how the HiPEAC community is developing the technology to power different industry sectors. Here, Rafael Zalman and Knut Hufeld give us an insight into how Infineon’s

TriCore microcontrollers respond to the ever-increasing demands of the automotive industry.

Industry focus

HiPEACINFO 4624

Petar Radojkovic’, Paul Carpenter, Jaume Abella and Francisco J. Cazorla of Barcelona Supercomputing

Center (BSC) explain how BSC is pioneering the use of this statistical approach in computer science.

Extreme Value Theory (EVT) is a branch of statistics which deals

with values at either end of the spectrum – the greatest devia-

tions from the median of probability distributions. It aims to

assess the probability of events more extreme than those previ-

ously observed using a sample of a random variable. Since its

introduction in the 1920s, EVT has been successfully applied in

multiple fields, including civil engineering, material testing,

finance and risk management. Now, researchers in BSC’s com-

puter sciences department are pioneering the use of EVT in com-

puter science and engineering, showing that EVT provides

powerful theorems and tools of great interest to our community.

Intractable problems in computer science are usually addressed

by designing an individual, heuristics-based (that is, approxi-

mate) approach and then tuning it for each specific problem and

metric. This requires substantial effort and deep understanding

both of the application and the target. BSC’s researchers have

presented problem-solving methods using EVT which are inde-

pendent of the problem addressed and can therefore be applied

to other intractable problems and metrics. As this approach does

not require profound understanding of the application or target,

the time/effort investment is significantly reduced.

The first problem addressed was thread assignment on multi-

threaded processors, part of process scheduling on modern pro-

cessors. The scientific paper summarizing this study, ‘Thread

Assignment in Multicore/Multithreaded Processors: A Statistical

Approach’ (http://bit.ly/EVT-thread-assignment), was the fea-

tured article in the January 2016 issue of IEEE Transactions on

Peac performance

Solving intractable computer science problems with Extreme Value Theory

Have you applied an innovative methodology to solve a research problem? Would you like to share your opinion on a specific

aspect of technology? We’d love to hear from you – email [email protected] with the details

EVT applied to thread assignment

HiPEACINFO 46 25

As far as moving data to and from the processor is concerned, the

main constraints are the external memory devices and input/out-

put (I/O) interfaces rather than the processor core IP. ARM sells

processor core IP rather than complete integrated circuits, and it

is up to the silicon partner to build a complete system-on-chip,

which integrates the ARM IP into a single package, together with

appropriate I/O and memory interfaces.

Inside the chip, the ARM IP interfaces to the rest of the silicon

functionality using a high-speed internal memory bus such as

AMBA. The ARM Cortex-A72, for example, even with a modest

clock frequency of 1 GHz, can support an internal bus capable of

reading and writing a total of 32 GB/s, which is sufficient to satu-

rate four channels of dual data-rate (DDR) memory. Only new

serial memory devices, such as Micron’s HMC, are capable of

breaking through this memory wall.

Designed appropriately, the integrated system-on-chip could also

handle 100s of GB/s of I/O. So, as far as moving large amounts

of data through a microprocessor device is concerned, the appli-

cability towards big data application of a chip depends more on

the design of the memory and I/O components than the proces-

Peac performance

Technology opinion: Matching processors to big data needs

Professor John Goodacre, Director of Technology and Systems, ARM

At ARM, we create intellectual

property for processor design. The

company, which recently cele-

brated its 25th birthday, has

achieved enor mous success:

around 75 billion processor cores

have been shipped into a myriad

of different devices, suggesting

great versatility across application

domains. But could low-power processors such as ARM’s really

handle big data workloads? In this write-up, I’d like to provide a

high-level overview of how big data applications place require-

ments on the design of a processor core.

There are two main issues to take into consideration: first, the

bandwidth available to transfer data to/from the processor; and

second, the maximum number of operations per clock cycle that

the processor can perform.

Computers. Since January, the article has appeared in the maga-

zine Computing Now and has been promoted through videos in

English (https://www.youtube.com/embed/Zaq2g_bVD6s) and

Chinese (https://www.youtube.com/embed/nqElaPiNesY).

Modern multithreaded processors are highly complex, with many

cores, many hardware threads and many levels of shared

resources. Concurrently running application threads share pro-

cessor resources at multiple levels, including functional units,

caches and on-chip interconnection networks. There are a large

number of possible assignments of threads to cores and, given a

particular assignment, the complexity of the architecture makes

it very hard to predict the resulting performance. Finding an opti-

mal thread assignment is therefore intractable.

The BSC scientific paper presents a statistical approach to this

problem. Instead of trying to find the optimal solution, the opti-

mal performance is estimated using random sampling and EVT.

The method executes each assignment on the target machine and

records its performance. Based on the recorded performance val-

ues, EVT is used to estimate the optimal performance, including

confidence bounds, that is, ranges of estimates based on a sample.

BSC researchers also observed that if a random sample contains

hundreds of random observations, the best-performing assign-

ment in the sample is likely to be in the top 1% of solutions.

Hence if no heuristics-based algorithm is available to find a solu-

tion, a good alternative could be to take the best solution in the

sample. The study also compared this random-sampling approach

versus the predicted optimal performance, and concluded that,

for this problem, a good solution can in fact be found using ran-

dom sampling.

BSC researchers have applied random sampling and EVT to graph

partitioning of streaming applications (http://bit.ly/EVT-optimal-

partition) and are leading the European PROXIMA project (www.

proxima-project.eu) and a project with the European Space

agency which are applying these techniques, along with the use

of time-randomized computing platforms, to analyse the timing

behaviour of applications in real-time embedded systems.

HiPEACINFO 4626

sor design, meaning that a modern power-efficient ARM core can

certainly be competitive.

The second key challenge in processor design relates to the num-

ber of operations that the arithmetic unit can carry out within a

single clock cycle. This depends predominantly on the proces-

sor’s issue width, which is the maximum number of instructions

per cycle (IPC) that the processor can execute. It also depends,

however, on the characteristics of the software code, including

the dependencies between instructions, i.e. whether multiple

instructions are free of dependencies and can be executed in par-

allel in the same cycle.

The big data processing landscape is today dominated by multi-

core superscalar processors. Such processors are preferred

because the alternative of continually extending the issue width

of a single-core processor quickly reaches diminishing returns: an

exponentially increasing cost in silicon and energy consumption

generates only a small increase in performance.

The ratio of operations to byte of I/O is defined by any specific

application. If a Big data application has a small number of oper-

ations per unit of data, then total capital and operational costs

can be greatly reduced using a larger number of smaller proces-

sors such as the Cavium, ARM architecture based, ThunderX

(www.cavium.com/ThunderX_ARM_Processors.html). This device

is perfectly capable of meeting the needs of applications that

focus more on data movement than compute. If an application

needs more operations per unit of data, then devices using a

wide-issue processor such as the Cortex-A57 processor as used in

the AMD Seattle devices could be more appropriate.

As big data processing needs grow, the challenge is to generally

match the processor’s designed capability to application require-

ments, which can only be done precisely through an understand-

ing of application needs and the co-design between the hardware

and software. However, since only a few vertical businesses have

the necessary resources and commercial volume to match an

ideal processor design to each application, most designs will

have to take a more general-purpose approach. This could be

achieved through over-provisioning a single design, or through

offering multiple processors in the same chip, each processor

with different capabilities.

The latter approach, otherwise known as heterogeneous multi-

core processing, means that only the most appropriate processors

for the job in hand need to be powered up. By design, this proces-

sor best matches the type and number of operations required by

the application. To maximize cost efficiency, such heterogeneity

should be tightly integrated into the design. Heterogeneous pro-

cessing poses specific challenges for software developers – but

that’s a story for another day.

This article first appeared on the RETHINK big project website:

http://rethinkbig-project.eu

Peac performance

Node (left) for Avantek high density ARM blade server (right), incorporating twwo Cavium® ThunderX™ CN8890 48 core ARMv8 processors (Image copyright: Avantek)

HiPEACINFO 46 27

Career talk: Linda Dewar, Systems Administrator, Edinburgh Parallel Computing Centre (EPCC)

HiPEAC futures

What did you study at university and what training did you

undertake subsequently?

I studied for a physics degree at Edinburgh University, and fol-

lowed that with an MSc in microelectronics. My first job after

graduating was as an engineer in high-volume manufacturing in

the semiconductor industry, first with INMOS and later with the

Digital Equipment Corporation. This was in the early 90s when

computers were not nearly as mainstream as they are now; in

fact for the first few years I didn't even have a computer on my

desk and had to share one with several other colleagues!

Although I enjoyed my job as an engineer, it was a project which

involved writing test programs for computer chips that made me

realize that I preferred this to manufacturing. I returned to uni-

versity to do a postgraduate course in computing, and this led to

my first job in IT – this time with Motorola, supporting computer

integrated manufacturing for components for mobile phones.

When the downturn in UK semiconductor manufacturing hap-

pened around 2002, I was made redundant by Motorola and was

very lucky to be employed by EPCC to work in the team support-

ing HPC systems - first Hector and now Archer - a job I would

never have dreamt of having just a few years previously.

What three words sum up your job? What do you like best

about it?

Busy, varied, technically challenging. In this environment, tech-

nologies, tools and applications are constantly changing, which

means there is something new to learn every day.

Describe what your job involves on a typical day.

A typical day involves sharing a rota with colleagues to respond

to problems which users have logged with our helpdesk. These

include problems with transferring data, jobs running slowly,

account administration, etc. A large part of my work is involved

in the careful planning of changes and upgrades to the system

which are to be carried out without risk to either our HPC service

or its data. We also spend a lot of time monitoring the HPC sys-

tems for hardware/software/network problems or cyber security

alerts and responding to them before they can cause any prob-

lems for the service.

What's the most surprising thing that's happened to you on

the job?

I think that being a part of a very small team with responsibility

for tens of millions of pounds’ worth of equipment has come as

the biggest surprise to me!

What key skills and experience are essential for this job? What

kind of personality do you think is best suited to it?

On the technical side, skills in Linux systems administration, net-

working, storage and security along with HPC knowledge are all

essential. Also very important is the ability to keep a clear head

when faced with problems, work well under pressure, good plan-

ning and organizational skills and a strong aversion to taking

risks. Working well in a small, close-knit team is also crucial.

WHERE WILL YOUR CAREER TAKE YOU NEXT?

Check out the numerous job opportunities on the HiPEAC jobs portal:

www.hipeac.net/jobs

HiPEACINFO 4628

Creating the future through international exchange: HiPEAC collaboration grants

Offered to PhD students and junior post-doctoral researchers within the HiPEAC network, collaboration grants allow students to spend time at

another research institute, working jointly with a new research group to work on key challenges for computing systems. Between 20 and 25 collaboration grants are awarded each year. For further information

about how to apply, visit www.hipeac.net/mobility/collaborations.

HiPEAC futures

NAME: Diego Felix de Souza

RESEARCH CENTRE: Instituto de

Engenharia de Sistemas e Computa-

dores Investigação e Desenvolvimento

em Lisboa (INESC-ID Lisbon)

HOST INSTITUTION: Technische

Universität Berlin (TU Berlin)

DATE OF COLLABORATION:

16/09/15-20/12/15

PORTUGUESE-GERMAN EXPERTISE DELIVERS MORE EFFICIENT VIDEO DECODING

High-efficiency video coding (HEVC), also known as H.265, is a

video compression standard which offers roughly twice the data

compression as advanced video coding, the current widely used

format, while offering the same video quality. Alternatively, it

offers greatly improved video quality at the same bit rate. Over

the last few years, the Embedded Systems Architecture group

managed by Professor Ben Juurlink at TU Berlin has developed a

highly optimized, multi-threaded CPU-based HEVC decoder.

Exploiting other research directions, the INESC-ID Lisbon group

has parallelized most of the HEVC decoder modules to be exe-

cuted on state-of-the-art GPU devices.

The main aim of this collaboration was to develop a joint research

initiative to create a high-performance, CPU+GPU HEVC

decoder, where the CPU is responsible for the most irregular and

sequential modules, such as the entropy decoder for lossless data

decompression, and the remaining modules are accelerated by

the GPU device. The collaboration aimed to fill a gap in the sci-

entific literature on how to combine state-of-the-art CPU and

GPU architectures to provide more efficient HEVC decoding

structures.

As well as providing an excellent opportunity to develop my PhD

research, supervised by Professor Leonel Sousa, the collaboration

also allowed the two groups to consolidate future opportunities.

It consolidated joint working between two HiPEAC research

teams with proven research experience in developing efficient

encoder and decoder modules for state-of-the-art parallel

architectures.

Special thanks to Professor Ben Juurlink and the entire Embedded

Systems Architecture group, in particular Dr Mauricio Álvarez-

Mesa, Chi Ching Chi and Biao Wang.

Professor Ben Juurlink at TU Berlin commented: ‘I am extremely

happy about the collaboration. We had the design of a hybrid

CPU+GPU H.265/HEVC decoder, while Diego had all the stan-

dalone kernels mapped onto GPU. It was therefore extremely

useful that we teamed up to develop a full CPU+GPU H.265/

HEVC decoder, rather than just a few kernels as most papers do.

Furthermore, our results show that under certain circumstances

our CPU+GPU decoder is faster than a very high-performance

CPU implementation, which is a significant breakthrough. What’s

more is that we were able to achieve this in just three months

thanks to the groundwork already laid by our team and Diego.

All that is left to do is finish writing the paper and submit it to a

high-impact conference or journal.’

HiPEACINFO 46 29

HiPEAC futures

Training the next generation of experts: HiPEAC internships

Did you know that SMEs can get internships fully funded through HiPEAC, or that larger companies can get 50% of internship costs

funded? Once a year, HiPEAC invites all of its company members to submit research projects which they’d like interns to work on. HiPEAC

students then submit their applications for internships, which are evaluated by the companies concerned and candidates selected before

the steering committee decides on final allocations. Further information is available on the HiPEAC website: www.hipeac.net/mobility/internships

NAME: Tsvetan Shoshkov

RESEARCH CENTRE: Technical University

of Sofia

HOST COMPANY: Thales Research and

Technology, Palaiseau, France

DATE OF INTERNSHIP:

27/07/2015 - 27/11/2015

ON THALES´ RADAR FROM SOFIA TO PARIS

For my PhD at the Technical University of Sofia, I have been

focusing on the implementation of digital processing systems

with field-programmable gate arrays (FPGAs) using the

Peripheral Component Interconnect Express (PCIe) interface, a

high-speed serial computer expansion bus standard. The PCIe

standard is a popular choice for high-speed serial communication

in networking, computing, industrial and embedded systems.

Thanks to HiPEAC, I was able to take up an internship at Thales

Research and Technology under the supervision of François

Duhem. The main aim of the internship was to add a PCIe inter-

face to a radar signal processing architecture implemented on an

FPGA chip. The radar processing architecture rested on a net-

work on chip (NoC) and includes processing elements and other

auxiliary components. PCIe communication was used to stream

data through the NoC towards the processing elements. The

design was implemented on a custom FPGA board based on a

Xilinx Virtex-6 device. Another board based on general-purpose

processors was used as a host to stream data in and out over the

PCIe interface.

As a result of the internship, PCIe interface communication was

successfully implemented. Dealing with issues as they arose

helped me amplify my technical skills: the main challenges were

establishing a proper clock domain crossing and metastability

protection. Another challenge was setting up the test environ-

ment and connection between the two boards, which form part

of the whole system.

System block diagram

According to Research Engineer François Duhem: ‘Thales

Research and Technology developed a radar signal processing

architecture based on an FPGA device to address the performance

and power consumption requirements of future radar applica-

tions. Tsvetan was responsible for adding a PCIe interface to the

architecture that did not rely on off-the-shelf intellectual prop-

erty in order to have full control over the design and be able to

reuse it in other projects as well.’

HiPEACINFO 4630

HiPEAC futures

Three-minute thesis

The HiPEAC network numbers over 800 PhD students. Between them, they defend, on average, more than two theses a week. A directory of PhD student profiles showcasing their research areas, theses, work experience and skills will soon be available on www.hipeac.net. Watch this space for further information.

NAME: Edgardo Mejía Roa

RESEARCH CENTRE: Complutense University of Madrid

ADVISERS: Dr Alberto Pascual Montano, Dr Francisco Tirado Fernández

THESIS: Optimizing the Non-Negative Matrix Factorization for

Bioinformatics

FEATURED RESEARCH: HARNESSING GPUS TO OPTIMIZE BIOINFORMATICS ANALYTICS

Current high-throughput technologies used in biology generate large datasets requiring

analysis and interpretation. Among the data-mining techniques used to form hypothe-

ses, non-negative matrix factorization (NMF) has been identified as a highly effective

method for discovering patterns, as it is able to extract interpretable parts from high-

dimensional datasets. However, the computing time required to process large data

matrices might become impractical, especially in gene expression analysis, where two

popular clustering methods (sample classification and biclustering) use a probabilistic

model that executes NMF a high number of times.

This thesis proposes the parallelization of NMF and both clustering methods to provide

a new analytics tool, named bioNMF, for the scientific community. Implementing the

NMF algorithm using graphics processing unit (GPU) technology achieves 40 times the

speed offered by traditional processors. However, many GPU architectures are in the

form of a detached device connected to the CPU, with a low-capacity on-board memory.

This configuration requires the transfer of input data from the CPU’s main memory to

the GPU’s memory before starting the process and the transfer of output data back to

the CPU’s memory once the computing process is complete. In addition, as the on-board

memory is usually far less than in its CPU counterpart, to analyse large datasets the

algorithm must be able to transfer and process the input data blockwise.

To overcome this, data are distributed among multiple devices synchronized through a

message-passing interface. Using multiple GPUs in this way achieves a super-linear

speedup over a single device if the data portions assigned to each device are small

enough to be transferred once, at the start of the algorithm. The clustering methods can

use grid computing to execute the numerous instances of NMF, each executed in a com-

puting node comprising a multi-GPU system. Finally, web and web-service interfaces

provide a user-friendly environment.

Access the public online version for free: http://bionmf.dacya.ucm.es

Multi-GPU source code: http://bioinfo-cnb.github.io/bionmf-gpu

Benjamin Andreassen Bjørnseth awarded best FPGA-related master’s thesis award

Norwegian University of Science and

Technology (NTNU, after its initials in

Norwegian) student Benjamin

Andreassen was recently awarded the

best master’s thesis 2015 by the

Norwegian Field-Programmable Gate

Array (FPGA) Forum. The work for

Benjamin’s thesis, named ‘Enabling

Research on Energy-Efficient System

Software Using the SHMAC Infra-

structure’, led to a paper which was

accepted for the 2016 Design,

Auto mation and Test in Europe

(DATE) conference: www.date-confer-

ence.com/conference/session/6.4.

SHMAC (Single-ISA Heterogeneous

Many-Core Computer) is part of the

Energy-Efficient Computing Systems

initiative at NTNU.

Benjamin has also been awarded the

2015 Norwegian Computing Center

prize for the best master’s thesis in

computer science or mathematics at

NTNU.

Benjamin was supervised by Lasse

Natvig and Asbjørn Djupdal.

The thesis can be downloaded from

https://daim.idi.ntnu.no/

masteroppgave?id=11723.

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