HiSIM HV 1.0.2, Version 1.02 User’s Manualhome.hiroshima-u.ac.jp/usdl/.../C-Code/HiSIM_HV_1.0.2_UsersManual.pdf · HiSIM HV 1.0.2 Copyright c 2008 Hiroshima University & STARC:

HiSIM HV 1.0.2, Version 1.02 User’sManual

Copyright c© 2008Hiroshima University & STARC

All Rights Reserved

HiSIM HV 1.0.2 Copyright c© 2008 Hiroshima University & STARC: confidential

HiSIM HV Developers

Hiroshima University:

N. Sadachika, M. Miyake, M. Yokomichi, T. Kajiwara, A. Oohashi, T. MinamiY. Oritsuki, T. Sakuda, T. Yoshida, T. Murakami, H. Kikuchihara, U. Feldmann

H. J. Mattausch, M. Miura-Mattausch

Semiconductor Technology Academic Research Center:

T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, R. InagakiY. Furui, N. Fudanuki

HiSIM HV 1.0.2, Version 1.02

date : 2008.6.27

2


Contents

1 Physical Constants Used 5

2 Model Concept 5

3 Extension to LDMOS and HVMOS 7

4 Charges 9

5 Drain Current 14

6 Threshold Voltage Shift 16

6.1 (I) Short-Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 (II) Reverse-Short-Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Depletion Effect of the Gate Poly-Si 24

8 Quantum-Mechanical Effects 26

9 Mobility Model 28

10 Channel-Length Modulation 31

11 Narrow-Channel Effects 34

11.1 Threshold Voltage Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11.2 Mobility Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11.3 Transistor Leakage due to Shallow Trench Isolation (STI): Hump in Ids . . . . . . . . . . 35

11.4 Small Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 Effects of the Source/Drain Diffusion Length for Shallow Trench Isolation (STI) Tech-

nologies 39

13 Temperature Dependences 41

14 Resistances 43

15 Capacitances 48

15.1 Intrinsic Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

15.2 Overlap Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

15.3 Extrinsic Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

16 Leakage Currents 52

16.1 Substrate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1.1 Impact-Ionization Induced Bulk Potential Change . . . . . . . . . . . . . . . . . . 53

16.2 Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3


16.3 GIDL (Gate-Induced Drain Leakage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

17 Source/Bulk and Drain/Bulk Diode Models 59

17.1 Diode Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

17.2 Diode Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

18 Noise Models 65

18.1 1/f Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

18.2 Thermal Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

18.3 Induced Gate Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

18.4 Coupling Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

19 Non-Quasi-Static (NQS) Model 67

19.1 Carrier Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

19.2 Delay Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

19.3 Time-Domain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

19.4 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

20 Self-Heating Effect Model 69

21 DFM Model 71

22 Exclusion of Modeled Effects and Model Flags 72

23 List of Instance Parameters 74

24 Default Parameters and Limits of the Parameter Values 75

25 Overview of the Parameter-Extraction Procedure 83

25.1 General MOSFET Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

25.2 HiSIM HV Specific Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

References 86

4


1 Physical Constants Used

2 Model Concept

Requirement for accurate modeling of high-voltage MOSFET is increasing. There are two types of

structures commonly used. One is the asymmetrical laterally diffused structure called LDMOS and the

other is the symmetrical structure, which we distinguish by referring to it as HVMOS. HiSIM-LDMOS/HV

is valid for modeling both structure types, and has been developed as an extension of the HiSIM model

for conventional MOSFETs. HiSIM (Hiroshima-university STARC IGFET Model) is the first complete

surface-potential-based MOSFET model for circuit simulation based on the drift-diffusion theory, which

was originally developed by Pao and Sah [1]. The most important advantage of the surface-potential-based

modeling is the unified description of device characteristics for all bias conditions. The physical reliability

of the drift-diffusion theory has been proved by 2D device simulations with channel lengths even down

to below 0.1µm [2]. To obtain analytical solutions for describing device performances, the charge sheet

approximation of the inversion layer with zero thickness has been introduced (for example [3]). Together

with the gradual-channel approximation all device characteristics are then described analytically by the

channel-surface potentials at the source side (φS0) and at the drain side (φSL) (see Fig. 1).

These surface potentials are functions of applied voltages on the four terminals; the gate voltage Vg, the

drain voltage Vd, the bulk voltage Vb and the reference potential of the source Vs. The resistance in the

contact region causing potential drops affects also the surface potential values. Since the surface potentials

are implicit functions of the applied voltages, model-internal iteration procedures are introduced only for

calculating φS0 and φSL is calculated with in addition to the global iteration of the circuit simulator.

The potential φS(∆L) is calculated with φS0, φSL and Vds together with a fitting parameter.

S

φ

φ

φ

D

G

B

SL

S0

S0+Vds

Fig. 1: Schematic of the surface potential distribution in the channel.

The most important features of LDMOS/HVMOS devices, different from the conventional MOSFET, are

originating from the drift region introduced to achieve the sustainability of high voltages. By varying the

lengh as well as the dopant concentration of the drift region, various devices with various operating biase

5


conditions are realized as shown in Fig. 2 for the LDMOS structure. In any cases, the drift region affects

as the resistance for the current flow and also induces additional charge, which causes the especially

unique features of the LDMOS capacitances. Thus accurate modeling of the drift region is the main task

of HiSIM-LDMOS/HV.

n+ n+p

Drift Region

GateSource Drain

Ldrift

LoverLD

n- (=Nover)

Lover

Fig. 2: Schematic of the typical LDMOS structure and device parameters.

Fortunately, the HiSIM compact model determines the complete potential distribution along the gate

including the surface potential at the source side φS0, the potential at the pinch-off point φSL, the potential

at the channel/drain junction, φS(∆L), and the final potential value at the drain contact φS0 + Vds as

shown in Fig. 3.

Gate

S0+Vds

S(L)

Drain

Gradual-Channel

S0

Qi

L

SL

Potential Distribution

∆

φ∆φ

φ

φ

Fig. 3: Schematic of the surface potential distribution in the channel at the drain side of the LDMOSdevice structure.

For the LDMOS/HVMOS device the iterative solution is only one possible to model the specific features

of this device accurately, because the resistance effect in the drift region is dependent on the bias condition

as well as the detailed geometrical LDMOS/HVMOS structure. The basic modeling method is taken over

from the HiSIM2 model for advanced MOSFETs, and additional equations for capturing the drift-region

effects are included. Since the overlap length is relatively long for LDMOS/HVMOS, accurate surface-

potential calculation for the overlap region as a function of applied voltages is also necessary for accurate

prediction of the high-voltage MOS capacitances.

6


3 Extension to LDMOS and HVMOS

HiSIM HV enables to treat both the asymmetrical structure, where the typical one is LDMOS, and the

symmetrical structure. To make the structural definition easy, Flag COSYM is introduced as shown

in Fig. 4. COSYM=0 refers to the asymmetrical LDMOS, and all parameters have to be determined

independently. COSYM=1 refers to symmetrical HVMOS, and all parameters of the drain side are

copied to the source side. HiSIM HV considers the length of the drift region Ldrift, the overlap lengh

Lover, and the impurity concentraion of the drift region Nover explicitly. A schmatic of the general

structures for LDMOS and HVMOS are shown in Fig. 5 for the p-channel case. In the LDMOS case

independent structures at the source side and the drain side are distinguished, and the Ldrift region is not

introduced at the source side. In the HVMOS case, the parameter values for the drain side have to be

determined, and are copied to the source side automatically. If parameters are not determined, defalut

values are taken.

Structural parameters haveto be determined for bothsource and drain.

All structural parameter valuesof drain side are copied to thoseof source side.

COSYM= 1

= 0

LDMOS (asymmetrical) HVMOS (symmetrical)

Fig. 4: Device parameters in HiSIM-LDMOS/HV.

One most significant of the LDMOS/HVMOS devices feature is that the drain current continues to

increases steeply even under the saturation condition, which is refered as the quasi saturation. Other

features are observed the in capacitances, showing strong sharp peaks, depending on the structure. All

these phenomena are caused by the highly resistive drift region, enabling the high-voltage application of

MOSFETs. The structural parameters of the LDMOS/HVMOS device are explicitly considered in the

resistance modeling, and the resistance effect is considered as the potential drop solved iteratively within

HiSIM HV.

Thus the basic modeling of LDMOS/HVMOS is kept the same as in the conventional MOSFET model.

HiSIM HV solves the potential distribution along the surface by solving the Poisson equation iteratively

including the resistance effect in the drift region, where the bias dependence of the resistance is considered.

HiSIM limits the minimum value of the applied bulk voltage Vbs to -10.5V. However, this limitation can

be changed by the model parameter VBSMIN.

The HiSIM HV model parameters introduced in section 3 are summarized in Table 1.

7


HiSIM-LDMOS/HV

Asymmetrical LDMOS

channelLover

n+ p-SiLdrift2

n+Loverld Ldrift1

Nover

Symmetrical HV-MOS

n+ n+Ldrift2 Ldrift1 Loverld

Nover

Ldrift2Ldrift1Loverld

Nover

channel

p-Si

Fig. 5: Device parameters in HiSIM-LDMOS/HV.

Table 1: HiSIM-LDMOS/HV model parameters introduced in section 3 of this manual.

LOVER overlap length at source sideLOVERLD overlap length at drain, and at source, if COSYM=1LDRIFT1 length of lightly doped drift region at drain, and at source, if COSYM=1LDRIFT2 length of heavily doped drift region at drain, and at source, if COSYM=1NOVER impurity concentration of LOVERLD at drain, and at source, if COSYM=1VBSMIN minimum Vbs voltage applied

8


4 Charges

The effective channel length Leff and width Weff are calculated from the gate length Lgate and width

Wgate, where Lgate and width Wgate deviate from the gate drawn length and width

Lgate = Ldrawn + XL (1)

Wgate =Wdrawn

NF+ XW (2)

Lpoly = Lgate − 2× LL(Lgate + LLD)LLN

(3)

Wpoly = Wgate − 2× WL(Wgate + WLD)WLN

(4)

Leff = Lpoly −XLD−XLDLD (5)

Weff = Wpoly − 2×XWD (6)

where XL and XW describe the difference between the real and drawn gate length and width, whereas

XLD/XLDLD and XWD account for the overlaps of source/drain contact and the gate oxide. LL,

LLD, LLN, WL, WLD, and WLN are further model parameters for including Lgate or Wgate depen-

dencies on Leff and Weff . Fig. 6.

XLDLDLeff

Lpoly

XLD

(LOVERLD for capacitance)

Fig. 6: Cross section of the device.

All device characteristics are determined on the basis of the charge control by applied voltages and by

expressing the MOSFET charges as functions of the surface potentials. Under the charge-sheet approxi-

mation the charges on the four MOSFET terminals QG(gate), QB(bulk), QD(drain), and QS(source), are

described for the symmetrical the source/drain contacts as [4]:

9


QG = −(QB + QI) (7)

QB = Weff

∫ Leff

0

Qb(y)dy (8)

QI = Weff

∫ Leff

0

Qi(y)dy (9)

QD = Weff

∫ Leff

0

y

LeffQi(y)dy (10)

QS = QI −QD (11)

where QB and QI are the depletion charge and the inversion charge, respectively, and y is the position

along the channel. Leff and 0 are the channel-end positions at the drain side and the source side,

respectively. For LDMOS with the asymmetrical source/drain contacts, the same definition is applied in

HiSIM, contrary to other exisiting models. The reason for the consistent treatment even for the LDMOS

is the consistent treatment of the resistance effect of the drift region. In addition to the intrinsic charges

the charge induced in the overlap region causes another contribution in capacitances, which is described

in section 15.

By applying the Gauss law, the charge density induced in the channel is derived from the Poisson

equation [5]:

−(QB + QI) = Cox

(V ′

G − φS(y))

=

√2εSiqNsub

β

[exp−β(φS(y)− Vbs)

+ β(φS(y)− Vbs)− 1

+np0

pp0

exp(β(φS(y)− φf(y))

)− exp

(β(Vbs − φf(y))

)] 12

(12)

Cox =εox

TOX(13)

V ′G = Vgs −VFBC + ∆Vth (14)

β =q

kT(15)

where VFBC is the flat-band voltage, TOX is the physical gate-oxide thickness, and ∆Vth is the threshold

voltage shift in comparison to the threshold voltage of a long-channel transistor [6]. The electron charge

is denoted by q, and εSi and Nsub are the silicon permittivity and the substrate impurity concentration,

respectively. The Boltzmann constant and the lattice temperature in Kelvin are k and T , respectively.

The quasi-Fermi potential φf(y) preserves the following relationship:

φf(Leff)− φf(0) = Vds,eff (16)

where Vds,eff is introduced to fit measured transition characteristics of the channel conductance gds be-

tween the linear region and the saturation region to compensate for insufficiencies of the charge-sheet

approximation as

10


Vds,eff =Vds[

1 +(

VdsVds,sat

)∆] 1

∆(17)

where

∆ =DDLTMAX · T1DDLTMAX + T1

+ 1 (18)

T1 = DDLTSLP · Lgate + DDLTICT (19)

and Vds,sat is calculated by solving the Poisson equation analytically by neglecting the inversion carrier

density.

The electron concentration at equilibrium condition np0 is

np0 =n2

i

pp0(20)

where the intrinsic carrier concentration ni is

ni = ni0T32 exp

(−Eg

2qβ

), (21)

pp0 is approximated to be Nsub, and Eg describes the temperature dependence of the bandgap (see sec-

tion 13).

The surface potentials, φS0 = φS(0) at the source side and at the pinch-off point φSL = φS(Leff − ∆L)

are calculated by solving Eq. (12) iteratively, where ∆L is the length of the pinch-off region under the

saturation condition (see section 10). Calculated φS characteristics are depicted schematically in Fig. 7.

φSL

φ S0

Vfb Vth Vgs

φS

Fig. 7: Surface potentials as a function of the gate voltage, Vgs.

The Poisson equation and the Gauss law are used to derive the inversion charge and bulk charge related

charge-density equations under the assumption of a homogeneous substrate impurity distribution as

Qb(y) = −

√2εSiqNsub

β


+ β(φS(y)− Vbs)− 1

] 12

(22)

Qi(y) = −Cox(V ′G − φS(y)) +

√2εSiqNsub

β


+ β(φS(y)− Vbs)− 1

] 12

(23)

11


After integrating the equations along the channel from the source side (y = 0) to the drain side (y = Leff),

we obtain analytical equations for QB and QI, which are described as a function of φS0 and φSL. These

integrations are lengthy but straightforward and the details are omitted in this manual. As an example,

the final equation for QB is given in Eq. (24).

QB = Weff ·NF∫ L

0

Qbdy

=−∫ L

0

Qb

kTµWeff ·NF

qIds(QiβdφS − dQi)

=− kT

q

µ(Weff ·NF)2

Ids

∫ QbQiβdφS −Q′

BdQ′I)

=− µ(Weff ·NF)2

Ids

[const0 Cox(VG −VFBC− φS)

1β

23β(φS − Vbs)− 1

32

+ const0 Cox1β

23

1β

25β(φS − Vbs)− 1

52 − const02 1

β

12β(φS − Vbs)− 1

2]φSL

φS0

− kT

q

µ(Weff ·NF)2

Ids

[const0 Cox

1β

23β(φS − Vbs)− 1

32 +

12const02βφS

]φSL

φS0

=− µ(Weff ·NF)2

Ids

[const0 Cox(VG −VFBC)

1β

23

[β(φS − Vbs)− 1

32]φSL

φS0

− const0 Cox1β

23

[φS

β(φS − Vbs)− 1

32]φSL

φS0

+ const0 Cox1β

23

1β

25

[β(φS − Vbs)− 1

52]φSL

φS0

− const02 1β

12[β2(φSL − Vbs)2 − 2β(φSL − Vbs) + 1− β2(φS0 − Vbs)2 + 2β(φS0 − Vbs)− 1

]]− 1

β

µ(Weff ·NF)2

Ids

[const0 Cox

1β

23β(φS − Vbs)− 1

32 +

12const02βφS

]φSL

φS0

(24)

Here const0 is defined as

const0 =

√2εSiqNsub

β(25)

while µ and Ids are the carrier mobility and the drain current, respectively. To reduce simulation time

without sacrificing the accuracy, a major effort in HiSIM is directed towards the efficient calculation of

the three independent charges QB, QI and QD.

Figure 8 shows a schematic plot of these charges as a function of Vgs for two fixed Vds values.

The HiSIM model parameters introduced in section 4 are summarized in Table 2.

12


-3

-2

-1

0

1

2

3

-1.5 -1 -0.5 0 0.5 1 1.5 2

QB

Qx

(10-1

2 C)

Vgs (V)

QG

Vds = 1.0V

Vds = 0.1V

QIVth

Cgg

Cdd

Fig. 8: Charges as a function of Vgs.

Table 2: HiSIM model parameters introduced in section 4 of this manual. # indicates an instanceparameter.

#NF number of gate fingersXL difference between real and drawn gate lengthXW difference between real and drawn gate widthXLD gate-overlap in length at source side

XLDLD gate-overlap in length at drain sideXWD gate-overlap in width

LL coefficient of gate length modificationLLD coefficient of gate length modificationLLN coefficient of gate length modificationWL coefficient of gate width modification

WLD coefficient of gate width modificationWLN coefficient of gate width modificationVFBC flat-band voltageVBI built-in potentailTOX physical gate-oxide thickness

*DDLTMAX smoothing coefficient for Vds

*DDLTSLP Lgate dependence of smoothing coefficient*DDLTICT Lgate dependence of smoothing coefficient

13


5 Drain Current

The drift-diffusion theory describes the drain current Ids as [1]

Ids = Weff ·NF · q · µ · n(y) ·(−dφS(y)

dy+

1β· d ln n(y)

dy

)(26)

where n(y) is the carrier density calculated from the relationship

Qi(y) = q · n(y) . (27)

Under the gradual-channel approximation with further approximations of an idealized gate structure and

uniform channel doping, the final equation for Ids is written [3, 5]

Ids =Weff ·NF

Leff· µ · Idd

β(28)

Idd = Cox(βV ′G + 1)(φSL − φS0)−

β

2Cox(φ2

SL − φ2S0)

− 23const0

[β(φSL − Vbs)− 1

32 −

β(φS0 − Vbs)− 1

32]

+ const0[

β(φSL − Vbs)− 1 1

2 −β(φS0 − Vbs)− 1

12] (29)

The above description includes the further approximation that the mobility µ is independent of position

along the channel y. A constant mobility approximation along the channel has been estimated to cause a

few % of inaccuracy, which is not severe for the drain current. However, the position dependent mobility

has strong influence on higher-order phenomena related to distributed effects along the channel. There-

fore, the potential distribution along the channel, which is exactly the origin of the position dependence

of the mobility, has to be considered to derive analytical equations for these higher-order phenomena (see

for example section 18). Here a model parameter KAPPA is introduced for Cox = ε0KAPPA/TOX,

where ε0 and KAPPA are permittivities in vacuum and in the gate dielectric, respectively. If this is not

specified, εox = ε0εSiO2 is taken.

The gradual-channel approximation, being introduced to derive closed-form equations, limits the validity

of the model description to the non-saturated condition. As Vds is increased to the saturation condition,

the so-called pinch-off region appears at drain side of the channel. However, it is difficult to obtain

information about the position where the gradual-channel approximation terminates and where the pinch-

off region starts. The Ids equation is extended to include the saturation condition by introducing a steep

increase of the surface potential in the pinch-off region, which is mainly controlled by the lateral electric

field instead of the vertical one. The modeling details are explained in the channel-length-modulation

section (section 10).

Specific features of LDMOS is caused by the resistive drift region. This affects on Ids as the resistance.

This is observed as the quasi-saturation behavior of the drain current, which is modeled in the resistance

section (section 14).


14


Table 3: HiSIM model parameters introduced in section 5 of this manual.

KAPPA dielectric constant of gate dielectric

15


6 Threshold Voltage Shift

Different from the drift approximation, the drift-diffusion approximation does not require a threshold

voltage parameter Vth for describing device performances. The MOSFET device parameters such as the

oxide thickness Tox and the substrate doping concentration NSUBC determine the complete MOSFET

behavior including the subthreshold characteristics automatically and consistently. The measured Vth is

influenced by various phenomena such as the short-channel effects, which cause a reduction of Vth for

short-channel transistors in comparison to long-channel transistors as shown in Fig. 9. This so-called Vth

roll-off is very much dependent on the technology applied for MOSFET fabrication. Therefore, HiSIM

can derive many detailed informations on the MOSFET fabrication technology, which are relevant for

modeling device characteristics, from the Vth changes (∆Vth) as a function of gate length (Lgate). The

modeled ∆Vth is incorporated in the φS iteration as can be seen in Eq. (14), and can be viewed as

consisting of two main effects or components:

(I) the short-channel effect: ∆Vth,SC

(II) the reverse-short-channel effect: ∆Vth,R and ∆Vth,P

The separation into these two components (∆Vth = ∆Vth,SC+∆Vth,R (or ∆Vth,P)) is schematically shown

in Fig. 9.

V th

Lgate

∆Vth

∆Vth

,R∆V

th,S

C

Fig. 9: Schematic plot of the separation of Vth into the contributions of the short-channel and the reverse-short-channel effect.

6.1 (I) Short-Channel Effects

As for the short-channel effects four important phenomena are observed: (i) reduction of Vth for reduced

Lgate, (ii) Vth dependence on Vds, (iii) reduction of the body effect, (iv) increase of the subthreshold swing,

where (iv) is often not obvious for the normal case of fabrication technologies. Recent advanced tech-

nologies utilize aggressive scaling, which induces observable subthreshold degradation. This is modeled

with the parameter PTHROU, introduced below in Eq. (34)).

All observed phenomena are caused by the lateral-electric-field contribution in the MOSFET channel,

which is important even at threshold condition with small Vds. Thus ∆Vth,SC can be written as a function

of the lateral electric field Ey by applying the Gauss law. A parabolic potential distribution along the

16


channel is approximated, which results in a position independent gradient of the lateral electric fielddEy

dy[6]

∆Vth,SC =εSi

CoxWd

dEy

dy(30)

where Wd is the depletion-layer thickness written as

Wd =

√2εSi(2ΦB − Vbs)

qNsub(31)

2ΦB =2β

ln(

Nsub

ni

)(32)

where ni is the intrinsic carrier density.dEy

dyis derived with model parameters in the form

dEy

dy=

2(VBI− 2Φ′

B)(Lgate −PARL2)2

(SC1 + SC2 · Vds · 1 + SC4 · (2ΦB − Vbs)+ SC3 · 2ΦB − Vbs

Lgate

)(33)

where

Φ′

B = ΦB + PTHROU ·(Φ

′′

B(Vgs)− ΦB

)(34)

and Φ′′

B is the surface potential calculated analytically by solving the Poisson equation under the diffusion

approximation

Φ′′

B(Vgs) = V ′G +

(const0Cox

β

2

)2

1−√√√√1−

4β(V ′G − Vbs)− 1

β2(

const0Cox

)2

(35)

const0 =

√2εSiqNsub

β(36)

VBI and PARL2 represent the built-in potential and the depletion width of the junction vertical to

the channel, respectively. V ′G and const0 were defined in Eqs. (14) and (25), respectively. The model

parameter SC1 determines the threshold voltage shift for small Vds and Vbs, and is expected to be unity.

If measured Vth is plotted as a function of Vds, it shows nearly a linear dependence. The gradient is

proportional to SC2. SC3 implements a correction of the charge-sheet approximation and is expected

to be small. Thus this parameter describes modification of the Vth on Vbs for inhomogeneous substrate

impurity profile. For LDMOS/HV-MOS, a new model parameter SC4 is introduced to model the modified

Vbs dependence, namely the increased Vbs dependence for low impurity concentrations. PTHROU

describes the increase of the subthreshold swing for short-channel transistors.

6.2 (II) Reverse-Short-Channel Effects

The reverse-short-channel effect is categorized into resulting from two physical MOSFET properties:

17


(i) Impurity concentration inhomogeneity in the direction vertical to the channel(vertical channel inhomogeneity)

(obvious in the retrograded implantation): ∆Vth,R

(ii) Impurity concentration inhomogeneity in the direction parallel to the channel(lateral channel inhomogeneity)

(obvious in the pocket implantation): ∆Vth,P

(i) Impurity concentration inhomogeneity in the direction vertical to the channel(Retrograded Implantation)

The model part described in section 4.2.(i) is to some extent (i. e. Eq. (39)) not included in HiSIM2,

because it is rarely necessary for fitting MOSFET technologies. Furthermore, the above model parameters

SC3 and SCP3 can be successfully used, if the inhomogeneity is not extremely large.

The substrate impurity pile-up of the retrograded profile at the surface near the source/drain contact is

a cause for reverse short channel effects [8]. The impurity profile Nsub(x) is modeled by a linear function

of the depth x to allow its easy extraction. With the depletion charge Qdep, the Vth shift in comparison

to a long-channel transistor is written [9, 10] as

∆Vth,R =Qdep

Cox− Qdep(long)

Cox(37)

Qdep = q

∫ Wd

0

Nsub(x)dx (38)

0.20µm 0.30µm 0.50µm 1.00µm

V th

(V)

φs – V bs ( V)

Vds = 0.1V−0.2

0

0.2

0.4

0.6

0.8

1

0 0.5 1 1.5 2

Lgate=0.15µm

Fig. 10: Simulated Vth-√

φS − Vbs characteris-tics. The gradient and the intersect are depen-dent on the Nsub(x) profile.

depth (µm)

Nsu

bx10

17 (

cm-3

)

channel surface

0 0.05 0.1

Lgate=0.2µm 0.3µm 0.5µm 1.0µm

0.15

8

6

4

2

0

Lgate=0.15µm

Fig. 11: Symbols are the impurity profiles usedfor the Vth simulation shown in Fig. 10. Linesare extracted profiles.

The impurity profiles are dependent on Lgate and are extracted from measured Vth-√

2ΦB − Vbs charac-

teristics as demonstrated in Fig. 10. Here 2ΦB is the surface potential at threshold condition. Since a

non-homogeneous impurity profile does not allow to describe Wd analytically, Eq. (38) has to be solved

numerically. The gradient of Nsub(x) and its intersect at x = 0 are determined to reproduce measured

Vth-√

φS − Vbs characteristics. Fig. 11 compares the extracted impurity profiles with the 2D process

18


simulation results [11]. Fig. 12 compares simulated and measured Vth values as a function of Lgate. The

integrated Qdep, represented by a polynomial function of Lgate, is implemented into the circuit-simulation

model to eliminate the integration procedure

Qdep = QDEPCC +QDEPCL

LQDEPCSgate

+

(QDEPBC +

QDEPBL

LQDEPBSgate

)√2ΦB − Vbs (39)

0

0.2

0.4

0.6

0.8

1.0

Vbs=0V

Vbs=−1.0V

Vbs=−2.0VV t

h (V

)

Lgate (µm)0.1 1 10

Vds=0.1V

Fig. 12: Comparison of measured Vth (solid symbols) with model results (solid lines).

QDEPCC, QDEPCL, QDEPCS, QDEPBC, QDEPBL, and QDEPBS are the final model param-

eters. The impurity concentration used for the surface-potential calculations is the value at the surface,

Nsub(0). The reason is that the inversion charge density Qi, which mostly determines the MOSFET

characteristics, extends only in a few nm into the vertical direction.

Although Eq. (39) is not implemented in the present version of HiSIM2, this could be easily done, if the

necessity should arise.

Fig. 13 shows the Vth dependence as a function of√

2ΦB − Vbs for two different impurity profiles along the

vertical direction. For cases where the inhomogeneity is large or where positive Vbs is applied, deviation

from the linearity of Vth as a function of√

2ΦB − Vbs is modeled with two fitting parameters BS1 and

BS2 as

QBmod =

√2q ·Nsub · εSi ·

(2ΦB − Vbs −

BS1BS2− Vbs

)(40)

where BS1 represents the strength of the deviation and BS2 is the starting value of Vbs where the

deviation becomes visible.

(ii) Impurity concentration inhomogeneity in the lateral direction parallel to the channel(Pocket Implantation)

The pocket-implant technology causes an inhomogeneity along the channel. Two obvious features are:

(1) the Vth increase starts already from relative long Lgate and (2) the short-channel effects such as the

Vds dependence on Vth appear also even for long-channel transistors [12]. This is modeled by developing

a new definition for the threshold voltage based on the idea that the threshold condition is determined

19


0 0.5 1 1.5 2

φs-Vbs V

-0.20

0.20.40.60.81.01.2

1.4

Thr

esho

ld V

olta

ge (

V)

retrograded

pile-up

( )

homogeneous

Fig. 13: Threshold voltage as a function of√

φS − Vbs for pile-up and retrograded impurity profiles inthe channel, where φS is fixed to 2φB. The deviation from linearity for small Vbs is modeled with theparameters BS1 and BS2.

by the inversion carrier densities in both the non-pocket region and in the pocket region [13] as shown in

Fig. 14. The gate voltage inducing a certain amount of total carrier density in the two regions is defined

as Vth. Two model parameters (LP: length of the pocket extension into the channel; NSUBP: peak of

the pocket impurity concentration) are introduced as shown in Fig. 15. The impurity concentration in

the substrate is distinguished with NSUBC from NSUBP. The final model equation requires an iteration

procedure for finding the surface potential value, which gives the determined threshold condition.

w/o pocketwith pocket

φ S (

V)

y (µm)

Source Drain

Leff

Fig. 14: Surface potential distribution along the channel simulated with a 2D simulator.

To eliminate this iteration for model application in circuit simulation, a simplification of the pocket-

implantation model is introduced, which nevertheless keeps the key features of the developed concept [14].

The resulting model equations for the Vth shift due to the pocket implant are:

20


∆Vth,P = (Vth,R − Vth0)εSi

CoxWd

dEy,P

dy(41)

Vth,R = VFBC + 2ΦB +QBmod

Cox+

1β

log(

Nsubb

NSUBC

)(42)

Vth0 = VFBC + 2ΦBC +

√2qNSUBCεSi(2ΦBC − Vbs)

Cox(43)

dEy,P

dy=

2(VBI− 2ΦB)LP2

(SCP1 + SCP2 · Vds + SCP3 · 2ΦB − Vbs

LP

)(44)

Nsubb = 2 ·NSUBP− (NSUBP−NSUBC) · Lgate

LP−NSUBC (45)

The parameters SCP1 - SCP3 describe the short-channel effect caused by the potential minimum at

the higher impurity concentration of the pocket. 2ΦBC is the potential giving threshold condition with

NSUBC and 2ΦB is the equivalent potential with Nsub

ΦBC =2β

ln(

NSUBC

ni

)(46)

ΦB =2β

ln(

Nsub

ni

)(47)

Nsub =NSUBC(Lgate − LP) + NSUBP · LP

Lgate(48)

As defined in Eq. (48), Nsub is replaced to the averaged impurity concentration in the channel and Nsubb

is introduced, beginning from channel lengths where pockets at source and drain start to overlap.

As Vds approaches zero, the Vth dependence on Vds deviates from linearity and Vth increases drastically

as shown schematically in Fig. 16. This is modeled with two model parameters SCP21 and SCP22 as

4

5

6

7

8

0.2 0.4 0.6 0.8

depth=30nm 60nm

Nsu

b [x

1017

cm-3

]

Position in the channel [µm]

NSUBP

Leff

NSUBC LP

Fig. 15: The dashed curves are simulated impurityprofiles by the 2D-process simulator TSUPREM atvarious depths. The extracted pocket profile withthe model is depicted by a solid line.

Vds

Vth

SCP21

Fig. 16: Threshold voltage as a function of Vds.The deviation from linearity for small Vds is mod-eled with parameters SCP21 and SCP22.

∆Vth,P = ∆Vth,P −SCP22

(SCP21 + Vds)2(49)

21


where SCP21 determines the Vds value at which Vth starts to deviate from linearity as a function of Vds.

The parameter SCP22 determines the gradient of this deviation.

target

Lgate[ m]µ

10.1

Vth

mV

[]

400

350

300

250

w/o SCE

300

320

280

260

240

220

Lgate[ m]µ10.1

Vth

mV

[]

target

with SCE

(a) (b)

Fig. 17: Comparison of measurements and pocket-implant model for Vth as a function of Lgate.Results (a) with and (b) without short-channel effects (SCE) are shown.

Vth,R and Vth0, defined in Eqs. (42) and (43), are the threshold voltages for the cases with and without

pocket-implant, respectively. The overlap start of source and drain pockets causes a steep increase of

Vth as a function of decreasing Lgate. This effect enables to extract LP from measurements. Fig. 17

compares the Vth-Lgate characteristics of the developed pocket-implant model with and without inclusion

of the short-channel effects (SCE). The steep increase at Lgate=0.1µm in Fig. 17a means the starting of

the pocket overlap, where LP=0.05µm.

In some cases the pocket profile cannot be described by the single linearly decreasing form, but pro-

vides extensive tails as schematically shown in Fig. 18. Therefore, two model parameters NPEXT and

LPEXT are introduced to model the pocket tails as

Nsub = Nsub +NPEXT−NSUBC(1xx + 1

LPEXT

)Lgate

(50)

where

xx = 0.5× Lgate − LP . (51)

NPEXT is the maximum concentration of the pocket tail and LPEXT describes the tail extension

characteristics. Usually strong pocket implantation induces a vertical impurity distribution at the same

time. For fitting the measured results in such cases it is recommended to use the parameter SCP3

together with parameters BS1 and BS2.


22


Pocket Tail

Nsu

b

Position in Channel

NSUBP

Leff

NSUBC LP

Fig. 18: Modeled pocket tail with NPEXT and LPEXT.

Table 4: HiSIM model parameters introduced in section 6 of this manual. ∗ indicates minor parameters.

VBI built-in potentialPARL2 depletion width of channel/contact junction

SC1 magnitude of short-channel effectSC2 Vds dependence of short-channel effect∗SC3 Vbs dependence of short-channel effect∗SC4 Vbs dependence of short-channel effect

∗PTHROU correction for subthreshold swingNSUBP maximum pocket concentration

LP pocket penetration length∗BS1 body-coefficient modification due to impurity profile∗BS2 body-coefficient modification due to impurity profileSCP1 magnitude of short-channel effect due to pocketSCP2 Vds dependence of short-channel due to pocket∗SCP3 Vbs dependence of short-channel effect due to pocket∗SCP21 short-channel-effect modification for small Vds

∗SCP22 short-channel-effect modification for small Vds

∗NPEXT maximum concentration of pocket tail∗LPEXT extension length of pocket tail

23


7 Depletion Effect of the Gate Poly-Si

Carrier depletion in the gate poly-Si occurs due to the relatively low impurity concentration of the poly-

Si in the region above the gate-oxide. Nevertheless, this concentration is usually much higher than the

impurity concentration in the substrate. Therefore, carrier depletion in the poly-Si near the gate-oxide

interface starts after the formation of the inversion layer in the substrate as shown in Fig. 19. For

modeling the gate poly-Si depletion a physical model parameter, namely the impurity concentration in

the gate poly-Si (Npg), is introduced. The Poisson equation has to be solved in the substrate and in the

gate poly-Si simultaneously by iteration [15], which results in

V ′G − φS − φSpg = −QSP

Cox=

εSiESi

Cox(52)

where ESi is the vertical electric field at the substrate surface. The electric field Epg in the poly-Si at the

gate oxide interface is written as

Epg = qNpgLD,pg

√2[

exp(−βφSpg) + βφSpg − 1

+np0,pg

pp0,pg

exp(βφSpg)− βφSpg − 1

] 12

(53)

0

0.2

0.4

0.6

0.8

1.0

1.2

−1 −0.5 0 0.5 1 1.5 2 2.5

φso

φspg : Npg = 6.0x1019 φspg : Npg = 3.0x1019

Vgs (V)

Pote

ntia

l (V

) φsoPoly-Si

Siφspg

Fig. 19: Simulated surface potential at the source side (φS0) as a function of Vgs. The poly-depletionpotential is also shown for two doping concentrations Npg in the poly-Si.

where LD,pg, np0,pg and pp0,pg are the Debye length, the intrinsic carrier concentration for electrons and

the intrinsic carrier concentration for holes in the poly-Si, respectively. A further reasonable approxima-

tion is that φSpg never enters the inversion region under normal operation conditions, and thus Eq. (53)

can be simplified as

Epg = qNpgLD,pg

√2(βφSpg − 1)

12 (54)

Eqs. (52) and (54) are solved iteratively under the boundary condition of ESi = Epg. Fig. 19 shows

calculation results of φSpg together with φS0 as a function of Vgs.

To eliminate the necessary iteration procedure for the circuit-simulation application, φSpg is further

approximate as a function of Vgs and Vds by the simple formula of Eq. (55), and is included in the ∆Vth

calculation as a potential drop of Vgs.

24


φSpg = PGD1(

1 +1

Lgate × 104

)PGD4

exp(

Vgs −PGD2−PGD3 · Vds

V

)(55)

In Eq. (55), PGD1 describes the strength of the poly-depletion, PGD2 represents the threshold voltage

of the poly-depletion, and PGD3 is introduced to take into account the weakening gate poly-Si depletion

for large Vds. The reason for adopting an exponential function for the Vgs dependence is the exponential

φSpg-Vgs characteristic obtained when solving Eqs. (52) and (54) iteratively. It has to be noticed, however,

that the function of Eq. (55) has to be smoothed so that φSpg does not exceed φS0 for very large Vgs. A

further parameter PGD4 has been introduced to represent the channel length dependence of the gate

poly-depletion effect. V in the exp term is introduced just to delete dimension.


Table 5: HiSIM model parameters introduced in section 7 of this manual. ∗ indicates a minor parameter.

PGD1 strength of poly depletionPGD2 threshold voltage of poly depletionPGD3 Vds dependence of poly depletion∗PGD4 Lgate dependence of poly depletion

25


8 Quantum-Mechanical Effects

The main quantum-mechanical phenomenon, which has to be included into a MOSFET model for circuit

simulation, is the repulsion of the channel’s carrier-density peak into the substrate away from the surface.

This can be described phenomenologically by an increased effective oxide thickness Tox. Two major

approximations are introduced to derive a simple set of equations for Tox: First, a triangular potential

perpendicular to the channel is approximated and second, carriers are assumed to occupy only the lowest

quantized energy level. The resulting effective oxide thickness Tox can be written as [16, 17]

Tox = TOX + ∆Tox

= TOX + Qealp

(Qb +

1132

Qi

)− 13

(56)

Qealp =(

48πmeq

εSi~2

)− 13

= 3.5× 10−10[C cm]13

The coefficient Qealp, originally calculated quantum mechanically under the above mentioned approxi-

mations, is used for fitting purposes. From measured Cgate-Vgs characteristics Qealp can be extracted

(e. g. Fig. 20). The extraction is performed at Vds = 0 and results in position independent values for Qb

and Qi. However, as can be seen from the above Tox in Eq. (56), Qb and Qi are required to calculate

Tox. On the other hand, the Qb and Qi calculations require the previous knowledge of Tox. Therefore,

the Tox extraction procedure has to be carried out iteratively. From the iteratively calculated ∆Tox-Vgs

characteristics, shown in Fig. 21, it is concluded that the ∆Tox dependence on Vgs can be described by

the simple equation

∆Tox = a(Vgs − Vth − b)2 + c (57)

where a, b, and c are fitting parameters and

Vth = 2ΦB + VFBC +Tox + ∆Tox

εoxqNsubWd (58)

Here the Vth calculation requires again the previous knowledge of ∆Tox. By substituting Eq. (58) into

Eq. (57), ∆Tox is obtained analytically after some simplifications

∆Tox = a (Vgs − Vth(Tox = Tox)− b′)2 + c′ (59)

Final equations implemented into HiSIM for the reproduction of quantum mechanical effects are:

Tox = TOX + ∆Tox (60)

∆Tox =QME1QME22 (Vgs − Vth(Tox = TOX)−QME2)2 + QME3 (61)

where QME1, QME2, and QME3 are the quantum-effect model parameters.


26


0-1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5

Cga

te (

µF/c

m2 )

Vgs (V)

1.4

1.21.00.80.60.40.2

Coxwithoutwith QE

measuredwith QE & PDE

Fig. 20: Comparison of measured C-V char-acteristics with simulation results for dif-ferent model complexities with and withoutquantum effect (QE) or poly-Si depletion ef-fect (PDE).

Vgs (V)

∆Tox

(nm

)

0

0.2

0.4

0.6

0.8

0 0.5 1.0 1.5 2.0 2.5

∆Tox (model)∆Tox (exact calculation)

Vth

Fig. 21: Calculated Tox increase by the quan-tum mechanical effect. The solid line showsmodel results with Eqs. (60) and (61). Sym-bols are exact calculation results by solv-ing the Poisson equation and the Schrodingerequation simultaneously.


QME1 Vgs dependenceQME2 Vgs dependenceQME3 minimum Tox modification

27


9 Mobility Model

The low-field mobility is described with the following expressions and includes the three independent

mechanisms of Coulomb, phonon and surface-roughness scattering [18]:

1µ0

=1

µCB+

1µPH

+1

µSR(62)

µCB(Coulomb) = MUECB0 + MUECB1Qi

q × 1011(63)

µPH(phonon) =Muephonon

EMUEPH0eff

(64)

µSR(surface roughness) =MUESR1

EMuesurfaceeff

(65)

where µPH(phonon) is temperature dependent as modeled in section 13.

100

200

300

Effective Electric Field, Eeff (V/cm)

Mob

ility

(cm

2 /V s)

1x106 2x1063x105 5x105

Lgate=1.5µm

Lgate=0.12µm -2

-0.3

Phonon Coulomb Surface Roughness

( . )Nsub × cm= -5 6 1017 3

( . )Nsub × cm= -1 08 1018 3

Fig. 22: Calculated mobility as a function of effective field for different MOSFET devices.

Here Eeff is the effective field normal to the surface. The field are written as

Eeff =1εSi

(Ndep ·Qb + NINV ·Qi) · f(φS) (66)

f(φS) =1

1 + (φSL − φS0) ·NINVD(67)

where Ndep considers the gate length dependence with two model parameters NDEPL and NDEPLP

as

Ndep = NDEPLNDEPLP

gate

NDEPL + LNDEPLPgate

(68)

The funtion f(φS) is introduced to reproduce the reduced resistance effect for small Vds with the model

parameter NINVD.

The mobility universality preserves following conditions [19, 20]

28


MUEPH0 ' 0.3 (69)

Muesurface = 2.0 (70)

NDEP = 1.0 (71)

NINV = 0.5 (72)

independent of technology variations, as illustrated in Fig. 22. However, these parameters can be used

for fitting purposes [21], if it is necessary.

Due to the carrier flow at increasing distance from the surface with reducing Lgate, the electric field

experienced by the carriers is different from the field in the long Lgate case. This results in a modification

of Muephonon, which is modeled as

Muephonon = MUEPH1×(

1 +MUEPHL

(Lgate × 104)MUEPLP

)(73)

The surface-roughness coefficient Muesurface is modeled to have a similar channel length dependence

written as

Muesurface = MUESR0×(

1 +MUESRL

(Lgate × 104)MUESLP

)(74)

because the same physical reasoning as for the Muephonon dependence on Lgate applies.

The high-field mobility is modeled as [22]

µ =µ0(

1 +(

µ0Ey

Vmax

)BB) 1

BB

(75)

where the maximum velocity Vmax is temperature dependent modeled, as described in section 13. BB

is usually fixed to 2 for electrons and 1 for holes, which preserves symmetry for device characteristics at

Vds = 0 even for odd numbers different from the argument given in [23]. Ey is derived from calculated φS

values. The maximum velocity Vmax should be the maximum electron-saturation velocity (' 1×107cm/s),

which is however exceeded at reduced Lgate. This phenomenon, called velocity overshoot, is included in

the mobility model in the following manner

Vmax = VMAX ·(

1 +VOVER

(Lgate × 104)VOVERP

)(76)


29



MUECB0 Coulomb scatteringMUECB1 Coulomb scatteringMUEPH0 phonon scatteringMUEPH1 phonon scattering∗MUEPHL length dependence of phonon mobility reduction∗MUEPLP length dependence of phonon mobility reductionMUESR0 surface-roughness scatteringMUESR1 surface-roughness scattering∗MUESRL length dependence of surface roughness mobility reduction∗MUESLP length dependence of surface roughness mobility reduction

NDEP depletion charge contribution on effective-electric field*NDEPL modification of depletion charge contribution for short-channel case

*NDEPLP modification of depletion charge contribution for short-channel caseNINV inversion charge contribution on effective-electric field

*NINVD reduced resistance effect for small Vds

BB high-field-mobility degradationVMAX maximum saturation velocityVOVER velocity overshoot effect

VOVERP Leff dependence of velocity overshoot

30


10 Channel-Length Modulation

The gradual-channel approximation is applied to derive analytical equations for describing device charac-

teristics. However, this approximation is not valid for large Vds causing the pinch-off phenomenon in the

channel. Without taking into account the pinch-off phenomenon, the calculated channel conductance gds

enters abruptly into the saturation condition. To include the pinch-off phenomenon in HiSIM, we apply

the conventional method of modeling the pinch-off region (∆L) separately from the rest of the channel

as depicted in Fig. 23 [24].

Gate

S0+Vds

S(∆L)

Drain

Gradual Channel Approx.

S0

φ

φφ

Qi0' y

Wd

∆L

y

x

Vds

Ey>Ex

SLφ

EC ED

Fig. 23: Schematic showing the correlation among physical quantities in the pinch-off region.

The position y = 0′ corresponds to the end point of the gradual-channel approximation, where the surface

potential is φSL. The length from y = 0′ to the drain contact is called ∆L. The surface potential at the

drain junction is referred to by φS(∆L). After integrating the Poisson equation in the ∆L region under

neglection of the vertical electric field Ex, we obtain [25]

∆L = εSiED − EC

qNsub + Qi/Wd(77)

where

E2D = E2

C +2qNsub

εSi(φS(∆L)− φSL) (78)

and EC is the electric field at y = 0′.

The validity of the gradual-channel approximation at y = 0′ is exploited to obtain

EC =Idd

β(Leff −∆L)Qi(79)

Though EC is dependent on ∆L, this dependence may be neglected to simplify Eq. (79) as

EC =Idd

βLeffQi(80)

For simple parameter extraction Qi at the source side is used in Eq. (80). The final potential value

at the end of the channel (φS(∆L)) lies between φSL and φS0 + Vds. The exact value is dependent on

31


the junction profile between the channel and the drain contact. This dependence is modeled with the

parameter CLM1 as

φS(∆L) = (1−CLM1) · φSL + CLM1 · (φS0 + Vds) (81)

where CLM1 can be interpreted to represent the hardness of the junction and must be in the range

0 ≤ CLM1 ≤ 1. Here CLM1 = 1 means that the contact profile is abrupt and the complete potential

increase occurs in the ∆L region, whereas CLM1 = 0 corresponds to the opposite condition and there

is no potential increase in the ∆L region.

Starting from the HiSIM2.2.0 model version, ∆L is calculated by solving Eqs. (77), (78) and (79), si-

multaneously. The dependence of Ec on ∆L, which becomes more significant for sub-100nm devices, is

consistently included in the calculation. The equation describing ∆L is

∆L2+1

Leff

(2

Idd

βQiz+2

Nsub

εSi(φS(∆L)−φSL)z2+E0z

2)∆L−

(2Nsub

εSi(φS(∆L)−φSL)z2+E0z

2)

= 0 (82)

by taking into account only up to quadratic terms. The final ∆L is derived as

∆L =12

[− 1

Leff

(2

Idd

βQiz + 2

Nsub

εSi(φs(∆L)− φSL)z2 + E0z

2

)

+

√1

L2eff

(2

Idd

βQiz + 2

Nsub

εSi(φs(∆L)− φSL)z2 + E0z2

)2

+ 4(

2Nsub

εSi(φs(∆L)− φSL)z2 + E0z2

)](83)

where E0 is fixed to 105 and

z =εSi

CLM2 ·Qb + CLM3 ·Qi(84)

Two model parameters CLM2 and CLM3 are introduced to consider the uncertainty of Qi in the pinch-

off region and to counterbalance the two contributions from Qb (= qNsubWd) and Qi. It has to be notified

that ∆L is equal to zero, when CLM1=0.

Though ∆L is determined mostly by φS(∆L), the combination between CLM2 and CLM3 influences

the lateral-field-induced capacitance CQy described in section 15.

For the pocket implantation the lateral field increase is observed even for long-channel transistors. The

effect is modeled by the threshold voltage shift. However, the degradation of the channel conductance

under the saturation condition is much stronger than that described by the threshold voltage shift alone.

This additional pocket effect is modeled as

∆L = ∆L(1 + CLM6 · (Lgate × 104)CLM5

)(85)

It can be happen that Leff − ∆L becomes negative, if extracted CLM5 and CLM6 values are out of

acceptable ranges. In this case HiSIM gives ”warning” and fixes Leff −∆L to 1nm.


32



CLM1 hardness coefficient of channel/contact junctionCLM2 coefficient for QB contributionCLM3 coefficient for QI contribution*CLM5 effect of pocket implantation*CLM6 effect of pocket implantation

33


11 Narrow-Channel Effects

11.1 Threshold Voltage Modification

The shallow-trench-isolation technology induces a Vth reduction for reduced channel width (Wgate). This

phenomenon is modeled under inclusion of the edge-fringing capacitances Cef at the edge of the trench [26]

as

∆Vth,W =(

1Cox

− 1Cox + 2Cef/(LeffWeff)

)qNsubWd +

WVTH0Wgate × 104

(86)

where WVTH0 is the parameter for including the basic width dependence and

Cef =2εoxπ

Leff ln(

2Tfox

Tox

)=

WFC2

Leff (87)

Here, Tfox is the thickness of the oxide at the trench edge, and WFC is the model parameter for including

the edge-fringing-capacitance effects. The final ∆Vth of Eq. (14), under inclusion of the shallow-trench-

isolation effects, becomes:

∆Vth = ∆Vth,SC + ∆Vth,R + ∆Vth,P + ∆Vth,W − φSpg (88)

Fig. 24 shows the schematic Vth dependence on Wgate for two gate lengths, Lgate. Enhancement of the Vth

reduction with decreasing Wgate is often measured when Lgate is also small. This effect becomes obvious

for the pocket technology and is modeled by a modification of the pocket impurity concentration as

Nsubp = NSUBP×(

1 +NSUBP0

(Wgate × 104)NSUBWP

)(89)

The width dependence of the substrate impurity concentration NSUBC is also considered as

NSUBC = NSUBC ·(

1 +NSUBCW

(Wgate · 104)NSUBCWP

)(90)

Vth

Wgate

short-channel

long-channel

Fig. 24: Schematic of the Vth characteristic as a function of the gate width Wgate for two different gatelengths, Lgate.

34


11.2 Mobility Change

Fig. 25 shows a schematic of the measured saturation current as a function of Wgate. It is known that

the trench isolation induces mechanical stress in the channel, which results in a degradation of the

mobility [27], and causes a reduction of Ids,sat with reduced Wgate as indicated by curve C1. This effect

is modeled by a decreasing phonon mobility with two model parameters MUEPHW and MUEPWP

as

Muephonon = Muephonon ×(

1 +MUEPHW

(Wgate × 104)MUEPWP

)(91)

However, the Ids-Wgate characteristic does not show monotonous decrease but starts to increase for

narrower Wgate as denoted by curve C2. This effect is modeled as a change of the surface-roughness

contribution caused by a carrier flow in increasing distance from the surface as

Muesurface = Muesurface ×(

1 +MUESRW

(Wgate × 104)MUESWP

)(92)

Wgate

Nor

mal

ized

Ids

,sat

short-channel

long-channelC1

C2

Fig. 25: Schematic of the normalized saturation current Ids,sat as a function of the gate width Wgate fortwo different gate lengths Lgate.

11.3 Transistor Leakage due to Shallow Trench Isolation (STI): Hump in Ids

The shallow trench isolation induces also an undesired hump in the subthreshold region of the Ids-Vgs

characteristics. This is due to an increased electric field at the edge of the trench. At this trench edge

the impurity concentration as well as the oxide thickness are different from the MOSFET middle position

along the width direction. Therefore, the surface potential values are expected to be different at the

trench edge and are found to cause a Vth reduction there. Thus a MOSFET leakage current occurs at

these edges, which is smaller than the main MOSFET current, and only important for modeling of the

subthreshold characteristics of the MOSFET. The surface potential of the leakage regions at the trench

edges can be derived analytically as [28]

φS,STI = V ′gs,STI +

εSiQN,STI

C ′ 2ox

[1−

√1 +

2C ′ 2ox

εSiQN,STI

(V ′

gs,STI − Vbs −1β

)](93)

35


where

QN,STI = q ·NSTI (94)

V ′gs,STI = Vgs −VFBC + VthSTI + ∆Vth,SCSTI (95)

where

VthSTI = VTHSTI−VDSTI · Vds (96)

and

∆Vth,SCSTI =εSi

CoxWd,STI

dEy

dy(97)

The threshold voltage for the STI effect VTHSTI includes features of STI such as NSTI which are

diferent from the substrate. The depletion-layer thickness Wd,STI is written as

Wd,STI =

√2εSi(2ΦB,STI − Vbs)

qNSTI. (98)

dEy

dyis described with model parameters in the same form as in section 6.1 on short-channel effects

dEy

dy=

2(VBI− 2ΦB,STI)(Lgate,sm −PARL2)2

(SCSTI1 + SCSTI2 · Vds) (99)

where

Lgate,sm = Lgate +WL1

wlWL1P(100)

wl = (Wgate × 104)× (Lgate × 104) (101)

The modeling of the transistor leakage for STI technologies is based on the idea that the current in

the subthreshold region is governed only by the diffusion term. The carrier concentration Qi,STI is

calculated analytically by the Poisson equation in the form shown in Eq. (12) with the substrate-impurity

concentration NSTI different from NSUBC and NSUBP. The final leakage current equation is written

as

Ids,STI = 2WSTI

Leff −∆Lµ

Qi,STI

β

[1− exp(−βVds)

](102)

where WSTI determines the width of the high-field region. The gate length dependence of WSTI is included

as

WSTI = WSTI(

1 +WSTIL

(Lgate,sm × 104)WSTILP

)(1 +

WSTIW(Wgate,sm × 104)WSTIWP

)(103)

Calculated Ids,STI is compared in Fig. 26 with measurements.

36


I ds

Vgs

[A

]

[V]

10 -3

10 -5

10 -7

10-11

10 -9

10-13

-0.5 0.5 1.0 1.50 2.010-15

measurementmeasurementsimulationsimulation

Vbs = 0.0 → −1.5VVds = 1.5V

analytical (diffusion)

Fig. 26: Comparison of measured Ids-Vgs (solid circles) and simulated results (lines). The simulationaccounts only for the leakage at the transistor edges.

11.4 Small Geometry

Small size devices do not show the same scaling characteristic as long-channel or wide-channel devices,

but rather deviate significantly. The reason is mainly due to the resolution inaccuracy of the lithography.

The small geometry effects are modeled first as the threshold voltage shift

∆Vth = ∆Vth,SC + ∆Vth,R + ∆Vth,P + ∆Vth,W + ∆Vth,sm − φSpg (104)

where

∆Vth,sm =WL2

wlWL2P(105)

The mobility modification due to the small device geometry is also modeled in the phonon scattering as

Muephonon = Muephonon ×(

1 +MUEPHSwlMUEPSP

)(106)

Vmax = Vmax ·(

1 +VOVERS

wlVOVERSP

)(107)


37



WFC threshold voltage change due to capacitance change∗WVTH0 threshold voltage shiftNSUBC substrate-impurity concentration

∗NSUBCW width dependence of substrate-impurity concentration∗NSUBCWP width dependence of substrate-impurity concentration∗NSUBP0 modification of pocket concentration for narrow width∗NSUBWP modification of pocket concentration for narrow width∗MUEPHW phonon related mobility reduction∗MUEPWP phonon related mobility reduction∗MUESRW change of surface roughness related mobility∗MUESWP change of surface roughness related mobility∗VTHSTI threshold voltage shift due to STI∗VDSTI Vds dependence of threshold voltage shift due to STI*SCSTI1 the same effect as SC1 but at STI edge*SCSTI2 the same effect as SC2 but at STI edgeSCSTI3 no more usedNSTI substrate-impurity concentration at the STI edgeWSTI width of the high-field region at STI edge

*WSTIL channel-length dependence of WSTI*WSTILP channel-length dependence of WSTI*WSTIW channel-width dependence of WSTI

*WSTIWP channel-width dependence of WSTIWL1 threshold volatge shift of STI leakage due to small size effect

WL1P threshold voltage shift of STI leakage due to small size effectWL2 threshold volatge shift due to small size effect

WL2P threshold voltage shift due to small size effect∗MUEPHS mobility modification due to small size∗MUEPSP mobility modification due to small size∗VOVERS modification of maximum velocity due to small size∗VOVERSP modification of maximum velocity due to small size

38


12 Effects of the Source/Drain Diffusion Length for ShallowTrench Isolation (STI) Technologies

The diffusion length, Lod between MOSFET gate and STI edge affects the MOSFET characteristics.

The influence is observed mainly in Vth and in the saturation current. The Vth change is attributed to a

change of the pocket impurity concentration and modeled as

Nsubsti =1 + T1 · T21 + T1 · T3

(108)

where

T1 =1

1 + NSUBPSTI2

T2 =NSUBPSTI1

Lod half

NSUBPSTI3

T3 =NSUBPSTI1

Lod half ref

NSUBPSTI3

(109)

which is used to modify the pocket concentration Nsubp as

Nsubp = Nsubp ×Nsubsti. (110)

The saturation-current change is attributed to a change of the mobility and modeled as

Muesti =1 + T1 · T21 + T1 · T3

(111)

where

T1 =1

1 + MUESTI2

T2 =MUESTI1

Lod half

MUESTI3

T3 =MUESTI1Lod half eff

MUESTI3

(112)

which is used to modify the phonon mobility parameter Muephonon as

Muephonon = Muephonon ×Muesti (113)

where Lod half and Lod half eff are determined in the same way as BSIM4.6.0 with model parameters

SAREF and SBREF and instance parameters SA, SB, and SD.


39


Table 10: HiSIM model parameters introduced in section 12 of this manual. # indicates instance param-eters.

NSUBPSTI1 pocket concentration change due to diffusion-region length between gate and STINSUBPSTI2 pocket concentration change due to diffusion-region length between gate and STINSUBPSTI3 pocket concentration change due to diffusion-region length between gate and STIMUESTI1 mobility change due to diffusion-region length between gate and STIMUESTI2 mobility change due to diffusion-region length between gate and STIMUESTI3 mobility change due to diffusion-region length between gate and STISAREF length of diffusion between gate and STISBREF length of diffusion between gate and STI

#SA length of diffusion between gate and STI#SB length of diffusion between gate and STI#SD length of diffusion between gate and gate

40


13 Temperature Dependences

If TEMP is treated as a model parameter, temperature T is determined as

T = TEMP + DTEMP (114)

where DTEMP is the temperature increase by self-heating. Whereas if TEMP is treated as an instance

parameter, T is determined as

T = TEMP (115)

The temperature dependence is included automatically in the surface potentials through β, which is

the inverse of the thermal voltage. Additionally the bandgap, the intrinsic carrier concentration, the

carrier mobility, and the carrier saturation velocity are also temperature dependent. The temperature

dependence of the bandgap determines the temperature dependence of Vth [29] and is modeled as

Eg = EG0−BGTMP1 · (T −TNOM)−BGTMP2 · (T −TNOM)2 (116)

where T is the given temperature. The temperature dependence of the intrinsic carrier concentration is

given by

ni = ni0 · T32 · exp

(−Eg

2qβ

)(117)

The temperature dependence of the mobility and the temperature dependence of the saturation velocity

have a major influence on the temperature dependence of the Ids-Vds characteristics under the on-current

condition. They are modeled as [22]:

µPH(phonon) =Muephonon

(T/TNOM)MUETMP × EMUEPH0eff

(118)

Vmax =VMAX

1.8 + 0.4(T/TNOM) + 0.1(T/TNOM)2 −VTMP× (1− T/TNOM)(119)

The temperature dependence of the gate current is modeled by modifying the bandgap specific for the

gate current as

Egp = Eg0 + EGIG + IGTEMP2(

1T− 1

TNOM

)+ IGTEMP3

(1

T 2− 1

TNOM2

)(120)

In addition to the temperature dependence of the physical device parameters, resistances include the

temperature dependence.

Rd0,temp = RDTEMP1 · (T −TNOM) + RDTEMP2 · (T −TNOM)2 (121)

Rdvd,temp = RDVDTEMP1 · (TEMP−TNOM) + RDVDTEMP2 · (TEMP2 −TNOM2) (122)


41


Table 11: HiSIM model parameters introduced in section 13 of this manual. ∗ indicates minor parameters.# indicates an instance parameter.

EG0 bandgapBGTMP1 temperature dependence of bandgapBGTMP2 temperature dependence of bandgapMUETMP temperature dependence of phonon scattering

TNOM temperature selected as nominal temperature value∗VTMP temperature dependence of the saturation velocityEGIG bandgap of gate current

IGTEMP2 temperature dependence of gate currentIGTEMP3 temperature dependence of gate currentRDTEMP1 temperature dependence of resistanceRDTEMP2 temperature dependence of resistance

RDVDTEMP1 temperature dependence of resistanceRDVDTEMP2 temperature dependence of resistance

TEMP given temperature#TEMP given also as an instance parameter

#DTEMP additional temperature increase

42


14 Resistances

Here the resistance model is described for the LDMOS case. For the symmetrical HVMOS case, the

resistance at the source side is modeled with the same equations for the drain side without the Vds

dependence.

The source and the drain resistances Rs and Rd are considered by voltage drops on each terminal as:

Vgs,eff = Vgs − Ids ·Rs (123)

Vds,eff = Vds − Ids · (Rs + Rdrift) (124)

Vbs,eff = Vbs − Ids ·Rs (125)

where

Rs =RSWeff

+ NRS ·RSH (126)

Rdrift = (Rd + Vds ·RDVD)(

1 + RDVG11− RDVG11RDVG12

· Vgs

)· (1− Vbs ·RDVB) (127)

and

Rd =Rd0

Weff

(1 +

RDS(Wgate · 104 × Lgate · 104)RDSP

)+ RSH ·NRD (128)

Rd0 = (RD + Rd0,temp) f1 · f2 (129)

RDVD =RDVD + Rdvd,temp

Weff· exp

(−RDVDL× (Lgate · 104)RDVDLP

)·(

1 +RDVDS

(Wgate · 104 × Lgate · 104)RDVDSP

)· f1 · f2 · f3 (130)

f1(Ldrift1) =LDRIFT1

1µm·RDSLP1 + RDICT1 (131)

f2(Ldrift2) =LDRIFT2

1µm·RDSLP2 + RDICT2 (132)

f3(Lover) = 1 + RDOV11− RDOV11RDOV12

· LOVERLD1µm

(133)

NRS and NRD are instance parameters describing the number of squares of the source and drain

diffusions, and RSH is its the sheet resistance of the square. The first terms of the right hand side of

Eq. (126) and Eq. (128) consider the resistances in the LDD region and the drift region, and the second

terms are the those in the diffusion regions, which are layout dependent. LDRIFT1 and LDRIFT2

are model parameters denoting lengths of different parts of the drift region. The source resistance in the

LDMOS case does not consider a drift region and has therefore no drift length parameters. Functions f1,

f2, and f3 describe the scalability of the resistance.

The voltage drops are calculated iteratively for given voltages to keep consistency among all device

performances. However, Rs and Rdrift can be also treated as extrinsic resistances, and can be included

in the equivalent circuit. Thus, the parasitic source and drain resistances, Rs and Rdrift, can be included

by two optional approaches. The first approach is to include them as external resistances, so that the

circuit simulator generates nodes and finds the solution with the source/drain resistance iteratively (Flag:

43


CORSRD=-1). The second approach is to include them as internal resistances of HiSIM, so that HiSIM

solves iteratively (Flag: CORSRD=1). Thus Flag CORSRD is provided for the selection of one of

the possible approaches. CORSRD = 0, 1, 2, 3, -1 means ”no resistance”, ”internal”, ”analytical”,

”internal + analytical”, and ”external” source/drain resistances, respectively. Options to be selected by

Flag CORSRD are summarized in Fig. 27.

ds

ds

ds

Circuit simulator generates nodes for RS and RD

VgseffVdseffVbseff

no

no

yes

yes

CORSRD =1 or 3

CORSRD =-1

CORSRD =0

HiSIM iteration

yes

no

yesIds= Idso / (1+ Idso (Rd/Vds)

CORSRD =2 or 3no

Vgseff= Vgs – I xRsVdseff= Vds – I x(Rs+ Rdrift )Vbseff= Vbs – I xRs

Vgseff=VgsVdseff=VdsVbseff=Vbs

Surface-Potential CalculationDevice-Characteristic Calculation

Fig. 27: Model options provided in HiSIM-LDMOS/HV for the resistance models, which are selected byFlag CORSRD.

CORSRD=2 is originally introduced to avoid simulation time penalty with an analytical description of

the resistance effect as

Ids =Ids0

1 + Ids0RdVds

(134)

where Ids0 is the drain current without the resistance effect and

Rd =1

Weff

(R′

d · V RD21ds + Vbs ·RD22

)(135)

The strength of the resistance R′d includes parameters introduced to consider the resistance reduction

due to the current flow in the drift region. Further model parameters are introduced to include the size

dependence of the resistance as

R′d = RD23′ (136)

44


where

RD23′ = RD23 · exp(−RD23L× (Lgate · 104)RD23LP

)(1 +

RD23S(Wgate · 104 × Lgate · 104)RD23SP

)(137)

For large Vgs, it happens that the resistance effect is too strong with the parameter fitted to the whole

Vgs regime. For this case the Vgs dependence has to be included with further model parameters. The

RD23′ is modified

R′d = RD24 (Vgs −RD25) (138)

where R′d itself is restricted by two boundaries with the lower boundary defined to be RD23′ and the

upper boundary to be multiplied with (1 + RD20) as

RD23′ ≤ R′d ≤ RD23′(1 + RD20) (139)

If RD20 = 0, R′d reduces to RD23′. For the LDMOS case RD21 is fixed to be unity. Here it has to be

noticed that this resistance affects only on the drain current, and capacitances are not influence.

An accurate approach to consider the resistance effect is to treat with internal node (CORSRD=1).

However, in case if it is necessary, both resistance models (internal-node approach and anlytical approach)

can be applied with CORSRD=3.

The approach with external source/drain resistances (CORSRD=-1) leads to shorter simulation time

for circuits with small to medium transistor numbers, while the approach with internal source/drain

resistances leads to shorter simulation times for circuits with very large transistor numbers. The transistor

number, for which both approaches result in approximately equal simulation times (the switching point

for the choice between the 2 approximations) is normally between 10000 and 50000 transistors.

The gate resistance becomes large as the gate width becomes large, which is the case for many RF circuits.

The equation for the gate-resistance calculation is taken from the BSIM4 [30] description as

Rg =RSHG ·

(XGW + Weff

3·NGCON

)NGCON · (Ldrawn −XGL) ·NF

(140)

where RSHG is the gate sheet resistance, and others are instance parameters dependent on the layout.

The flag CORG is provided for the inclusion of gate resistance. CORG = 0,1 means ”no”, ”external”

gate resistance, respectively.

Model parameters for the same substrate resistance network as BSIM4 (RBPB, RBPD, RBPS,

RBDB, RBSB) are included in the model parameter list, which are also treated as instance parameters.

Here summarizes the selection of the resistance model:

CORSRD = 0 : no resistance

CORSRD = −1 : solved by circuit siumlator with external nodes

All model parameters included in Eq. (123)–Eq. (133) are used.

Model parameters are:

RS, NRS, RSH

RDVG11, RDVG12, RDVB, RDS, RDSP, NRD

45


RD, RDVD, RDVDL, RDVDLP, RDVDS, RDVDSP

RDSLP1, RDICT1, RDSLP2, RDICT2, RDOV11, RDOV12

CORSRD = 1 : solved the same equations as CORSRD = −1 with internal nodes iteratively

CORSRD = 2 : solved with the analytical equations of Eq. (134)–Eq. (139)

Model parameters are:

RD21, RD22, RD23, RD23L, RD23LP

RD23S, RD23SP, RD24, RD25, RD20

CORSRD = 3 : Both CORSRD = 1 and CORSRD = 2 are considered.

At the starting of the parameter extraction, following model parameters are suggested to set to zero:

RDVG11, RDVB, RDVD

RDTEMP1, RDTEMP2, RDVDTEMP1, RDVDTEMP2

The above condition refers to the bias independent resistance.


46


Table 12: HiSIM model parameters introduced in section 14 of this manual. # indicates instance param-eters. indicates minor parameters.

RS source-contact resistance of LDD regionRD drain-contact resistance of LDD regionRSH source/drain sheet resistance of diffusion region

RSHG gate sheet resistanceRBPB substrate resistance networkRBPD substrate resistance networkRBPS substrate resistance networkRBDB substrate resistance networkRBSB substrate resistance network#NRS number of source squares#NRD number of drain squares#XGW distance from the gate contact to the channel edge#XGL offset of the gate length#NF number of fingers

#NGCON number of gate contacts*RDVG11 Vgs dependence of RD for CORSRD=1,3*RDVG12 Vgs dependence of RD for CORSRD=1,3

RDVD Vds dependence of RD for CORSRD=1,3RDVB Vbs dependence of RD for CORSRD=1,3*RDS small size dependence of RD for CORSRD=1,3

*RDSP small size depenence of RD for CORSRD=1,3*RDVDL Lgate dependence of RD for CORSRD=1,3

*RDVDLP Lgate dependence of RD for CORSRD=1,3*RDVDS small size dependence of RD for CORSRD=1,3

*RDVDSP small size dependence of RD for CORSRD=1,3RDOV11 Lover dependence of resistance for CORSRD=1,3RDOV12 Lover dependence of resistance for CORSRD=1,3RDSLP1 Ldrift1 dependence of resistances for CORSRD=1,3RDICT1 Ldrift1 dependence of resistances for CORSRD=1,3RDSLP2 Ldrift2 dependence of resistances for CORSRD=1,3RDICT2 Ldrift2 dependence of resistances for CORSRD=1,3RD20 RD23 boundary for CORSRD=2,3RD21 Vds dependence of RD for CORSRD=2,3RD22 Vbs dependence of RD for CORSRD=2,3RD23 modification of RD for CORSRD=2,3

*RD23L Lgate dependence of RD21 boundary for CORSRD=2,3*RD23LP Lgate dependence of RD21 boundary for CORSRD=2,3*RD23S small size dependence of RD21 for CORSRD=2,3

*RD23SP small size dependence of RD21 for CORSRD=2,3*RD24 Vgs dependence of RD for CORSRD=2,3*RD25 Vgs dependence of RD for CORSRD=2,3

47


15 Capacitances

15.1 Intrinsic Capacitances

The intrinsic capacitances are derivatives of the node charges determined as

Cjk = δ∂Qj

∂Vk(141)

δ = −1 for j 6= k

δ = 1 for j = k

HiSIM uses analytical solutions for all 9 independent intrinsic capacitances, derived from the charges

given in Eqs. (7) – (11) as explicit functions of the surface potentials. Therefore, there are no extra model

parameters for the intrinsic capacitances.

The lateral electric field along the channel induces a capacitance CQywhich significantly affects the gate

capacitance in saturation [31]. The induced charge associated with CQy is described with the surface

potential values as

Qy = εSiWeff ·NFWd

(φS0 + Vds − φS(∆L)

XQY

)+

XQY1

LXQY2gate

Vbs (142)

introducing XQY, a parameter determining the maximum field at the channel/drain junction indepen-

dent of Lgate. For XQY=0 the charge Qy is fixed to zero. To compensate the enhanced short-channel

effect, determined by the current characteristics, two model parameters XQY1 and XQY2 are in-

troduced. Under the saturation condition, CQytogether with the overlap capacitance dominates the

gate-drain capacitance Cgd. This effect is more visibly observed as the gate-length reduces. Therefore,

in the Cgd modeling, CQyis added to the conventional components as depicted in Fig. 28 and replaces

the so-called inner-fringing field effects which are conventionally applied [32]. To activate Qy the model

parameter CLM1 must be smaller than unity.

Cov CfringCint CQy

gate

source drain

inversionlayer

saturationregion

∆L

Fig. 28: Modeling of the gate-drain capacitance with CQyadded to the conventional components.

15.2 Overlap Capacitances

The overlap charge at the drain side is written as

48


Qgod

Weff ·NF · Cox=∫ LOVERLD

0

(Vgs − φS)dy (143)

Thus the surface-potential distribution along the overlap region determines the charge and the capaci-

tance. The potential increase of φS(y) from φS(∆L) to φS0 + Vds is modeled by considering the lateral

impurity-profile gradient of the drain contact [25]. However, the influence of the gradient is negligible,

and only the surface potential change as a function of applied voltage is considered here.

The overlap capacitance includes three options as summarized in Fig. 29. Here two bias dependent models

are provided: One considers the surface potential change as a function of Vgs and the other calculates

with a simple Vgs dependenc.

surface -potential-based Cov

simplified Vgs dependent Cov

COOVLP=0yes

no

constant Covno

NOVER=0yes

Fig. 29: Model options of the overlap capacitance are summarized.

i) Surface-Potential-Based Model

The description is described for the drain side. For the source side the same calculation is performed

with Vds=0. The calculation of the surface potential in the drain contact region is done for all possible

conditions, from the inversion condition to the accumulation condition. The surface potential φS is

calculated in the same manner as in the channel region, and only the polarity is inverted from the

channel. The final overlap charge equation is written with the calculated φS

a) under the depletion and the accumulation conditions

Qover = Weff ·NF · LOVERLD

(√2εSiqNOVER

β

√β(φS + Vds)− 1

)(144)

b) under the inversion condition

Qover = Weff ·NF · LOVERLD · Cox(Vgs −VFBOVER− φS) (145)

where LOVERLD is the length of the overlap region of the gate over drain, NOVER is the impurity

concentration in the drain contact region, and VFBOVER is the flat-band voltage in the overlap region.

This model is selected, if NOVER is not equal to zero.

A smooting function is introduced with a model parameter QOVSM (previous RD26) to achieve smooth

transisiton between the depletion region and the inversion region of the overlap charge.

ii) Simplified Bias-Dependent Model

49


If LOVER > 0 and the flag COOVLP = 1, the overlap gate charge at the source side is modeled as

Qgos

Weff ·NF · Cox= Vgs · LOVER−OVSLP · (1.2− (φS0 − Vbs)) · (OVMAG + Vgs) (146)

If NOVER is equal to zero, the overlap charge at the drain is also calculated with the simplified equation

as

Qgod = Weff ·NF · Cox [(Vgs − Vds)LOVERLD−OVSLP · (1.2− (φSL − Vbs)) · (OVMAG + Vgs)]

(147)

The overlap capacitance at the source side is calculated by differentiating Qgos. Whereas the overlap

capacitances at the drain side is calculated by differentiating either Qgod or Qover of the overlap charge

equations.

As a summary these bias-dependent overlap-capacitance models can be selected using the model flag

COOVLP = 1, and require OVSLP and OVMAG or NOVER and VFBOVER in addition as

model parameters. For further model adjustments LOVER (overlap length) is used.

The default overlap capacitance flag (COOVLP = 0) calculates bias-independent drain and source

overlap capacitances. User-defined values can be specified using the input parameters CGDO and

CGSO. If these values are not specified, the overlap capacitances are calculated using

Cov = − εoxTOX

LOVER ·Weff ·NF (148)

The gate-to-bulk overlap capacitance Cgbo loc is calculated only with a user-defined value CGBO using

Cgbo loc = −CGBO · Lgate (149)

independent of the model flag COOVLP.

15.3 Extrinsic Capacitances

The outer fringing capacitance is modeled as [33]

Cf =εoxπ/2

Wgate ·NF · ln(

1 +TPOLY

Tox

)(150)

where TPOLY is the gate-poly thickness. This capacitance is bias independent.


50



XQY distance from drain junction to maximum electric field point*XQY1 Vbs dependence of Qy

*XQY2 Lgate dependence of Qy

VFBOVER flat-band voltage in overlap region*QOVSM =RD26: smooting Qover at depletion/inversion transitionOVSLP coefficient for overlap capacitanceOVMAG coefficient for overlap capacitanceCGSO gate-to-source overlap capacitanceCGDO gate-to-drain overlap capacitanceCGBO gate-to-bulk overlap capacitanceTPOLY height of the gate poly-Si

51


16 Leakage Currents

16.1 Substrate Current

The substrate current Isub is generated by impact ionization in the depletion region at the drain junction

(see Fig. 30). Thus Isub is represented by

Isub = αIdsδL (151)

where δL is the length where the impact ionization occurs. This δL region is not necessarily restricted

to the channel, namely to the same ∆L determined in the channel-length-modulation modeling, but can

extend into the drain region. The coefficient α is the ionization coefficient. α is written as a function of

the lateral electric field Ey with fitting parameters C1 and C2

α = C1 exp(−C2

Ey

)(152)

Since α is a function of the electric field, and the field is dependent on the position in the pinch-off region,

Eq. (151) has to be integrated along the pinch-off region and beyond

Isub =∫ δL

0

IdsC1 exp(−C2

Ey

)dy. (153)

A

B C

D

y

Drain

Gate

Ey(0)

L

Ey(y)

tox

Xj

0

Ex

Fig. 30: Schematic of the high field region.

After some simplification we derive the well-known equation [34]

Isub =C1

C2

(φ(y)− φ(0)

)Ids exp

(− λC2

φ(y)− φ(0)

)(154)

where

λ2 =εSiXjTox

εox(155)

and Xj is the junction depth.

The basic equation of Eq. (154) is modified so that measurements for all device sizes can be reproduced.

Isub = Xsub1 · Psisubsat · Ids · exp(− Xsub2

Psisubsat

)(156)

where

52


Xsub1 = SUB1 ·

(1 +

SUB1LLSUB1LP

gate

)(157)

Xsub2 = SUB2 ·(

1 +SUB2L

Lgate

)(158)

Psisubsat = SVDS · Vds + φS0 −Lgate · Psislsat

Xgate + Lgate(159)

Xgate = SLG ·

(1 +

SLGLLSLGLP

gate

)(160)

Psislsat = Vg2 +q · εSi ·Nsub

C2ox

·

1−

√1 +

2C2ox

q · εSi ·Nsub·(

Vg2 −1β−Xvbs · Vbs

)(161)

Xvbs = SVBS ·

(1 +

SVBSLLSVBSLP

gate

)(162)

Vg2 = SVGS ·

(1 +

SVGSLLSVGSLP

gate

)·

WSVGSWPgate

WSVGSWPgate + SVGSW

· Vgp (163)

16.1.1 Impact-Ionization Induced Bulk Potential Change

The impact ionization induces electron and hole pairs, which is the origin of the substrate current.

However, not only the leakage current but also the charge distribtuion in the bulk is changed. This

induced charge redistribution affects as the bulk potential change. This is modeled in a simple way as

∆Ids =23

√2εSiqNsub

β


3232

β∆Vbulk

β(φSL − Vbs)− 1(164)

−β(φS0 − Vbs)− 1

3232

β∆Vbulk


](165)

−

√2εSiqNsub

β


1212

β∆Vbulk

β(φSL − Vbs)− 1(166)

−β(φS0 − Vbs)− 1

1212

β∆Vbulk


](167)

where

∆Vbulk = IBPC1(1 + IBPC2 ·∆Vth) · Isub (168)

IBPC1 and IBPC2 are model parameters.

53


Impact-Ionization in Drift Region

With increased Vgs the impact ionization occurs in the drift region, which shows exponential character-

istics as a function of Vgs. This type of impact-ionization induced current is

Isub = Ids · SUBLD1 · (Vds − φS(∆L) + φS0)

· exp(−(LOVERLD + LDRIFT1 + LDRIFT2) · SUBLD2

(Vds − φS(∆L) + φS0) · f(VgVt)

)(169)

f(VgVt) =√

QI/q (170)

This Isub is added to the original Isub. The parameters SUBLD1 and SUBLD2 are recognized as

model parameters as well as instance parameters. The values determined as instance paremters have

higher prioity.

16.2 Gate Current

All possible gate leakage currents are schematically shown in Fig. 31.

gsIgateI

gdIgbI

Fig. 31: Gate leakage currents considered.

(i) Between Gate and Channel, Igate

As for the current between gate and channel, (Igate) the direct-tunneling mechanism is considered [35].

Since measured Igate shows nearly linear Lgate dependence, the tunneling is assumed to occur along the

whole channel length. Thus the final description implemented in HiSIM is [36, 37]

Igate = q ·GLEAK1 · E2

E12gp

· exp

(−E

32gp ×GLEAK2

E

)·√

Qi

const0·Weff ·NF · Leff

· GLEAK6GLEAK6 + Vds

· GLEAK7GLEAK7 + Weff ·NF · Leff

(171)

54


where

E =VG −GLEAK3× φS(∆L)2 GLEAKUNIT

Tox·(

1 +Ey

GLEAK5

)(172)

VG = Vgs −VFBC + GLEAK4 ·∆Vth · Leff (173)

∆Vth = ∆Vth,SC + ∆Vth,P + ∆Vth,W − φSpg (174)

where GLEAKUNIT is a dimension of 1/V. GLEAK1− 7 are model parameters, and Egp describes

the temperture dependent bandgap for the gate current. The gate-channel current Igate is partitioned

into two terminal currents with one model parameter in the following manner.

Igate = Igate,s + Igate,d (175)

where

Igate,s = (1− Patition · Igate) (176)

Igate,d = Partition · Igate (177)

where analytical description of Partition is obtained by integrating the following equation in the same

manner as the drain current given in Eq. (10)

Igate,d =∫ Leff

0

y

LeffIgate(y)dy = PartitionIgate (178)

The straightforward simulation result is shown in Fig. 32. However, the derived equation requires long

simulation time and has to be simplified.

55


Fig. 32: Exact results of gate partitioning.

(ii) Between Gate and Bulk, Igb

The Igb current under the accumulation condition is modeled as

Igb = GLKB1 · E2gb · exp

(−GLKB2

Egb

)Weff ·NF · Leff (179)

Egb = −Vgs −VFBC + GLKB3Tox

(180)

The Fowler-Nordheim tunneling mechanism is also considered

IFN =q · FN1 · E2

FN

Eg12· exp

(−FN2 · Eg32

EFN

)·Weff ·NF · Leff (181)

where

EFN = −FVBS · Vbs − (Vgs −∆Vth,SC −∆Vth,P)− FN3TOX

(182)

Eg32 = Eg · Eg12 (183)

Eg12 =√

Eg (184)

Total substrate current is the sum of the two components as

Igb = Igb + IFN (185)

(iii) Between Gate and Source/Drain, Igs/Igd

The tunneling current between the gate and the source/drain overlap region is modeled as

Igs = signGLKSD1 · E2gs exp (Tox(−GLKSD2 · Vgs + GLKSD3)) Weff ·NF (186)

56


Egs =Vgs

Tox(187)

Igd = signGLKSD1 · E2gd exp (Tox(GLKSD2 · (−Vgs + Vds) + GLKSD3)) Weff ·NF (188)

Egd =Vgs − Vds

Tox(189)

sign = +1 for E ≤ 0

sign = −1 for E ≥ 0

16.3 GIDL (Gate-Induced Drain Leakage)

The GIDL current is generated at the drain junction under the accumulation condition. The Vds increase

induces a very narrow potential well in the drain just under the gate, causing carrier generation. Therefore,

the GIDL current is strongly dependent on Vds. At further reduced Vgs values the direct gate tunneling

starts to dominate the IGIDL measurements, resulting in Vds independence. The Vds dependent IGIDL

is modeled here. The generation mechanism is considered to be the direct tunneling between the above

mentioned narrow potential well of length ∆Y and the ordinary drain region.

IGIDL = αIds∆Y (190)

The generation occurs only in this ∆Y region at the drain. The final equation is

IGIDL = q ·GIDL1 · E2

E12g

· exp

(−GIDL2 · E

32g

E

)·Weff ·NF (191)

where

E =GIDL3 · (Vds + GIDL4)− V ′

G

Tox(192)

and

V ′G = Vgs + ∆Vth ·GIDL5 (193)

Here ∆Vth is defined as

∆Vth = ∆Vth,SC + ∆Vth,P (194)

The GISL current is calculated with the same equation as the GIDL current described above. The

selection either IGIDL or IGISL is done by the polarity of the current flow.


57



SUB1 substrate current coefficient of magnitudeSUB1L Lgate dependence SUB1

SUB1LP Lgate dependence SUB1SUB2 substrate current coefficient of exponential termSUB2L Lgate dependence of SUB2SVDS substrate current dependence on Vds

SLG substrate current dependence on Lgate

SLGL substrate current dependence on Lgate

SLGLP substrate current dependence on Lgate

SVBS substrate current dependence on Vbs

SVBSL Lgate dependence of SVBSSVBSLP Lgate dependence of SVBSSVGS substrate current dependence on Vgs

SVGSL Lgate dependence of SVGSSVGSLP Lgate dependence of SVGSSVGSW Wgate dependence of SVGS

SVGSWP Wgate dependence of SVGSIBPC1 impact-ionization induced bulk potential changeIBPC2 impact-ionization induced bulk potential change

SUBLD1 substrate current induced in Ldrift


GLEAK1 gate to channel current coefficientGLEAK2 gate to channel current coefficientGLEAK3 gate to channel current coefficientGLEAK4 gate to channel current coefficient∗GLEAK5 gate to channel current coefficient ( short channel correction )∗GLEAK6 gate to channel current coefficient ( Vds dependence correction )∗GLEAK7 gate to channel current coefficient ( gate length and width dependence correction )∗EGIG bandgap of gate leakage

∗IGTEMP2 temperature dependence of gate leakage∗IGTEMP3 temperature dependence of gate leakage

GLKB1 gate to bulk current coefficientGLKB2 gate to bulk current coefficientGLKB3 flat-band shift for gate to bulk currentGLKSD1 gate to source/drain current coefficientGLKSD2 gate to source/drain current coefficientGLKSD3 gate to source/drain current coefficientGLPART1 partitioning ratio of gate leakage current

FN1 coefficient of Fowler-Nordheim-current contributionFN2 coefficient of Fowler-Nordheim-current contributionFN3 coefficient of Fowler-Nordheim-current contribution

FVBS Vbs dependence of Fowler-Nordheim currentGIDL1 magnitude of the GIDLGIDL2 field dependence of the GIDLGIDL3 Vds dependence of the GIDL∗GIDL4 threshold of Vds dependence∗GIDL5 correction of high-field contribution

58


17 Source/Bulk and Drain/Bulk Diode Models

17.1 Diode Current

The model equations for the source/bulk and drain/bulk diode currents are based on the concepts of

BSIM3v3 [39], but include a number of modifications.

The two regions denoted (a) and (b) in the schematic diagram of Fig. 33, correspond to the forward-bias

current saturation and the backward-bias region, respectively. These regions are distinguished in the

modeling and are treated separately according to their origins.

T Vbd,Vbs

(b) (a)

I bd

I bs

2T1 ,

,lo

g(

)

Fig. 33: The two Idiode currents (Ibd and Ibs) are modeled separately in the two different operatingregions (a) and (b).

The models for forward-biased current densities, describing the area and sidewall components of the

source/drain regions, are given in Eqs. (196) and (197), respectively. The corresponding backward-

biased current densities are given in Eqs. (198) and (199).

Ttnom =T

TNOM(195)

js = JS0 exp

(Eg(T = TNOM) · β(T = TNOM)− Egβ + XTI · log(Ttnom))NJ

(196)

jssw = JS0SW exp

(Eg(T = TNOM) · β(T = TNOM)− Egβ + XTI · log(Ttnom))NJSW

(197)

js2 = JS0 exp

(Eg(T = TNOM) · β(T = TNOM)− Egβ + XTI2 · log(Ttnom))NJ

(198)

jssw2 = JS0SW exp

(Eg(T = TNOM) · β(T = TNOM)− Egβ + XTI2 · log(Ttnom))NJSW

(199)

Nvtm =NJβ

(200)

(i) Between Drain and Bulk

59


With these current densities and the area parameter AD and the perimeter parameter PD of the drain

region, the forward and backward currents between drain and bulk are calculated as

Isbd = AD · js + PD · jssw (201)

Isbd2 = AD · js2 + PD · jssw2 (202)

The resulting drain-bulk current equations in the 2 operating regions (a) and (b) are derived as follows.

a) Vbd ≥ T1

Ibd =Isbd

exp

(T1

Nvtm

)− 1

+Isbd

Nvtmexp

(T1

Nvtm

)(Vbd − T1)

+ Isbd2 ·CISB

exp(−VbdCVBK

Nvtm

)− 1

exp (Ttnom − 1)CTEMP

+ CISBK

exp(−VbdCVBK

Nvtm

)− 1

(203)

b) T1 ≥ Vbd

Ibd =Isbd

exp

(Vbd

Nvtm

)− 1

+ Isbd2 ·CISB ·

exp(−Vbd ·CVB

Nvtm

)− 1


+ CISBK ·

exp(−Vbd ·CVBK

Nvtm

)− 1

(204)

T1 = Nvtm · log

VDIFFJIsbd

· (Ttnom)2 + 1

(205)

Ibd = Ibd + DIVX · Isbd2 · Vbd (206)

(ii) Between Source and Bulk

The area parameter AS and the perimeter parameter PS of the source region are used to calculate the

forward and backward currents between source and bulk.

Isbs = AS · js + PS · jssw (207)

Isbs2 = AS · js2 + PS · jssw2 (208)

This leads to the following source-bulk current equations in the 3 operating regions (a), (b) and (c).

a) Vbs ≥ T2

Ibs =Isbs

exp

(T2

Nvtm

)− 1

+Isbs

Nvtmexp

(T2

Nvtm

)(Vbs − T2)

+ Isbs2 ·CISB

exp(−VbsCVBK

Nvtm

)− 1


+ CISBK

exp(−VbsCVBK

Nvtm

)− 1

(209)

60


b) T2 ≥ Vbs

Ibs =Isbs ·

exp(

Vbs

Nvtm

)− 1

+ Isbs2 ·CISB ·

exp(−Vbs ·CVB

Nvtm

)− 1· exp (Ttnom − 1) ·CTEMP

+ CISBK ·

exp(−Vbs ·CVBK

Nvtm

)− 1

(210)

T2 = Nvtm · log

VDIFFJIsbs

· Ttnom)2 + 1

(211)

Ibs = Ibs + DIVX · Isbs2 · Vbs (212)

The hard-breakdown model of the diode will be implemented in a future version of HiSIM.

17.2 Diode Capacitance

The diode capacitances of the source/bulk junction Capbs and of the drain/bulk junction Capbd are given

by the following equations. These equations have the same basis as those used in BSIM3v3 [39], but

include a number of minor modifications.

The notations Θ = S, θ = s (for source/bulk junction) and

Θ = D, θ = d (for drain/bulk junction) apply.

czbθ = CJ ·AΘ (213)

(I) PΘ > Weff

czbθsw = CJSW(PΘ−Weff ·NF) (214)

czbθswg = CJSWG ·Weff ·N (215)

(i) Vbθ = 0

Qbθ = 0 (216)

Capbθ = czbθ + czbθsw + czbθswg (217)

(ii) Vbθ < 0

a-1) czbθ > 0

arg = 1− Vbθ

PB(218)

α) MJ = 0.5

sarg =1

√arg

(219)

β) MJ 6= 0.5

sarg = exp(−MJ · log(arg)) (220)

Qbθ =PB · czbθ(1− arg · sarg)

1−MJ(221)

Capbθ = czbθ · sarg (222)

61


a-2) czbθ ≤ 0

Qbθ = 0 (223)

Capbθ = 0 (224)

b) czbθsw > 0

arg = 1− Vbθ

PBSW(225)

α) MJSW = 0.5

sarg =1

√arg

(226)

β) MJSW 6= 0.5

sarg = exp(−MJSW · log(arg)) (227)

Qbθ + =PBSW · czbθsw(1− arg · sarg)

1.0−MJSW(228)

Capbθ + = czbθsw · sarg (229)

c) czbθswg > 0

arg = 1− Vbθ

PBSWG(230)

α) MJSWG = 0.5

sarg =1

√arg

(231)

β) MJSWG 6= 0.5

sarg = exp(−MJSWG · log(arg)) (232)

Qbθ + =PBSWG · czbθswg(1− arg · sarg)

1−MJSWG(233)

Capbθ + = czbθswg · sarg (234)

(iii) Vbθ > 0

Qbθ = Vbθ(czbθ + czbθsw + czbθswg)

+ V 2bθ

(12

czbθ ·MJPB

+12

czbθsw ·MJSWPBSW

+12

czbθswg ·MJSWGPBSWG

)(235)

Capbθ = czbθ + czbθsw + czbθswg

+ Vbθ

(czbθ ·MJ

PB+

czbθsw ·MJSWPBSW

+czbθswg ·MJSWG

PBSWG

)(236)

(II) PΘ ≤ Weff

czbθswg = CJSWG · PΘ (237)

(i) Vbθ = 0

Qbθ = 0 (238)

Capbθ = czbθ + czbθswg (239)

(ii) Vbθ < 0

62


a-1) czbθ > 0

arg = 1− Vbθ

PB(240)

α) MJ = 0.5

sarg =1

√arg

(241)

β) MJ 6= 0.5

sarg = exp(−MJ · log(arg)) (242)

Qbθ =PB · czbθ(1− arg · sarg)

1−MJ(243)

Capbθ = czbθ · sarg (244)

a-2) czbθ ≤ 0

Qbθ = 0 (245)

Capbθ = 0 (246)

b) czbθswg > 0

arg = 1− Vbθ

PBSWG(247)

α) MJSWG = 0.5

sarg =1

√arg

(248)

β) MJSWG 6= 0.5

sarg = exp(−MJSWG · log(arg)) (249)

Qbθ + = PBSWG · czbθswg ·1− arg · sarg

1−MJSWG(250)

Capbθ + = czbθswg · sarg (251)

(iii) Vbθ > 0

Qbθ = Vbθ · (czbθ + czbθswg)

+ V 2bθ

(12

czbθ ·MJPB

+12


)(252)

Capbθ = czbθ + czbθswg

+ Vbθ

(czbθ ·MJ

PB+


)(253)


63


Table 15: HiSIM model parameters introduced in section 17 of this manual. # indicates instance param-eters.

JS0 saturation current densityJS0SW sidewall saturation current density

NJ emission coefficientNJSW sidewall emission coefficientXTI temperature coefficient for forward-current densitiesXTI2 temperature coefficient for reverse-current densitiesDIVX reverse current coefficientCISB reverse biased saturation currentCVB bias dependence coefficient of CISB

CTEMP temperature coefficient of reverse currentsCISBK reverse biased saturation current ( at low temperature )CVBK bias dependence coefficient of CISB ( at low temperature )

CJ bottom junction capacitance per unit area at zero biasCJSW source/drain sidewall junction cap. grading coefficient per unit length at zero bias

CJSWG source/drain sidewall junction capacitance per unit length at zero biasMJ bottom junction capacitance grading coefficient

MJSW source/drain sidewall junction capacitance grading coefficientMJSWG source/drain gate sidewall junction capacitance grading coefficient

PB bottom junction build-in potentialPBSW source/drain sidewall junction build-in potential

PBSWG source/drain gate sidewall junction build-in potentialVDIFFJ diode threshold voltage between source/drain and substrate

#AD junction area of the drain contact#PD junction periphery of the drain contact#AS junction area of the source contact#PS junction periphery of the source contact

64


18 Noise Models

18.1 1/f Noise Model

The 1/f noise is caused by both the carrier fluctuation and the mobility fluctuation. The final description

for the drift-diffusion model is [40]

SIds =I2dsNFTRP

βf(Leff −∆L)Weff ·NF

[1

(N0 + N∗)(NL + N∗)+

2µEyNFALPNL −N0

ln(

NL + N∗

N0 + N∗

)+ (µEyNFALP)2

](254)

where the parameters NFALP and NFTRP represent the contribution of the mobility fluctuation and

the ratio of trap density to attenuation coefficient, respectively. N0 and NL are carrier densities at source

side and drain side or pinch-off point, respectively, as calculated in HiSIM. N∗ is written as

N∗ =Cox + Cdep + CIT

qβ(255)

where Cdep is the depletion capacitance calculated with φS. CIT is the capacitance caused by the

interface-trapped carriers and is normally fixed to be zero.

Nflick = SIds · fFALPH (256)

is calculated in HiSIM, where FALPH has been introduced to model the deviation from the exact 1/f

characteristic.

18.2 Thermal Noise Model

Van der Ziel derived the equation for the spectral density of the thermal drain-noise current at temperature

T by integrating the transconductance along the channel direction y based on the Nyquist theorem [41]

Sid =4kT

L2eff

∫gds(y)dy = 4kTgds0γ (257)

Here k, Ids, gds(y), gds0, γ are Boltzmann’s constant, drain current, position-dependent channel conduc-

tance, channel conductance at Vds = 0, and drain-noise coefficient, respectively. In HiSIM the integration

is performed with the surface potential φs instead of the channel position as [42, 43]

Sid =4kT

L2effIds

∫g2ds(φs)dφs (258)

gds(φs) =Weff ·NF

Leffβ

d(µ(φs)f(φs))dφs

(259)

Here f(φs) is a characteristic function of HiSIM related to the carrier concentration [44]. The final

equations for Sid in our compact-modeling approach, obtained after solving the integral of Eq. (258),

become functions of the self-consistent surface potentials as well as the surface-potential derivatives at

source and drain.

Sid = 4kTWeff ·NFCox V gV t µ

(Leff −∆L)(1 + 3η + 6η2)µ2

d + (3 + 4η + 3η2)µdµs + (6 + 3η + η2)µs

15(1 + η)µ2av

(260)

65


where µs, µd and µav are mobilities at the source side, the drain side, and averaged, respectively.

η = 1− (φSL − φS0) + χ(φSL − φS0)VgVt

(261)

χ = 2cnst0Cox

[[23

1β

β(φSL − Vbs)− 1 32 − β(φS0 − Vbs)− 1 3

2

φSL − φS0

]−√


](262)

V gV t is equal to the carrier density at the source side divided by the oxide capacitance.

Thus no additional model parameters are required for the thermal noise model.

Nthrml = Sid/4kT (263)

is calculated in HiSIM.

18.3 Induced Gate Noise Model

No additional model parameters are required for the induced gate noise model.

Nigate = Sigate/f2 (264)

is calculated in HiSIM. Explicit model equation were presented at SISPAD in 2006 [45].

18.4 Coupling Noise Model

No additional model parameters are required for the coupling noise model.

Ncross =Sigid√

Sigate · Sid

(265)

is calculated in HiSIM. Explicit model equation were presented at SISPAD in 2006 [45].


Table 16: HiSIM model parameters introduced in section 18 of this manual. ∗ indicates a minor parameter.

NFTRP ratio of trap density to attenuation coefficientNFALP contribution of the mobility fluctuation∗CIT capacitance caused by the interface trapped carriers

FALPH power of f describing deviation of 1/f

66


19 Non-Quasi-Static (NQS) Model

19.1 Carrier Formation

Carriers in the channel take time to build-up as opposed to the Quasi-Static (QS) approximation. To

consider this phenomenon in HiSIM, the carrier formation is modeled as [46, 47, 48]

q(ti) =q(ti−1) + ∆t

τ Q(ti)1 + ∆t

τ

(266)

where q(ti) and Q(ti) represent the non-quasi-static and the quasi-static carrier density at time ti, re-

spectively, and ∆t = ti − ti−1 is valid. Eq. (266) implies that the formation of carriers under the NQS

approximation is always delayed in comparison to the QS approximation, which is the basic origin of the

NQS effect. The delay is determined by the carrier transit delay τ and the time interval in the circuit

simulation ∆t.

19.2 Delay Mechanisms

Up to weak inversion, carriers diffuse to the channel and the transit delay is approximated by

τdiff = DLY1 (267)

At strong inversion, there is already conduction due to field-driven carriers. The transit delay due to the

flow of such conductive carriers is

τcond = DLY2 · Qi

Ids(268)

where DLY2 is a constant coefficient. These two delay mechanisms (diffusion and conduction) are

combined using the Matthiessen rule

1τ

=1

τdiff+

1τcond

(269)

Carrier delay mechanisms in a MOSFET switch-on operation with a gate-voltage rise time tr of 20ps are

illustrated in Fig. 34.

Applying the same approach for the formation of bulk carriers, leads to the approximation of the bulk

carrier delay as an RC delay in the form

τB = DLY3 · Cox (270)

where DLY3 is a constant coefficient and Cox is the oxide capacitance.

67


0 5 10 15 20 25 30

Time (ps)

1

10

10

10

104

105

3

2

1

τ

ττ

diff

cond Lg = 0.5µm

Vds = 1V

tr = 20ps

dela

y (p

s)0

1.5

Gate voltage (ps)

Fig. 34: Example of the dynamically calculated transit delay times, as incorporated in the NQS modelof HiSIM, in a MOSFET switch-on simulation.

19.3 Time-Domain Analysis

The total drain/source/bulk terminal currents are derived from the superposition of the transport current

and the charging current. The transport current is a function of the instantaneous terminal voltages and

is approximated by the steady-state solution. The source/drain/bulk charging currents are the time

derivatives of the associated non-quasi-static charges, qS, qD, and qB, respectively.

For LDMOS/HVMOS, carrier transit delay τ in the drift region is also important. The modeling is done

in the the same way as in the channel region as

τLD =(LOVERLD + LDRIFT1 + LDRIFT2)2

DLYDFT · (Vds − φSL + φS0)(271)

This delay mechnism is deactivated for this version.

The formation delay for the accumulation condition is also model as

τLD = DLYOV · Cox0 (272)

19.4 AC Analysis

This model part is now under revision.



DLY1 coefficient for delay due to diffusion of carriersDLY2 coefficient for delay due to conduction of carriersDLY3 coefficient for RC delay of bulk carriers

DLYDFT coefficient for carrier transit delay: inactivatedDLYOV coefficient for RC delay of carriers

68


20 Self-Heating Effect Model

The self-heating effect is modeled with the thermal network shown in Fig. 35. The flag COSELFHEAT

must be equal to one and RTH0 must not be equal to zero to activate the model. The temperature

node is automatically generated in circuit simulator for each device as other bias nodes. Fisrt, the model

core (HiSIM.eval) is called to evaluate device characteristics without heating. Then, the temperature is

updated considering the self-heating effect by creating the temperature node. The model core is called

again to update the device characteristics with the calculated temperature T . Under the DC condition

the temperature increase is calculated analytically as

T = T + RTH · Ids · Vds (273)

The model parameter RTH0 is fitted to measured DC data, and the model parameter CTH0 is intro-

duced for AC fitting, where

Rth =RTH0Weff

·(

1NFRTH0NF

)(1 +

RTH0W(Wgate · 104)RTH0WP

)(274)

Cth = CTH0 ·Weff (275)

IdsVds

Temp

CthRth Rth0R

Fig. 35: Thermal Network applied for the self-heating effect.

The model parameter RTH0R is introduced to model the thermal dissipation as

Rth0R =RTH0RTEMP3 (276)

If RTH0R is selected to zero, which is the usual case, the Rth0R element is neglected and only the

conventional Rth and Cth are considered.


69



RTH0 thermal resistanceCTH0 thermal capacitance

RTH0W width dependence of thermal resistanceRTH0WP width dependence of thermal resistanceRTH0NF number of finger dependence of thermal resistanceRTH0R thermal dissipation

70


21 DFM Model

To support design for manufacturability (DFM) HiSIM introduces an option for considering the variation

of device parameters.

Accurate prediction of device performance for a wide range of the substrate-impurity-concentration varia-

tions is secured by introducing an impurity concentration dependent mobility due to the phonon scattering

as

Muephonon = MUEPH1 [MPHDFMln(NSUBCDFM)− ln(NSUBC)+ 1]

NSUBP = NSUBP + (NSUBCDFM −NSUBC) (277)

NEXT = NEXT + (NSUBCDFM−NSUBC) (278)

where NSUBCDFM is an instance parameter and MPHDFM is a model parameter describing the

mobility reduction due to the increase of the substrate impurity concentration. This model is activated

if the model flag CODFM = 1, and NSUBCDFM is also given.


Table 19: HiSIM model parameters introduced in section 21 of this manual. # indicates an instanceparameter.

#NSUBCDFM substrate impurity concentrationMPHDFM mobility dependence of NSUBC due to µphonon

71


22 Exclusion of Modeled Effects and Model Flags

1. To exclude specific modeled effects, following parameter settings should be chosen:

Short-Channel Effect SC1 = SC2 = SC3 = 0Reverse-Short-Channel Effect LP = 0Quantum-Mechanical Effect QME1 = QME3 = 0Poly-Depletion Effect PGD1 = PGD2 = PGD3 = 0Channel-Length Modulation CLM1 = CLM2 = CLM3 = 0Narrow-Channel Effect WFC = MUEPHW = WL1 = 0Small-Size Effect WL2 = 0

Following flags are prepared to select required model options.

2. Contact resistances Rs and Rd are included:

CORSRD = 0: no

CORSRD = 1 & RS/RD 6= 0: yes, as internal resistances of HiSIM

CORSRD = 2 & RD 6= 0: yes, analytical description

CORSRD = 3 & RD 6= 0: yes, both internal and analytical descriptions (default)

CORSRD = −1 & RS/RD 6= 0: yes, as external resistances of HiSIM

3. Overlap capacitance model is selected as:

COOVLP = 0: constant overlap capacitance

COOVLP = 1: yes (default)

4. Substrate current Isub is calculated:

COISUB = 0: no (default)

COISUB = 1: yes

5. Gate current Igate is calculated:

COIIGS = 0: no (default)

COIIGS = 1: yes

6. GIDL current IGIDL is calculated:

COGIDL = 0: no (default)

COGIDL = 1: yes

7. STI leakage current Ids,STI is calculated:

COISTI = 0: no (default)

COISTI = 1: yes

8. Lateral field induced and overlap charges/capacitances are added to intrinsic ones:

COADOV = 0: no

COADOV = 1: yes (default)

9. Non-quasi-static mode is invoked:

CONQS = 0: no (default)

CONQS = 1: yes

72


10. Gate-contact resistance is included:

CORG = 0: no (default)

CORG = 1: yes

11. Substrate resistance network is invoked:

CORBNET = 0: no (default)

CORBNET = 1: yes

12. 1/f noise is calculated:

COFLICK = 0: no (default)

COFLICK = 1: yes

13. Thermal noise is calculated:

COTHRML = 0: no (default)

COTHRML = 1: yes

14. Induced gate and cross correlation noise are calculated:

COIGN = 0 ‖ COTHRML = 0: no (default)

COIGN = 1 & COTHRML = 1: yes

15. Previous Ids is used for calculating source/drain resistance effect (Rs and/or Rd 6= 0):

COIPRV = 0: no

COIPRV = 1: yes (default)

16. Previous φS is used for the iteration:

COPPRV = 0: no

COPPRV = 1: yes (default)

17. Parameter variations for the DFM support is considered:

CODFM = 0: no (default)

CODFM = 1: yes

18. Self-Heating Effect is considered:

COSELFHEAT = 0: no (default)

COSELFHEAT = 1: yes

19. Selection for asymmetrical (LDMOS) or symmetrical structure is done:

COSYM = 0: LDMOS (default)

COSYM = 1: symmetrical HV-MOS

73


23 List of Instance Parameters

Partly the same instance-parameter names and their definitions as in the BSIM3/4 models are adopted

for the convenience of HiSIM users. The HiSIM Research Group wishes to acknowledge the UC Berkeley

BSIM Research Group for the introduction of these instance parameters.

L gate length (Lgate) default: L = 2µmW gate width (Wgate) default: W = 2µm

** Diode **AD area of drain junctionAS area of source junctionPD perimeter of drain junctionPS perimeter of source junction

** Source/Drain Resistance **NRS number of source squaresNRD number of drain squares

** Gate Resistance **XGW distance from the gate contact to the channel edgeXGL offset of the gate lengthNF number of gate fingersM multiplication factor

NGCON number of gate contacts** Substrate Network **

RBPB substrate resistance networkRBPD substrate resistance networkRBPS substrate resistance networkRBDB substrate resistance networkRBSB substrate resistance network

** Length of Diffusion **SA length of diffusion between gate and STISB length of diffusion between gate and STISD length of diffusion between gate and gate

** Temperature **TEMP device temperature (T )

DTEMP device temperature change** Design for Manufacturability **

NSUBCDFM substrate impurity concentration** Substrate Current **



LDRIFT1 lenght of lightly doped drift region (default: 0)LDRIFT2 length of heavily doped drift region (defailt: 1 µm)

74


24 Default Parameters and Limits of the Parameter Values

The maximum and minimum limits of the model parameter are recommended values. These values may

be violated in some specific cases.

parameter unit min max default remarks

TOX [m] 30nXL [m] 0XW [m] 0XLD [m] 0 50n 30nXWD [m] -10n 100n 0TPOLY [m] 200×10−9

LL 0LLD [m] 0LLN 0WL 0WLD [m] 0WLN 0NSUBC [cm−3] 0NSUBP [cm−3] 1×1016 1×1019 1×1017

LP [m] 0 300n 0∗NPEXT [cm−3] 1×1016 1×1018 1×1017

∗LPEXT [m] 1×10−50 10×10−6 1×10−50

VFBC [V] −1.2 −0.8 −1.0VBI [V] 1.0 1.2 1.1KAPPA [—] 3.9EG0 [eV] 1.0 1.3 1.1785BGTMP1 [eV K−1] 90.25µ fixedBGTMP2 [eV K−2] −1µ 1µ 0.1µTNOM [C] 27

VMAX [cm s−1] 1MEG 20MEG 10MEGVOVER [cmVOVERP] 0 1.0 0.3VOVERP [—] 0 2 0.3∗VTMP [cm s−1] -2.0 1.0 0

QME1 [V−2m] 0 300n 0QME2 [V] 0 3.0 1.0QME3 [m] 0 800p 0

PGD1 [V] 0 50m 0PGD2 [V] 0 1.5 1.0PGD3 [—] 0 1.0 0.8∗PGD4 [—] 0 3.0 0

75



PARL2 [m] 0 50n 10nSC1 [—] 0 200 1.0SC2 [V−1] 0 50 1.0∗SC3 [V−1m] 0 1m 0∗SC4 [—] 0 0SCP1 [—] 0 50 1.0SCP2 [V−1] 0 50 0.1∗SCP3 [V−1m] 0 1m 0∗SCP21 [V] 0 5.0 0∗SCP22 [V4] 0 50m 0∗BS1 [V2] 0 100m 0∗BS2 [V] 0.5 1.0 0.9

∗PTHROU [—] 0 50m 0

MUECB0 [cm2V−1s−1] 100 100K 1KMUECB1 [cm2V−1s−1] 15 10K 100MUEPH0 [—] 0.25 0.35 0.3 fixedMUEPH1 [cm2V−1s−1(V cm−1)MUEPH0] 2K 30K 25K(nMOS),9K(pMOS)

MUETMP [—] 0.5 2.0 1.7∗MUEPHL [—] 0∗MUEPLP [—] 1.0MUESR0 [—] 1.8 2.2 2.0MUESR1 [cm2V−1s−1(V cm−1)MUESR0] 1×1014 5×1016 1×1016

∗MUESRL 0∗MUESLP 1.0NDEP [—] 0 1.0 1.0∗NDEPL [—] 0∗NDEPLP [—] 1.0NINV [—] 0 1.0 0.5∗NINVD [V−1] 0 0 0.0BB [—] 2.0(nMOS),1.0(pMOS) fixed

76



WFC [F cm−2m−1] -5.0×10−15 1×10−6 0∗WVTH0 0NSUBCW [cmNSUBCWP] 1.0NSUBCWP [—] 0∗NSUBP0 [cm−3] 0∗NSUBWP 1.0∗MUEPHW 0∗MUEPWP 1.0∗MUESRW 0∗MUESWP 1.0∗VTHSTI 0VDSTI 0SCSTI1 0SCSTI2 0SCSTI3 0NSTI [cm−3] 1.0×1017

WSTI [m] 0WSTIL 0WSTILP 1.0WSTIW 0WSTIWP 1.0WL1 0WL1P 1.0NSUBPSTI1 [m] 0NSUBPSTI2 [m] 0NSUBPSTI3 [m] 1.0MUESTI1 0MUESTI2 0MUESTI3 1.0

WL2 0WL2P 1.0∗MUEPHS 0∗MUEPSP 1.0∗VOVERS [—] 0∗VOVERSP [—] 0

CLM1 [—] 0.01 1.0 0.05CLM2 [—] 1.0 2.0 2.0CLM3 [—] 1.0 5.0 1.0CLM5 [—] 0 5.0 1.0CLM6 [—] 0 5.0 0

77



SUB1 [V−1] 50×10−3

SUB1L [m] 2.5×10−3

SUB1LP [—] 1.0SUB2 [V] 100SUB2L [m] 0 1.0 2×10−6

SVDS [—] 0.8SLG [m] 3×10−8

SLGL [mSLGLP] 0SLGLP [—] 1.0SVBS [—] 0.5SVBSL [mSVBSLP] 0SVBSLP [—] 1.0SVGS [—] 0.8SVGSL [mSVGSLP] 0SVGSLP [—] 1.0SVGSW [mSVGSWP] 0SVGSWP [—] 1.0

IBPC1 [VA−1] 0IBPC2 [V −1] 0SUBLD1 [—] 0SUBLD2 [—] 0

MPHDFM -3 3 -0.3

SAREF [m] 1.0×10−6

SBREF [m] 1.0×10−6

78



GLEAK1 [A V−3/2C−1] 50GLEAK2 [V−1/2cm−1] 10MEGGLEAK3 [—] 60×10−3

GLEAK4 [cm−1] 4.0∗GLEAK5 [V cm−1] 7.5×103

∗GLEAK6 [V] 250×10−3

∗GLEAK7 [cm2] 1×10−6

∗EGIG [V] 0∗IGTEMP2 [V K] 0∗IGTEMP3 [V K2] 0GLKSD1 [A cmV−2] 1fGLKSD2 [V−1cm−1] 1×10−2

GLKSD3 [cm−1] -1×10−2

GLKB1 [A V−2] 5×10−16

GLKB2 [cm V−1] 1.0GLKB3 [V] 0GLPART1 [-] 0 1.0 0.5FN1 [V −1.5· cm2] 0FN2 [V −0.5· cm−1] 0FN3 [V] 0FVBS [—] 0

GIDL1 [A V−3/2C−1cm] 2.0GIDL2 [V−2cm−1F−3/2] 3×107

GIDL3 [—] 0.9∗GIDL4 [V] 0.9∗GIDL5 [—] 0.2

VBSMIN [V] -10.5VVZADD0 [V] 10m fixedPZADD0 [V] 5m fixed

DDLTMAX [ ] 1 10 1DDLTSLP [ ] 0 20 0DDLTICT [ ] -3 20 10

79



JS0 [A m−2] 0.5×10−6

JS0SW [A m−1] 0NJ [—] 1.0NJSW [—] 1.0XTI [—] 2.0XTI2 [—] 0DIVX [V−1] 0CTEMP [—] 0CISB [—] 0CISBK [A] 0CVB [—] -0.1 0.2 0CVBK [—] -0.1 0.2 0CJ [F m−2] 5×10−4

CJSW [F m−1] 5×10−10

CJSWG [F m−1] 5×10−10

MJ [—] 0.5MJSW [—] 0.33MJSWG [—] 0.33PB [V] 1.0PBSW [V] 1.0PBSWG [V] 1.0VDIFFJ [V] 0.6×10−3

NFALP [cm s] 1×10−19

NFTRP [V−1cm−2] 10G∗CIT [F cm−2] 0FALPH [—] 1.0

DLY1 [s] 100×10−12

DLY2 [—] 0.7DLY3 [Ω] 0.8×10−6

XQY [m] 0 50n 0XQY1 [F·µmXQY2−1] 0 50n 0XQY2 [-] 0 50n 2LOVER [m] 30nOVSLP [—] 2.0×10−8

OVMAG [V] 500CGSO [F m−1] 0 100nm ×Cox to be set by userCGDO [F m−1] 0 100nm ×Cox to be set by userCGBO [F m−1] 0 0

80



RS [Ωm] 0 10m 0RD [Ωm] 0 100m 5mRSH [V A−1square] 0 1m 0RSHG [V A−1square] 0 100 0GBMIN [—] 1×10−12 requested by circuit sim.RBPB [Ω] 50RBPD [Ω] 50RBPS [Ω] 50RBDB [Ω] 50RBSB [Ω] 50

RTH0 [Kcm/W] 0.1CTH0 [Ws/(Kcm)] 1×10−7

RTH0W [—] 0RTH0WP [—] 1RTH0NF [—] 0RTH0R [—] 0

XLDLD [m] 1.0×10−6

LOVERLD [m] 1.0×10−6

NOVER [cm−3] 3×1016

VFBOVER [V] -0.5VDLYDFT [cm2/(Vs)] 5.0×10−2 inactivatedDLYOV [s/F] 1.0×103

QOVSM [—] 0.2 for smoothing of Qover

LDRIFT1 [m] 0.0LDRIFT2 [m] 1.0 ×10−6

+LDRIFT1 + LDRIFT2LDRIFT [m] 1.0 ×10−6 redetermined by LOVERLD

+LDRIFT1 + LDRIFT2RDVG11 [—] Vds,max/30 for CORSRD=1,3RDVG12 [—] Vds,max 100 for CORSRD=1,3RDVD [Ω/V] 7.0×10−2 for CORSRD=1,3RDVB [—] 0 for CORSRD=1,3RDS [—] 0 for CORSRD=1,3RDSP [—] 1 for CORSRD=1,3RDVDL [—] 0 for CORSRD=1,3RDVDP [—] 1 for CORSRD=1,3RDVDS [—] 0 for CORSRD=1,3RDVDSP [—] 1 for CORSRD=1,3RD20 [—] 0 for CORSRD=2,3RD21 [—] 1 for CORSRD=2,3RD22 [Ωm/V] 0 for CORSRD=2,3RD23 [Ωm/VRD21] 5m for CORSRD=2,3RD23L [—] 0 for CORSRD=2,3RD23LP [—] 1 for CORSRD=2,3RD23S [—] 0 for CORSRD=2,3RD23SP [—] 1 for CORSRD=2,3RD24 [Ωm/VRD21+1] 0 for CORSRD=2,3RD25 [V] 0 for CORSRD=2,3

81


parameter unit min max default remarksRD26 [—] 0.2 renamed to QOVSMRDOV11 [—] 0 Lover dependence of resistanceRDOV12 [—] 1.0 Lover dependence of resistanceRDSLP1 [—] 0 Ldrift1 dependence of resistanceRDITC1 [—] 1.0 Ldrift1 dependence of resistanceRDSLP2 [—] 1.0 Ldrift2 dependence of resistanceRDITC2 [—] 0 Ldrift2 dependence of resistanceRDTEMP1 [Ωm/K] 0 temperature dependence of resistanceRDTEMP2 [Ωm/K2] 0 temperature dependence of resistanceRDVDTEMP1 [—] 0 temperature dependence of resistanceRDVDTEMP2 [—] 0 temperature dependence of resistance

82


25 Overview of the Parameter-Extraction Procedure

25.1 General MOSFET Part

In HiSIM, device characteristics are strongly dependent on basic device parameter values, such as the

impurity concentration and the oxide thickness. Therefore, the parameter-value extraction has to be

repeated with measured characteristics of different devices in a specific sequence until extracted parameter

values reproduce all device characteristics consistently and reliably. To achieve reliable results, it is

recommended to start with initial parameter values according to the recommendations listed in the table

below. Since some of the model parameters such as Tox are difficult to extract, they are expected to

be determined directly by dedicated measurements. Threshold voltage measurements allow to derive a

rough extraction for the model parameters referred to as “basic device parameters”. The parameters

identified with the symbol ”*” in the Model Parameter Table are initially fixed to zero.

Determined by dedicated measurements Default values listed in the section 24(not changed during extraction procedure) are used initially for the groups of parameters listed belowTOX basic device parameters (not listed on left side)

gate leakageGIDLsource/bulk and drain/bulk diodesnoisesubthreshold swingnon-quasi-static modeloverlap capacitances

The sequence of device selection for the parameter extraction is recommended in 4 steps

1. Long-Channel Devices

2. Short-Channel Devices

3. Long-Narrow Devices

4. Short-Narrow Devices

Prior to the extracttion, a rough extraction with measured Vth−Lgate characteristics is recommended to

get rough idea about parameter values. These parameters are usually important giving strong influence

on accuracy of the total parameter extraction. The parameter extraction of the general MOSFET part

is summarized in the following Table.

25.2 HiSIM HV Specific Part

Model parameters are categorized into two parts: (1) general MOSFET related parameters and (2)

the HiSIM HV specific parameters. The HiSIM HV specific model parameters are extracted after the

extraction of the intrinsic MOSFET part. Recommended extraction procedure is to perform first (1) and

then (2). Thus the parameter extraction is done in the following sequence:

1. rougth extraction of the MOSFET parameters with measured Vth − Lgate

2. fine extraction with measured subthreshold in Ids − Vgs

3. extraction of mobility parameters with Ids − Vgs and Ids − Vds

83


Table 20: Summary of the 7 steps of HiSIM’s Parameter Extraction Procedure.

Step 1: Initial preparation and rough extraction1-1. Initialize all parameters to their default values1-2. Use the measured gate-oxide thickness for TOX TOX1-3. Rough extraction with Vth-dependence on Lgate NSUBC, VFB, SC1, SC2

[Vth − Vgs] SC3, NSUBP, LP, SCP1SCP2, SCP3NPEXT, LPEXT

1-4. Quantum and poly-depletion effects [Cgg − Vgs] QME1, QME2, QME3PGD1, PGD2

Step 2: Extraction with long and wide transistors2-1. Fitting of sub-threshold characteristics NSUBC, VFB, MUECB0

[Ids − Vgs] MUECB12-2. Determination of mobility parameters for low Vds MUEPH0, MUEPH1

[Ids − Vgs] MUESR0, MUESR12-3. Determination of mobility parameters for high Vds [Ids − Vgs] NINV, NDEPStep 3: Extraction with medium/short length and large width transistors3-1. Pocket-parameter extraction with medium NSUBP, LP

length transistors [Ids − Vgs] SCP1, SCP2, SCP3NPEXT, LPEXT

3-2. Short-channel-parameter extraction with SC1, SC2, SC3short-length transistors [Vth − Lgate] PARL2, XLD

3-3. Mobility-parameter refinement for low Vd [Ids − Vgs] MUEPHL, MUEPLPMUESRL, MUESLP

3-4. Velocity parameter extraction for high Vd [Ids − Vgs] VMAX, VOVER, VOVERP3-5. Parameters for channel-length modulation [Ids − Vds] CLM1, CLM2, CLM33-6. Source/drain resistances [Ids − Vds] RS, RD, RSH, NRS, NRD

Step 4: Extraction of the width dependencies for long transistors4-1. Fitting of sub-threshold width dependencies NSUBC, NSUBCW, NSUBCWP

[Ids − Vgs] WFC, XWD, WVTH04-2. Fitting of mobility width dependencies [Ids − Vgs] MUEPHW, MUEPWP

MUESRW, MUESWPStep 5: Extraction of the width dependencies for short transistors5-1. Fitting of sub-threshold dependencies [Ids − Vgs] NSUBP0, NSUBWP

Step 6: Extraction of small-geometry effects6-1. Effective channel-length corrections WL2, WL2P6-2. Mobility and velocity [Ids − Vds] MUEPHS, MUEPSP

VOVERSVOVERSP

Step 7: Extraction of temperature dependence with long-channel transistors7-1. Sub-threshold dependencies [Ids − Vgs] BGTMP1, BGTMP2

EG07-2. Mobility and maximum carrier-velocity MUETMP, VTMP

dependencies [Ids − Vgs]

84


4. extraction of resistance parameters with Ids − Vgs and Ids − Vds

5. fine extraction of resistance with channel-conductance and trans-conductance

6. capacitacne extraction

Agreement of the extraction results after the 3rd step is not sufficient especially in high Vgs region and

low Vds region. The 4th resistance-extraction step is focused on the resion where the quasi-saturation

effect is obvious. It is recommended to repeat the extraction steps from 3rd to 5th to achieve better

fitting. The steps from 1st to 3rd are the same as the conventional extraction procedure.

The extraction of the resistance parameters are done after the model selection as summarized in Fig. 36.

Rs, Rd extraction

Circuit simulator generates nodes for RS and RD

no

no

yes

yes

yes

CORSRD =1 or 3

CORSRD =-1

CORSRD =0

HiSIM iterationRdrift=f (RD, RDVD, RDVG11, RDVG12, RDVDL,

RDVDLP, RDS, RDSP, RDVDS, RDVDSP)

Vgseff= Vgs – IdsxRsVdseff= Vds – Idsx(Rs+ Rdrift )Vbseff= Vbs – IdsxRs

Vgseff=VgsVdseff=VdsVbseff=Vbs

Ids= Idso / (1+ Idso (Rd/Vds))Rd=f (RD23, RD23L, RD23P, RD23S, RD23SP,RD24, RD25, RD20, RD22, RD21)

Surface-Potential CalculationDevice-Characteristic Calculation

VgseffVdseffVbseff

CORSRD =2 or 3

yes

no

no

Fig. 36: Parameter extraction flow for resistance parameters.

If the self-heating effect is activatied, all device characteristics are changed drastically. Retunning of

model parameters are required. These model parameters are mostly related to the mobility and re-

sistance models. The temperature dependent parameters are extracted without the self-heating effect

with temperature dependent measurements. These values are usually not necessary to be modified after

activating the self-heating effect.

85


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