hsabaghianb @ kashanu.ac.ir Microprocessors 1-1 Microprocessors
Spring 2005
Slide 2
hsabaghianb @ kashanu.ac.ir Microprocessors 1-2 Books The Z80
Microprocessor, Hardware, Software programming & interfacing
Author: Burry B. Brey Translator: Hossein Nia Publisher: Astane
Ghodse Razavi(Beh Nashr
Slide 3
hsabaghianb @ kashanu.ac.ir Microprocessors 1-3 Books
Microcompiuter and Microprocessor : the 8080, 8085, Z-80
Programming, interfacing and trubleshooting Publisher: Nass
Pub.Date: 1381 Edition Turn: 3 ISBN: 964-6264-43-4-3 Pages: 719
Author: John E. UffenbeckTranslator: Mahmmod Dayani
Slide 4
hsabaghianb @ kashanu.ac.ir Microprocessors 1-4 Books The 80x86
IBM PC and compatible computers (Design and interfacing of the IBM
PC PS and compatible) Publisher: Baghani Pub.Date: 1379 Edition
Turn: 2 ISBN: 964-91532-3-3 Pages: 760 Author: Mohammad Ali. Mazidi
Janice Gillispie. MazidiTranslator: Dr. Sepidnam
Slide 5
hsabaghianb @ kashanu.ac.ir Microprocessors 1-5 Books
Microcontroller 8051 Publisher: Baghani Pub.Date: 1380 ISBN:
964-7343-00-0 Pages: 380 Author: Mohammad ali Mazidi Jonis Glispi
MazidiTranslator: Dr. Sepidnam
hsabaghianb @ kashanu.ac.ir Microprocessors 1-7 Intruduction
Microprocessor (uP)(MPU) A uP is a CPU on a single chip. Components
of CPU ALU, instruction decoder, registers, bus control circuit,
etc. Micro-computer (u-Computer) small computer uP + peripheral I/O
+ memory specifically for data acquisition and control applications
Microcontroller (uC) u-Computer on a single chip of silicon
Slide 8
hsabaghianb @ kashanu.ac.ir Microprocessors 1-8 uP vs. uC uP A
uP only is a single-chip CPU bus is available RAM capacity, num of
port is seletable RAM is larger than ROM (usually) A uC contains a
CPU and RAM,ROM,Prepherals, I/O port in a single IC internal
hardware is fixed Communicate by port ROM is larger than RAM
(usually) Small power consumption Single chip, small board
Implementation is easy Low cost
Slide 9
hsabaghianb @ kashanu.ac.ir Microprocessors 1-9 Applications
uCs are suitable to control of I/O devices in designs requiring a
minimum component uPs are suitable to processing information in
computer systems. uP vs. uC cont.
Slide 10
hsabaghianb @ kashanu.ac.ir Microprocessors 1-10 uP vs. uC
cont. uC is easy to use and design. Only single chip can be a
complete system interfacing to other devices, for example, motors,
displays, sensors, and communicate with PC. In contrast, similar
system that builds from uP would require a lot of additional units,
such as RAM, UART, I/O, TIMER and etc.
Slide 11
hsabaghianb @ kashanu.ac.ir Microprocessors 1-11 uC is a
Reusable Hardware Logic circuit provides limited function for one
single design. In order to change circuits functionality, we need
to redesign the circuits. uC can reprogram and change functionality
of every port, input to output or digital to analog on the
fly.
Slide 12
hsabaghianb @ kashanu.ac.ir Microprocessors 1-12 uCs Many uCs
are existing right now. 8051, 68HC11, MSP430, ARM series, and etc.
We may widely divide it with how it is designed RISC/CISC
architecture. What is the main difference between RISC/CISC? Does
it make any difference to our application?
Slide 13
hsabaghianb @ kashanu.ac.ir Microprocessors 1-13 The
Microprocessor (MPU) The uP is the brain of the microcomputer Is a
single chip which is capable of processing data controlling all of
the components which make up the microcomputer system P used to
sequence executions of instructions that is in memory uP Fetch,
Decode, and Execute the instruction The internal architecture of
the microprocessor is complex.
Slide 14
hsabaghianb @ kashanu.ac.ir Microprocessors 1-14 The
Microprocessor (MPU) microprocessor (MPU) typically contains
Registers: Temporary storage locations for program instruction or
data. The Arithmetic Logic unit (ALU): This part of the MPU
performs both arithmetic and logical operations Timing and Control
Circuits: that keep all of the other parts of system (Regs, ALU,
memory & I/O) working together in the right time sequence
Slide 15
hsabaghianb @ kashanu.ac.ir Microprocessors 1-15 Microcomputers
All Microcomputers consist of (at least) : 1. Microprocessor Unit
(MPU) 2. Program Memory (ROM) 3. Data Memory (RAM) 4. Input /
Output ports 5. Bus System (and Software) MPU is the brain of
microcomputer
hsabaghianb @ kashanu.ac.ir Microprocessors 1-17 The
Input/Output (I/O) System I/O is the link between the MPU and the
outside world. An input port is a circuit through which an external
device can send signals (data?) to the MPU. An output port is a
circuit that allows the MPU to send signals (data?) to external
devices. I/O ports connect both digital and analogue devices by DAC
and ADC
Slide 18
hsabaghianb @ kashanu.ac.ir Microprocessors 1-18 Bus A Bus is a
common communications pathway used to carry information between the
various elements of a computer system The term BUS refers to a
group of wires or conduction tracks on a printed circuit board
(PCB) though which binary information is transferred from one part
of the microcomputer to another The individual subsystems of the
digital computer are connected through an interconnecting BUS
system.
Slide 19
hsabaghianb @ kashanu.ac.ir Microprocessors 1-19 Bus There are
three main bus groups ADDRESS BUS DATA BUS CONTROL BUS
Slide 20
hsabaghianb @ kashanu.ac.ir Microprocessors 1-20 Data Bus The
Data Bus carries the data which is transferred throughout the
system. ( bi-directional) Examples of data transfers Program
instructions being read from memory into MPU. Data being sent from
MPU to I/O port Data being read from I/O port going to MPU Results
from MPU sent to Memory These are called read and write
operations
Slide 21
hsabaghianb @ kashanu.ac.ir Microprocessors 1-21 Address Bus An
address is a binary number that identifies a specific memory
storage location or I/O port involved in a data transfer The
Address Bus is used to transmit the address of the location to the
memory or the I/O port. The Address Bus is unidirectional ( one way
): addresses are always issued by the MPU.
Slide 22
hsabaghianb @ kashanu.ac.ir Microprocessors 1-22 Control Bus
The Control Bus: is another group of signals whose functions are to
provide synchronization ( timing control ) between the MPU and the
other system components. Control signals are unidirectional, and
are mainly outputs from the MPU. Example Control signals RD: read
signal asserted to read data into MPU WR: write signal asserted to
write data from MPU
Slide 23
hsabaghianb @ kashanu.ac.ir Microprocessors 1-23 Main memory
The duties of the memory are : To store programs To provide data to
the MPU on request To accept result from the MPU for storage Main
memory Types ROM : read only memory. Contains program (Firmware).
does not lose its contents when power is removed (Non-volatile)
RAM: random access memory (read/write memory) used as variable
data, loses contents when power is removed volatile. When power up
will contain random data values
Slide 24
hsabaghianb @ kashanu.ac.ir Microprocessors 1-24 Read-Only
Memory uP can read instructions from ROM quickly Cannot write new
data to the ROM ROM remembers the data, even after power cycled
Typically, when the power is turned on, the microprocessor will
start fetching instructions from the still-remembered program in
ROM (bootstrap )
Slide 25
hsabaghianb @ kashanu.ac.ir Microprocessors 1-25 Available ROMs
Masked ROM or just ROM PROM or programmable ROM(once only) EPROM
(erasable via ultraviolet light) Flash (can be erased and
re-written about 10000 times, usually must write a whole block not
just 1 byte or 2 bytes, slow writing, fast reading) EEPROM
(electrically erasable read-only memory, also known as EEROMboth
reading and writing are very slow but can program millions of
timesuseless for storing a program but good for say configuration
information.
Slide 26
hsabaghianb @ kashanu.ac.ir Microprocessors 1-26 ROM A0 A1 A2
Am D0 Dn D1 D2 n+1 bit Data Capacity : m+1 bit Address : Output
Enable connect to RD of uP : Chip Enable to Address decoder ROM
PROM EEPROM
Slide 27
hsabaghianb @ kashanu.ac.ir Microprocessors 1-27 Timing Diagram
for a Typical ROM A0-Am D0-Dn OE falls to data valid Addr valid to
data valid
Slide 28
hsabaghianb @ kashanu.ac.ir Microprocessors 1-28 27XX EPROM 16
kbit 2 kbyte 32 kbit 4 kbyte 64 kbit 8 kbyte PGM and VPP are used
to programming
hsabaghianb @ kashanu.ac.ir Microprocessors 1-31 RAM (Random
Access Memory) The uP can read the data from RAM quickly, The uP
can write new data quickly to RAM RAM forgets its data if power is
turned off Two type of is available : Static RAM(SRAM): ff base,
fast, expensive, low cap/vol, applied for cache, no refresh Dynamic
RAM (DRAM): cap base, slow, low cost high capacity/volume, applied
for main memory(pc) need refresh.
Slide 32
hsabaghianb @ kashanu.ac.ir Microprocessors 1-32 RAM(Static) A0
A1 A2 Am D0 Dn D1 D2 n+1 bit Data Capacity : m+1 bit Address : Chip
Select to Address decoder RAM : Read signal connect to MemRD of uP
: Write signal connect to MemWR of uP Data bus is
Bidirectional
Slide 33
hsabaghianb @ kashanu.ac.ir Microprocessors 1-33 Session 2
Microprocessors History Data width 8086 vs 8088 8086 pin
description Z80 Pin description
Slide 34
hsabaghianb @ kashanu.ac.ir Microprocessors 1-34
Microprocessors Microprocessors come in all kinds of varieties from
the very simple to the very complex Depend on data bus and register
and ALU width uP could be 4-bit, 8-bit, 16-bit, 32-bit, 64-bit We
will discuss two sample of it Z80 as an 8-bit uP and 8086/88 as an
16-bit uP All uPs have the address bus the data bus RD, WR, CLK,
RST, INT,...
hsabaghianb @ kashanu.ac.ir Microprocessors 1-36 Internal and
External Bus Internal bus is a pathway for data transfer between
registers and ALU in the uPs External bus is available externally
to connect to RAM, ROM and I/O Int. and Ext. Bus width may be
different For example In 8088 Int. Bus is 16-bit, Ext. bus is 8-bit
In 8086 Int. Bus is 16-bit, Ext. bus is 16-bit
Slide 37
hsabaghianb @ kashanu.ac.ir Microprocessors 1-37 8086 vs 8088
16_bit Data Bus 20_bit Address 8_bit Data Bus 20_bit Address 8088
8086 Only external bus of 8088 is 8_bit
hsabaghianb @ kashanu.ac.ir Microprocessors 1-39 8086 Pin
Description Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground
AD0..AD7, A8..A15, A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address
Bus MN/MX (input) : Indicates Operating mode READY (input, Active
High) : take uP to wait state CLK (input) : Provides basic timing
for the processor RESET (input, Active High) : At least 4 clock
cycles Causes the uP immediately terminate its present activity.
TEST (input, Active Low) : Connect this to HIGH HOLD (input, Active
High) : Connect this to LOW HLDA (output, Active High) : Hold Ack
INTR (input, Active High) : Interrupt request INTA (output, Active
Low) : Interrupt Acknowledge NMI (input, Active High) :
Non-maskable interrupt
Slide 40
hsabaghianb @ kashanu.ac.ir Microprocessors 1-40 8086 Pin
Description DEN (output) : Data Enable. It is LOW when processor
wants to receive data or processor is giving out data (to 74245 )
DT/R (output) : Data Transmit/Receive. When High, data from uP to
memory When Low, data is from memory to uP (to74245 dir) IO/M
(output) : If High uP access I/O Device. If Low uP access memory RD
(output) : When Low, uP is performing a read operation WR (output)
: When Low, uP is performing a write operation ALE (output) :
Address Latch Enable, Active High Provided by uP to latch address
When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as
address lines
Slide 41
hsabaghianb @ kashanu.ac.ir Microprocessors 1-41 Z80 CPU Pin
Assignment
Slide 42
hsabaghianb @ kashanu.ac.ir Microprocessors 1-42 Z80 Pin
Description A15-A0 : Address bus (output, active high, 3-state).
Used for accessing the memory and I/O ports During the refresh
cycle the I is put on this bus. D7-D0 : Data Bus (input/output,
active high, 3-state). Used for data exchanges with memory, I/O and
interrupts. RD: Read (output, active Low, 3-state) indicates that
the CPU wants to read data from memory or I/O WR: Write (output,
active Low, 3-state) indicates that the CPU data bus holds valid
data to be stored at the addressed memory or I/O location.
Slide 43
hsabaghianb @ kashanu.ac.ir Microprocessors 1-43 Z80 Pin
Description MREQ Memory Request (output, active Low, 3-state).
Indicates memory read/write operation. See M1 IORQ Input/Output
Request(output,active Low,3-state) Indicates I/O read/write
operation. See M1 M1 Machine Cycle One (output, active Low).
Together with MREQ indicates opcode fetch cycle Together with IORQ
indicates an Int Ack cycle RFSH Refresh (output, active Low).
Together with MREQ indicates refresh cycle. Lower 7-bits address is
refresh address to DRAM
Slide 44
hsabaghianb @ kashanu.ac.ir Microprocessors 1-44 Z80 Pin
Description INT Interrupt Request (input, active Low). Interrupt
Request is generated by I/O devices. Checked at the end of the
current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable
Interrupt (Input, negative edge-triggered). Higher priority than
INT. Recognized at the end of the current Instruction Independent
of the status of IFF Forces the CPU to restart at location
0066H.
Slide 45
hsabaghianb @ kashanu.ac.ir Microprocessors 1-45 Z80 Pin
Description BUSREQ Bus Request (input, active Low). higher priority
than NMI recognized at the end of the current machine cycle. forces
the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to
high-imp. BUSACK Bus Acknowledge (output, active,Low) indicates to
the requesting device that address, data, and control signals MREQ,
IORQ, RD, and WR have entered their high-impedance states.
Slide 46
hsabaghianb @ kashanu.ac.ir Microprocessors 1-46 Z80 Pin
Description RESET Reset (input, active Low). RESET initializes the
CPU as follows: Resets the IFF Clears the PC and registers I and R
Sets the interrupt status to Mode 0. During reset time, the address
and data bus go to a high-impedance state And all control output
signals go to the inactive state. must be active for a minimum of
three full clock cycles before the reset operation is
complete.
Slide 47
hsabaghianb @ kashanu.ac.ir Microprocessors 1-47 Z80 CPU
Slide 48
hsabaghianb @ kashanu.ac.ir Microprocessors 1-48 Z80
Programming Model
Slide 49
hsabaghianb @ kashanu.ac.ir Microprocessors 1-49 Register Set A
: Accumulator Register F : Flag register Two sets of six
general-purpose registers may be used individually as 8-bit A F B C
D E H L (A F B C D E H L) or in pairs as 16-bit registers AF BC DE
HL (AF BC DE HL) The Alternative registers (A F B C D E H L) not
visible to the programmer but can access via: EXX (BC) (BC'), (DE)
(DE'), (HL) (HL') EX AF, AF (AF) (AF') what is this instruction
useful for?
Slide 50
hsabaghianb @ kashanu.ac.ir Microprocessors 1-50 Register
Set(cont) 4 16-bit registers hold memory address (pointers) index
registers (IX) and (IY) are 16-bit memory pointers 16 bit stack
pointer (SP) Program counter (PC) Program counter (PC) PC points to
the next opcode to be fetched from ROM when the P places an address
on the address bus to fetch the byte from memory, it then
increments the program counter by one to the next location Special
purpose registers I : Interrupt vector register. R : memory Refresh
register
Slide 51
hsabaghianb @ kashanu.ac.ir Microprocessors 1-51 Flag Register
SSign Flag (1:negativ)* ZZero Flag (1:Zero) HHalf Carry Flag (1:
Carry from Bit 3 to Bit 4)** PParity Flag (1: Even) VOverflow Flag
(1:Overflow)* NOperation Flag (1:previous Operation
wassubtraction)** CCarry Flag (1: Carry from Bit n-1 to Bit n, with
n length of operand) *:2-complement number representation **:used
in DAA-operation for BCD-arithmetic
Slide 52
hsabaghianb @ kashanu.ac.ir Microprocessors 1-52 DAA - Decimal
Adjust Accumulator before DAAafter DAA OpNCBits 4-7HBits 0-3A=A+..C
ADD ADC 000-90 000 000-80A-F060 000-910-3060 00A-F00-9601
009-F0A-F661 00A-F10-3661 010-200-9601 010-20A-F661 010-31 661 SUB
SBC NEG 100-90 000 100-816-FFA0 117-F00-9A01 116-F1 9A1 Adjusts the
content of the Accumulator A for BCD addition and subtraction
operations such as ADD, ADC, SUB, SBC, and NEG according to the
table:
Slide 53
hsabaghianb @ kashanu.ac.ir Microprocessors 1-53 Instruction
cycles, machine cycles and T-states Instruction cycle is the time
taken to complete the execution of an instruction Machine cycle is
defined as the time required to complete one operation of accessing
memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency) f=
4MHZ T-state=0.25 uS
Slide 54
hsabaghianb @ kashanu.ac.ir Microprocessors 1-54 Basic CPU
Timing Example
hsabaghianb @ kashanu.ac.ir Microprocessors 1-56 The R register
Is increased at every first machine cycle (M1). Bit 7 of it is
never changed by this; only the lower 7 bits are included in the
addition. So bit 7 stays the same Bit 7 can be changed using the LD
R,A instruction. LD A,R and LD R,A access the R register after it
is increased R is often used in programs for a random value, which
is good but of course not truly random. the block instructions
decrease the PC with two, so the instructions are re-executed.
hsabaghianb @ kashanu.ac.ir Microprocessors 1-64 M1 Refresh
Cycle Takes 4T to 6Ts Z80 includes built in circuitry for
refreshing DRAM This simplifies the external interfacing hardware
DRAM consists of MOS transistors, which store Information as
capacitive charges; each cell needs to be periodically refreshed
During T3 and T4 (when Z80 is performing internal ops), the low
order address is used to supply a 7-bit address for refresh
Slide 65
hsabaghianb @ kashanu.ac.ir Microprocessors 1-65 Wait Signal
the Z80 samples the wait signal during T2 if low then Z80 adds wait
states to extend the machine cycle used to interface memories with
slow response time Slow memory is low cost
Slide 66
hsabaghianb @ kashanu.ac.ir Microprocessors 1-66 Interrupts
There are two types of interrupts: non mask-able (NMI) Could not be
masked Jump to 0066H of memory mask-able(INT) Has 3 mode Can be set
with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets
Interrupt mode 1 IM 2 sets Interrupt mode 2
Slide 67
hsabaghianb @ kashanu.ac.ir Microprocessors 1-67 Interrupt
Modes Mode 0: An 8 bit opcode is Fetched from Data BUS and executed
The source interrupt device must put 8 bit opcode at data bus 8 bit
opcode usually is RST p instructions Mode 1: A jump is made to
address 0038h No value is required at data bus Mode 2: A jump is
made to address (register I 256 + value from interrupting device
that puts at bus) I is high 8 bit of interrupt vector Value is low
8 bit of interrupt vector
Slide 68
hsabaghianb @ kashanu.ac.ir Microprocessors 1-68
Slide 69
hsabaghianb @ kashanu.ac.ir Microprocessors 1-69 Z80 CPU
Instruction Description 158 different instruction types Including
all 78 of the 8080A CPU. Instruction groups Load and Exchange Block
Transfer and Search Arithmetic and Logical Rotate and Shift Bit
Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output
Basic CPU Control
hsabaghianb @ kashanu.ac.ir Microprocessors 1-71 Addressing
Modes(cont.) Register Addressing LD C,B Implied Addressing Op Code
implies other operand(s) ADD E Register Indirect Addressing 16-bit
CPU register pair as pointer (such as HL) ADD (HL) Bit Addressing
set, reset, and test instructions. SET 3,A RES 7,B
Slide 72
hsabaghianb @ kashanu.ac.ir Microprocessors 1-72 Minimal
Configuration of a Z80 Microcomputer
Slide 73
hsabaghianb @ kashanu.ac.ir Microprocessors 1-73 Z80 Memory
connection CPU 16 bit address bus 64 k memory(max) CPU 8 bit data
bus 8 bit data width Generally should be connected Data to data
Address to address Wr to wr Rd to rd Mreq to cs
Slide 74
hsabaghianb @ kashanu.ac.ir Microprocessors 1-74 Memory
connection (cont.) RAM 64 kb Z80 CPU D7~D0 A15~A0 If only one RAM
chip Full size (64 kb capacity)
Slide 75
hsabaghianb @ kashanu.ac.ir Microprocessors 1-75 Memory
connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15 If RAM
capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to
7FFFh
Slide 76
hsabaghianb @ kashanu.ac.ir Microprocessors 1-76 Memory
connection (cont.) There is two 32 kb RAM Problem: Bus Conflict.
The two memory chips will provide data at the same time when
microprocessor performs a memory read. Solution: Use address line
A15 as an arbiter. If A15 outputs a logic 1 the upper memory is
enabled (and the lower memory is disabled) and vice-versa.
Slide 77
hsabaghianb @ kashanu.ac.ir Microprocessors 1-77 Memory
connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0
A14~A0 A15 There is two 32 kb RAM A15 applied to select one RAM
chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh
(RAM1)
Slide 78
hsabaghianb @ kashanu.ac.ir Microprocessors 1-78 Memory
connection (cont.) ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0
A14~A0 A15 32 kb ROM and 32 kb RAM ROM doesnt have wr signal
Slide 79
hsabaghianb @ kashanu.ac.ir Microprocessors 1-79 Memory
connection (cont.) Z80 CPU There is 4 memory chip A14 and A15
applied to chip selection
hsabaghianb @ kashanu.ac.ir Microprocessors 1-81 Memory Map
Represents the memory type Address area of each memory chip Empty
area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM 1 16k 8000h BFFFh RAM 2
16k C000h FFFFh RAM 3 16k
Slide 82
hsabaghianb @ kashanu.ac.ir Microprocessors 1-82 Memory Map
Empty Area cannt write and read Read op. returns FFh value (usualy)
Write op. cannt store any value on it 0000h 3FFFh ROM 4000h 7FFFh
Empty 8000h BFFFh RAM 2 C000h FFFFh RAM 3 ROM 16 kb D7~D0 A13~A0
A15 RAM 16 kb D7~D0 A13~A0 RAM 16 kb D7~D0 A13~A0 A14 En S0 S1
Slide 83
hsabaghianb @ kashanu.ac.ir Microprocessors 1-83 Memory Map
Empty Area cannt write and read Read op. returns FFh value (usualy)
Write op. cannt store any value on it 0000h 3FFFh ROM 4000h 7FFFh
Empty 8000h BFFFh RAM C000h FFFFh Empty ROM 16 kb D7~D0 A13~A0 A15
RAM 16 kb D7~D0 A13~A0 A14 En S0 S1
Slide 84
hsabaghianb @ kashanu.ac.ir Microprocessors 1-84 Full and
Partial Decoding Full (exhaust) Decoding All of the address lines
are connected to any memory/device to perform selection Absolute
address : any memory location has one address Partial Decoding When
some of the address lines are connected the memory/device to
perform selection Using this type of decoding results into
roll-over addresses (fold back or shading). roll-over address : any
memory location has more than one address
Slide 85
hsabaghianb @ kashanu.ac.ir Microprocessors 1-85 Partial
Decoding A15~A12 has no connection Then doesnt play any role in
addressing What is the Memory and Address Bit map? RAM 4 kb Z80 CPU
D7~D0 A11~A0 X A15~A12
Slide 86
hsabaghianb @ kashanu.ac.ir Microprocessors 1-86 Partial
Decoding A15 to A0 (HEX) AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA
3210 Memory Chip X000h XFFFh xxxx 0000 1111 0000 1111 0000 1111 RAM
4 kb Z80 CPU D7~D0 A11~A0 X A15~A12 0000h 0FFFh RAM 1000h 1FFFh RAM
2000h 2FFFh RAM 3000h 3FFFh RAM F000h FFFFh RAM Every memory
location has more than one address For example first RAM location
has addresses: 0000h 1000h 2000h 3000h . F000h Roll-over
Address
Slide 87
hsabaghianb @ kashanu.ac.ir Microprocessors 1-87 Partial
Decoding A12 only connected to RAM A13 has no connection What is
the memory map? ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0
A12~A0 A14 A15 X A13
Slide 88
hsabaghianb @ kashanu.ac.ir Microprocessors 1-88 Partial
Decoding 8 roll-over address for ROM 4 roll-over address for RAM
AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0xxx
0000 1111 0000 1111 0000 1111 ROM X0x0 X0x1 0000 1111 0000 1111
0000 1111 RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0
A12~A0 A14 A15 X A13
Slide 89
hsabaghianb @ kashanu.ac.ir Microprocessors 1-89 Partial
Decoding AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory
Chip 0xxx 0000 1111 0000 1111 0000 1111 4k ROM X0x0 X0x1 0000 1111
0000 1111 0000 1111 8k RAM 0000h 1FFFh RAM 0000h 0FFFh ROM 1000h
1FFFh ROM 2000h 3FFFh RAM 2000h 2FFFh ROM 3000h 3FFFh ROM 4000h
5FFFh 4000h 4FFFh ROM 5000h 5FFFh ROM 6000h 7FFFh 6000h 6FFFh ROM
7000h 7FFFh ROM 8000h 9FFFh RAM F000h FFFFh A000h BFFFh RAM C000h
DFFFh E000h FFFFh ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb
D7~D0 A12~A0 A14 A15 X A13 Conflict
Slide 90
hsabaghianb @ kashanu.ac.ir Microprocessors 1-90 Partial
Decoding AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory
Chip 0xxx 0000 1111 0000 1111 0000 1111 4k ROM X1x0 X1x1 0000 1111
0000 1111 0000 1111 8k RAM 0000h 1FFFh 0000h 0FFFh ROM 1000h 1FFFh
ROM 2000h 3FFFh 2000h 2FFFh ROM 3000h 3FFFh ROM 4000h 5FFFh RAM
4000h 4FFFh ROM 5000h 5FFFh ROM 6000h 7FFFh RAM 6000h 6FFFh ROM
7000h 7FFFh ROM 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM
E000h FFFFh RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0
A12~A0 A14 A15 X A13 Conflict
hsabaghianb @ kashanu.ac.ir Microprocessors 1-93 1 Bit Memory
With Separated I/O 2147 RWM 4k 1 D out A11~A0 D in 2147 RWM 4k 1 D
out A11~A0 D in 2147 RWM 4k 1 D out A11~A0 D in D0 D1D7 D7-D0
A11-A0
Slide 94
hsabaghianb @ kashanu.ac.ir Microprocessors 1-94 What is the
memory(addr. bit) map D0 2147 RWM 4k 1 D out A11~A0 D in 2147 RWM
4k 1 D out A11~A0 D in 2147 RWM 4k 1 D out A11~A0 D in D1D7 D7-D0
A11-A0 2764 EPROM 8k 8 D7~D0 A12~A0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C
B A G2A G2B G1 0000h-1FFFh 2000h-3FFFh A15 A14 A13 GND VCC
Slide 95
hsabaghianb @ kashanu.ac.ir Microprocessors 1-95 Adding RAM
& ROM
Slide 96
hsabaghianb @ kashanu.ac.ir Microprocessors 1-96 Minimum Z80
Computer System
hsabaghianb @ kashanu.ac.ir Microprocessors 1-98 Z80 Input
Output Z80 at most could have 256 input port and 256 output 8 bit
port address is placed on A7A0 pin to select the I/O device OUT
(n), A n is 8 bit port address Content of A is data OUT (C), r
Content of C is a port address r is a data register IN A, (n) n is
8 bit port address Data is transfered to A IN r (C) Content of Reg
C is a port address Input data is transfered to r (data reg)
hsabaghianb @ kashanu.ac.ir Microprocessors 1-100 Z80 and
simple output port OUT (03), A
Slide 101
hsabaghianb @ kashanu.ac.ir Microprocessors 1-101 Z80 and
simple input port Z80 CPU A14 A0 : D7 D6 RD IORQ A15 D5 D4 D3 D2 D1
D0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IORD 74LS244 A0 A1 A2 A3 A4 A5
A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1G2 5V IN A, (02)
Slide 102
hsabaghianb @ kashanu.ac.ir Microprocessors 1-102 8088 and
simple output port A 1 5 8088 Minimum Mode A18 A0 : D7 D6 IOR IOW
A19 D5 D4 D3 D2 D1 D0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6
A 5 A 4 A 3 A 2 A 1 A 0 IOW 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1
D2 D3 D4 D5 D6 D7 OELE
Slide 103
hsabaghianb @ kashanu.ac.ir Microprocessors 1-103 8088 and
simple input port A 1 5 8088 Minimum Mode A18 A0 : D7 D6 IOR IOW
A19 D5 D4 D3 D2 D1 D0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6
A 5 A 4 A 3 A 2 A 1 A 0 IOW What is this? 74LS244 A0 A1 A2 A3 A4 A5
A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1G2 5V
Slide 104
hsabaghianb @ kashanu.ac.ir Microprocessors 1-104 Simplified
Drawing of 8088 Minimum Mode D7 - D0Q7 - Q0 OE LE 74LS373 D7 - D0Q7
- Q0 OE LE 74LS3738088 AD7 - AD0 A15 - A8 A19/S6 - A16/ S3 DEN DT /
R IO / M RD WR ALE D7 - D4Q7 - Q4 OE LE 74LS373 D3 - D0Q3 - Q0 GND
A7 - A0B7 - B0 E DIR 74LS245 MEMR MEMW IOR IOW A7-A0 A15-A8 A19-A16
D7-D0
hsabaghianb @ kashanu.ac.ir Microprocessors 1-106 What are the
memory locations of a 1MB (2 20 bytes) Memory? A19 to A0 (HEX) AAAA
1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 000000000
FFFFF1111 Example: 34FD0 0011 0100 11111 1101 0000
Slide 107
hsabaghianb @ kashanu.ac.ir Microprocessors 1-107 Minimum Mode
512 kB memory 512 kB Memory D7 - D0 A18 - A0 RD WR Simplified
Drawing of 8088 Minimum Mode D7 - D0 A18 - A0 MEMR MEMW CS A19 What
do we do with A19? 1)Dont connect it 2)Connect to cs What is the
difference?
Slide 108
hsabaghianb @ kashanu.ac.ir Microprocessors 1-108 512 kB Memory
Map Dont connect it A19 is not connected to the memory so even if
the 8088 microprocessor outputs a logic 1,the memory cannot see it.
A19=0 is the same as A19=1 for Memory Connect to cs If A19=0 Memory
chip act normal fanction 00000h 7FFFFh 512k Mem 80000h FFFFFh 512k
Mem 00000h 7FFFFh 512k Mem 80000h FFFFFh Empty
