RECONFIGURABLE MONOCYCLE PULSE BASED UWB TRANSMITTER IN 0.18 μM CMOS FOR

INTRA/INTERCHIP WIRELESS INTER CONNECT S. M. Salahuddin1, Salahuddin Raju2, P. K. Saha3

1Department of Electrical and Electronic Engineering. East West University, Bangladesh.

2Department of Electrical and Electronic Engineering. American International University-Bangladesh, Bangladesh.

3Department of Electrical and Electronic Engineering. Bangladesh University of Engineering and Technology, Bangladesh.

Email: 1sms@ewubd.edu, 2raju@aiub.edu, 3sahapk@eee.buet.ac.bd

Abstract - Ultra wide band (UWB) communication has got special attention as a promising radio technology for networks delivering extremely high data rate with relatively low power consumption at short distance. In this paper we are reporting a new Monocycle Pulse (MCP) generation technique which can be used in a single chip implementation of Impulse Radio based ultra wideband (UWB) transceiver architecture for high speed intra/interchip communication. The proposed MCP based UWB transmitter is implemented in 0.18µm CMOS process. The performance and simulation results of the circuit is presented in this paper. The MCP is found to be reconfigurable; therefore it is possible to control the data rate.

I. INTRODUCTION To provide communication among distant chips with minimum latency, proper interconnection is required. During the past few decades, with the advancement of transistor scaling, interconnect scaling has augmented the distributed resistance-capacitance product which engenders larger latency for a given interconnect length. Scaling of interconnects serves to reduce cost but increases latency and energy dissipation. These increase result from relatively larger average interconnect lengths and larger die sizes for successive generation. So, the chief obstacle in the route of good performance and reduced energy dissipation in future ULSI is undoubtedly the interconnect problem. The time delay in case of global interconnects increases by a square of the factor m where devices and interconnects are scaled down by a factor m. But the local interconnect delay reduced only by a factor of m which again proves that global interconnect is the most dominating one [1]. Presently 60%-70% of the clock cycle is consumed by interconnect delays which is rising with the ever decreasing device size. Sometimes, to reduce the interconnect delay repeater is inserted between the route. This brings increased power consumption and somewhat reduction of delay. Using thicker and wider metal wires, delay can be also reduced but the problem is due to high performance System-on-Chip, optimally

buffered minimum size of global wire is decreasing sharply with technology scaling. Furthermore, wider wires create signal integrity problem, cross talk, delay instability and introduce inductance due to enormous speed. On the contrary, when we increase the spacing to ameliorate the performance, it causes high capacitance and consequently high parasitic effects. To solve the future interconnect problem wireless interconnect technique using integrated antenna was first proposed in [2]. Ultra wide band (UWB) communication systems use signal with bandwidth that is larger than 20 % of center frequency or wider than 500 MHz [3]. Of the different techniques for UWB, carrier free impulse radio based UWB (IR-UWB) technology uses very short low duty cycle pulse which has wide bandwidth and high center frequency [4]. Conventional IR-UWB system use Gaussian monocycle pulse (GMP) which has no dc component. GMP shape is changed due to the differentiation effect of antenna [4]. As a result the received signal will be second derivative of the GMP. Thus the receiver needs the second derivative of GMP as template signal which is difficult to generate. In this paper we propose a new monocycle pulse (MCP) which can be generated from a sinusoidal signal train. Twice differentiation of the sinusoidal signal due to antennas keeps the same wave shape at the receiver side. The proposed MCP shows UWB characteristics and could be reconfigured for the desired MCP center frequency and pulse repetition rate.

II. System Level Simulation of MCP The schematic of proposed MCP based UWB transceiver is shown in Fig 1. and system level simulation of the proposed transceiver is found in [5]. In this paper MCP generation process and circuit is well described. A schematic block diagram of the proposed MCP generation technique is shown in Fig 2. Here voltage controlled oscillator (VCO) is used to generate sinusoidal signal of desired frequency. Output of the VCO is then fed into a comparator, which output works as a clock of a 3 bit

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ring counter. Ring counter generates square wave which duty cycle is equal to the desired MCP’s width. One of the ring counter’s outputs is then multiplied by the VCO’s output to generate MCP. The only complexity of proposed MCP generation is the synchronization of ring counter and VCO due to the inherent circuit delay. Thus VCO output is required to be delayed prior to the multiplication with the ring counter’s output. VCO output can be delayed by using a voltage controlled delay circuit or a properly designed transmission line section.

Fig. 1 Block diagram of MCP based Transceiver The simulation result is shown in Fig. 3. Fig 3(a) shows the 3 GHz sinusoidal VCO output. The ring counter output is given in Fig 3(b). Fig 3(c) shows new MCP which has width of 330 ps and pulse repetition rate of 1 GHz. Thus a maximum data transmission rate of 1 Gbps could be achieved. The generated MCP has also a good symmetry and no ringing. The Fourier transform of the MCP as shown in Fig. 4 depicts that the new MCP has a center frequency of 3 GHz and a -3 dB bandwidth of 2.2 GHz, 73.33% of center frequency which confirms the ultra wideband characteristic of the proposed MCP. The center frequency which is reciprocal of the MCP’s width could be changed by changing the VCO’s control voltage. This makes the reconfigurable MCP generation.

Fig. 2 Block diagram of the proposed MCP generation.

Fig. 3 MATLAB output at different stages of MCP generator circuit

Fig 4. New MCP in frequency domain

III. Circuit Level Simulation A. Voltage Controlled Oscillator: The main block of the designed MCP is the voltage controlled oscillator (VCO) shown in Fig 5 . The VCO is fully differential to minimize the role of noise associated with the system inherently. A varactor diode is used as voltage controlled capacitor to change the operating frequency. Gate length of both nMOS and pMOS set to 0.18µm and width 5.4µm for nMOS and 10.8µm for pMOS. TSPICE simulation Output of VCO is shown in Fig 6.

Fig. 5 Voltage Control Oscillator

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Fig. 6 Output of VCO (3GHz)

B. Comparator:

In this design, a single ended single stage CMOS comparator is used to convert the sinusoidal signal to digital signal which is used as clock for ring counter. Fig. 7 shows the comparator circuit. For buffering and minimize the rise time and fall time output of comparator is directly connected to a buffer.

Fig. 7 Comparator

C. Ring Counter:

The buffered signal is used as clock in ring counter. A three bit ring counter is designed using D flip flop which having the provision of set and preset and these options are active low. Fig 8 shows the ring counter’s building block.

Fig 8. D Flip-flop used in ring counter

Gate pulse generated from the ring counter is used to activate the transmission gate to control the delayed version of sinusoidal signal through transmission gate. Fig 9, Fig 10 and Fig 11 shows the output of transmission gate having different center frequency. For each case peak to peak voltage swing is 1.6 volts. These figures depict that the generated MCP has also a good symmetry and 6.75% ringing due to the following edge of gate pulse used for transmission gate.

Fig 9 Center frequency 2.5 GHz

Fig 10 Center frequency 3.5 GHz

Fig 11 Center frequency 3 GHz

Fig 12 Frequency distribution at 3 GHz

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IV. MCP Performance Comparison Comparison of MCP performance obtained from system level simulation by MATLAB with that obtained from TSPICE simulation is given in Table 1. The table shows a very good agreement of MCP performance obtained from both level of simulation.

Comparison of overall performance of MCP, Gaussian monocycle pulse (GMP) and step recovery diode based GMP is given in table 2. The table 2 depicts that the new MCP shows better performance as compared with that of the other two techniques [6],[7].

Table 1: MCP Performance Comparison System Level Circuit LevelRinging level No ringing -24dB Symmetry 100% 100% Pulse width Reconfigurable ReconfigurableCenter frequency

Reconfigurable Reconfigurable

Peak to Peak amplitude

1.8V 1.6V

3 dB bandwidth 73.33% 56%

Table 2: MCP and GMP Performance Comparison GMP SRD MCP Ringing level

-20.2dB -17dB -24dB

Symmetry Not well balanced

Not well balanced

100%

Pulse width 0.28ns 0.30ns Reconfigurable Center frequency

3.6 GHz -------- Reconfigurable

Peak to Peak amplitude

0.123V 0.2V 1.6V

V. Conclusion The MCP circuit is implemented using TSMC 0.18µm CMOS process. It shows well symmetry and low ringing level. As the proposed MCP is reconfigurable and generated from sinusoidal signal, data rate can be varied by changing VCO’s reference voltage.

References [1] W. J. Dally, “Interconnect Scaling - the real limiter to high performance ULSI” in IEDM Tech. Dig., 1995 pp. 15-17

[2] B A Floyd, C.M. Hung and Kenneth K. O .” A 15 GHz Wireless interconnect implemented in a 0.18μm CMOS technology using integrated transmitters, receivers and antenna ,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.

[3] Federal Communication Commission (FCC), Ultra –Wideband First report and Order, Feb. 2002.

[4] Win M. Z. and Scholtz R. A, “Impulse radio: how it works”, IEEE Communication Letter, 1998,2, pp. 36-38

[5] Salauddin Raju, S. M. Salahuddin, Md Shahidul Islam , P.K. Saha and A. H. M. Zahirul Alam “DSSS IR UWB Transceiver for Intra/ Inter Chip Wireless Interconnect in Future ULSI using Reconfigurable Monocycle Pulse” Proceedings of the International Conference on Computer and Communication Engineering 2008, May 13-15, 2008 Kuala Lumpur, Malaysia pp. 306-309.

[6] Pran Kanai Saha, Nobuo Sasaki and Takamaro Kikkawa, “ A Single-chip Gaussian Monocycle Pulse Transmitter using 0.18 µm CMOS Technology for Intra/Interchip UWB communication”, in Digest of Technical Papers, IEEE Symposium on VLSI Circuits, Hondula, HI, USA, 11-15 June, 2006, pp. 252-253. [7] Jeongwoo Han and Cam Nguyen, “A New Ultra-Wideband, Ultra-Short Monocycle Pulse Generator With Reduced Ringing”, IEEE Microwave and wireless components letters, vol. 12, no 6, 2002, pp 206-208.

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