A Voltage Scaling 0.25-1.8 V Delta-Sigma Modulator with Inverter-Opamp Self-configuring Amplifier

Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, and Hiroki Ishikuro Department of Electronics and Electrical Engineering, Keio University

Yokohama, Japan yoshioka@iskr.elec.keio.ac.jp

Abstract—A 2nd order discrete time (DT) ΔΣ modulator with very wide supply voltage range of 0.25-1.8 V is presented. An inverter-opamp self-configuring amplifier (IOSA) is proposed with sufficient gain through sub-threshold to strong inversion region. The amplifier senses the supply voltage and automatically configures either to operate as an inverter or an opamp. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a best FoM of 0.09 pJ/step. At 1.8 V supply the modulator achieves SNDR 61dB and operates down to 0.25V.

I. INTRODUCTION ADC applications vary from low powered, low speed

sensors for energy harvesting devices and medical devices (requiring BW under 1kHz), to audio and wireless devices with 20k-10MHz of BW. To add on, not only the sensors demand low powered ADCs but thermal energy sourced energy harvesting devices requires the circuit to be operated at supply of 0.25-0.3V. In the recent years, the SAR ADC has been noted for its low power and extremely low voltage performance [1]. Although at the digital domain, SAR ADC’s lowest performable voltage is limited by its complex set & reset flip-flop cells at the register. On the other hand, 1-bit quantization ΔΣ modulator require only NAND based latch as the most complex digital cell, the simplicity allowing further ultra-low voltage operation.

Focusing in the analog domain, a modulator requires switched-capacitor (SC) circuit in addition, which becomes critical at ultra-low voltage operation. As the supply voltage is decreased, the amplifier operation becomes severe. To overcome this problem, a solution using single inverter as an amplifier has been proposed [2,3]. Generally the inverter gain is largest when it operates in the sub-threshold region. However, as the supply voltage rises and after entering the strong inversion region, the gain will eventually degrade damaging the modulator accuracy. Hence, at standard supply voltage high gain opamp are likely to be used.

Past ΔΣ modulator researches can be largely separated into two types: opamp used high voltage operation and inverter used ultra-low voltage modulators. Since these two researches use completely different amplifiers, designing an ADC which can be used in various voltages as SAR ADC in [1], is very challenging.

This work presents an inverter-opamp self-configuring amplifier (IOSA), in which the amplifier operates either as an inverter or an opamp by automatically sensing the power supply voltage. IOSA is embedded in a 2nd order DT ΔΣ modulator, realizing a voltage scaling modulator. The prototype chip fabricated in 180nm CMOS operates at a wide supply voltage of 0.25-1.8V. At 0.3V supply, the modulator achieved peak power efficiency of FoM 0.09 pJ/conv. and SNDR of 53dB. At a supply of 1.8V, the modulator bandwidth (BW) is enlarged to 0.64MHz and SNDR of 61dB.

II. CONVENTIONAL AMPLIFIER As Fig.1 (a) shows, an opamp which has high DC gain is

selected for a standard power supply voltage modulator. However the static bias current of the opamp dominates the power consumption of the modulator. In addition, to obtain high gain, cascode transistors should be used. In order to operate all the transistors at the saturation region, a power supply of VDD > 4Veff is required. In 180nm process design, minimum of VDD > 1.1V is required but when the supply voltage is further decreased, the gain rapidly decreases as in Fig.1 (c).

Fig. 1 (a) Opamp SC circuit (b) Inverter SC circuit

(c) Inverter and opamp operation

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Fig. 2 Schematic of IOSA

Fig. 3 IOSA schematic of opamp mode

Fig. 4 IOSA schematic of inverter mode

In the resent years, modulator using an inverter for the amplifier [2,3] have been reported for extremely low voltage and low power operation as in Fig.1 (b). Essentially inverter is a digital element, but when used as an analog circuit, it has relatively high gain through sub-threshold to weak inversion region (Fig.1 (c)). However, once the inverter enters strong inversion region (VDD > VTHN + VTHP), the gain starts to drop and SC circuit operation becomes difficult.

In addition to inverters, 0.5 V operating opamp has been reported with enough gain for the modulator [4]. However, even though Ref.[4] accomplishes extreme low voltage operation, it is challenging to perform in deeper sub-threshold region, such as supply voltage of 0.25V.

III. IOSA DESIGN In order to design an amplifier which can operate in wide

range of supply voltage, both the advantage of opamp and inverter should be utilized according to the supply voltage. Fig. 2 is the schematic of the proposed IOSA.

Fig. 5 Simulated IOSA gain results

Fig. 6 Hysteresis of the IOSA switching point

The IOSA circuit is based on a folded cascode opamp which has wide output range and its topology is close to an inverter. A. Circuit Operation

A clocked comparator is placed inside the amplifier which detects the supply voltage. The comparator outputs a signal MODE which configures the IOSA to be operated as an inverter or an opamp.

When the MODE signal is low, IOSA operates as a folded cascode opamp as in Fig.3. This operation mode achieves the highest gain and gain bandwidth (GW).

The MODE signal is turned to high when the supply voltage is not high enough for the cascode transistors. IOSA operates as an inverter by configuring the bias either to VDD or VSS to turn off the cascode transistors (MP4-MP7, MN4-MN7). On the contrary, the tail transistors at the folded section (MP3, MN3) are turned on. Fig.4 shows a schematic which removed the transistors that were turned off and the circuit performs as an inverter.

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B. IOSA Gain Fig.5 shows the simulated result of the IOSA’s supply

voltage versus gain. At sub-threshold region below 0.5V, the gain of inverter is maximized. As the supply voltage rises and the circuit enters strong inversion region, the inverter gain falls below 30dB. The gain continues to fall, and at a supply voltage of 1.8V the gain is as small as 20dB. On the other hand, at opamp mode, IOSA does not operate below 1V. As the supply voltage is increased, the IOSA increases its gain and achieves gain over 50dB at higher than 1.2V.

Therefore the amplifier must be designed to change its operation, inverter to opamp, around 1.2V supply to achieve a good modulator performance throughout 0.25-1.8V supply. C. Mode Configuration

The MODE self configuration circuit is implemented in IOSA of the second integrator as in Fig. 2. In this design, the input amplitude swing of the first integrator is large and there is chance of decision error. Therefore, the MODE signal generated in second integrator IOSA is also used to control the IOSA in the first integrator.

The common mode feedback (CMFB) circuit is the first circuit to fail when the supply voltage is decreased. Since the CMFB circuit is basically configured as a differential amp, its output range becomes narrow as the supply voltage drops. If the output feedback exceeds CMFB’s limit, the opamp common mode feedback does not work. When this occurs, the SC circuit fails to operate properly since the amplifier does not form a virtual ground. As a result, the input of the second amplifier leaves away from the sufficient CM (VDD/2). As a consequence, the CM falls down to near ground level turning the input differential NMOS (MN1&MN2) off and the voltage of node A shifts. The comparator detects this event and generates the MODE signal. D. Mode Switching Hysteresis

Fig. 6 shows the modulator MODE configuration hysteresis. When the supply voltage rises (or when switching inverter to opamp), the IOSA switches at 1.25V supply. However, when the supply voltage descends (switching opamp to inverter), the IOSA’s switching point is shifted to 1.15V because of the system’s non-linearity. By this hysteresis characteristic, the IOSA’s stability is guaranteed.

Fig. 8 Chip Photo

IV. MODULATOR DESIGN A. ΔΣ Modulatetor Topology

Fig. 7 shows the structure of the modulator. In this study, to proof the concept of the IOSA, relatively simple 2nd order with 1-bit internal quantizer is chosen instead of higher order. From system level design by Matlab/Simulink, SNDR of over 60dB were to be expected in 2nd order. When the IOSA operates as an inverter, the SC circuit performs with the offset cancelling technique and the CM technique proposed in [3]. B. Switches

When designing extremely low voltage data converters, the switch must be designed carefully. As supply voltage decreases, the switch RON rise and result in enlargement of switch settling time. If enough settling is not given, the modulation accuracy is degraded. To deal with the signal around VDD/2, bootstrapped switches are used for main signal path. On the other hand, the CMOS switches are used for the switches in the feedback path from 1-bit quantizer because the signal is only either VDD or VSS, relaxing the switch much.

V. MEASUREMENT RESULTS The proposed modulator was designed in 180nm CMOS

process. Fig. 8 shows the microphotograph of the chip. The core area is 600um x 700um. Supply voltage versus sampling frequency (Fs) and BW are plotted respectively in Fig.9. The over sampling ratio (OSR) is 64. Fs is set at the maximum frequency at which the SNDR does not degrade. Below 0.5V, Fs rapidly decreases because the amplifier operates at sub-threshold region and the current decreases exponentially.

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Fig. 9 Supply Voltage versus Fs

Fig. 10 Supply Voltage versus SNDR

Fig. 11 16384 plot FFT on various supply voltage

Fig. 10 plots supply voltage versus SNDR. The modulator achieves high SNDR when the amplifier holds high gain at opamp mode. When the IOSA operates in inverter mode, the ΔΣ modulator achieves SNDR of over 50dB even at 0.25V supply. At 0.4V the modulator achieves peak SNDR of 55dB.

The IOSA can also be used for fixed inverter mode or opamp mode by manually controlling the MODE signal. For comparison, inverter mode operation beyond 1.2V is plotted as well in white-painted rectangles. As expected, the SNDR degrades because of the degraded amplifier gain. If the IOSA is used at opamp mode below 1.0V, the SNDR drastically degrades because the opamp gain decreases.

Fig. 11 is the 16384 bin FFT plot on several voltages including the highest and the lowest operating voltage. Fig. 12 plots input signal amplitude versus SNDR. Finally at Fig. 13, supply voltage versus power consumption per MHz and FoM is plotted, respectively. The opamp bias ID is adjusted to match the speed of logic circuits which is a proportion of supply voltage. As a result, the opamp power consumption scales with the voltage and the modulator power consumption

Fig. 12 Input Signal Amplitude versus SNDR

Fig. 13 Supply Voltage versus Power/MHz & FoM

is a proximity of P=CV2. VI. CONCLUSION

A ΔΣ modulator with very wide supply voltage operation range of 0.25-1.8V and with inverter-opamp self-configuring amplifier (IOSA) was proposed. By automatically sensing the supply voltage and operating in either an inverter or opamp, the amplifier holds sufficient gain through sub-threshold region to strong inversion region. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a peak FoM of 0.09 pJ/step. At 1.8V supply the modulator achieves SNDR 61dB and operates down to 0.25V.

ACKNOWLEDGEMENT This work is supported by VLSI Design and Education Center(VDEC), the

University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc..

REFERENCES [1] M. Yip et al, “A resolution-reconfigurable 5-to-10b 0.4-to1V power

scalable SAR ADC,” ISSCC, pp. 190-191, Feb. 2011 [2] F. Michel et al, “A 250 mV 7.5 uW 61 dB SNDR SC ΔΣ Modulator

Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS” JSSC, pp. 709–721, March 2012.

[3] Y. Chae et al, “Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator” JSSC, pp. 458–472, Feb. 2009.

[4] S. Chatterjee et al, “0.5-V Analog Circuit Techniques and Their Application in OTA and Filter Design” JSSC, pp. 2373-2387, Dec. 2005

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