Nickel Induced Crystallization of &-Si Gate Electrode at 500°C and Gate Oxide Reliability

Amol R. Joshi and Krishna C. Saraswat Stanford University

CIS 006, 420 Via Ortega, Stanford, CA 94305-4070, (650) 725-3608

Introduction In this paper we present a study on reliability of

gate oxide during metal induced crystallization (MIC) of amorphous silicon (a-Si) gate electrode with nickel. MIC is attractive for low thermal budget thin film transis- tors [l] and many papers like Lee et al. [2] have reported using Ni MIC to crystallize and activate dopants in gate a-Si. Since Ni is a fast diffuser [3] and deep trap [4] in silicon, it is important to study the effects of Ni MIC on gate oxide and overall capacitor reliability. In order to do that we measured C-V, I-V and charge to breakdown ( Q E D ) data for capacitors and compared with devices which didn’t have Ni. Based on these results we found that Ni did not cause significant degradation of devices.

Experimental PMOS capacitors schematically shown in fig. 1 were

fabricated on n-type crystalline Si substrate using stan- dard LOCOS isolation. Gate dielectric was 10 nm thick thermal Si02 grown at 1000°C. 150 nm thick, in-situ phosphorus doped a-Si gate was then deposited at 550°C by LPCVD. The phosphorus in a-Si was not activated. After gate a-Si patterning, LTO spacers were formed on the sidewalls to prevent Ni deposition on them. On ex- perimental wafer A, 5 nm thick Ni layer was deposited and annealed at 400°C for 4 hours to form silicide. Un- reacted Ni was removed by wet etch. Crystallization annealing conditions for wafer A and control wafers B and C are shown in table I.

Results SIMS showed greater than 2 x 1021/cm3 Ni in gates

of wafer A devices near the top surface and oxide in- terface. Resistivity profiles obtained by Spreading Re- sistance Analysis for wafers A, B and C are shown in fig. 2. Since dopant activation in wafer C is very poor compared to wafers A and B, it was excluded from fur- ther measurements.

C-V plots of 100 pmxlOO pm size capacitors on wafers A and B at low and high frequency are shown in fig. 3 and 4 respectively. Devices on wafer A show a positive V, shift of about 0.15 V indicating a change in gate electrode workfunction and a smaller low frequency ca- pacitance in inversion than wafer B. The slope of C-V curve in the transition region between accumulation and inversion is also lower for wafer A. The reduction in in- version capacitance is neither due to leakage current nor due to gate depletion. From the low and high frequency C-V data for wafer A and B, very little difference in Dit

values was observed. Hence all of the effects mentioned above are probably due to high concentration of Ni in gate electrode.

Capacitor I-V characteristics in fig. 5 and 6 show pos- itive shifts in inversion and accumulation I-V curves of wafer A which also indicate a change in gate electrode workfunction.

Q E D was measured under constant current density of 100 mA/cm2 for substrate (V&) and gate ( V c ) injec- tion of electrons. Fig. 7 shows the cumulative failure plots of Q E D . Wafer A shows highcr Q E D for substrate injection but lower Q B D for gate injection than wafer B. This can be explained using Fowler-Nordheim tunneling model. Under same current injection, device on wafer A , with higher barrier height (4b) for electrons will experi- ence higher oxide electric field and consequently earlier breakdown of gate oxide. Yang et d. [5] have shown that during gate injection of electrons, devices with p+ gates show much lower QBD than devices with n+ gates owing to higher q5b. In caSe of substrate injection, the substrate and hence the db for electrons are the same. So the highcr QBD for wafer A can be attributed to changc in material properties due to large amount of Ni at the gate electrode-oxide interface.

Conclusion Significant effects of Ni MIC of gate a-Si are a change

of about 0.15 eV in the gate workfunction, reduction of low frequency capacitance and some degradation of C-V curve slope all of which probably result from high concentration of Ni in the gate electrode. The leakage currcnts and &BD of Ni and non-Ni devices are of same order of magnitude. So we conclude that Ni does not cause significant degradation of devices during MIC.

References [l] S. W. Lee and S. K. Joo, IEEE Electron Device Lett.,

vol. 17, no. 4, pp. 160-162, 1996. [2] S. W. Lee, T. H. Ihn and S. K. Joo, IEEE Electron

Device Lett., vol. 17, no. 8, pp. 407-409, 1996. [3] R. M. Burger and R. P. Donovan, Fundamentals of

Silicon Integrated Device Technology, vol. 1, Prentice Hall Inc., pp. 232-233, 1967.

[4] S. M. Sze, Physics of Semiconductor Devices, Wiley Eastern Ltd., New Delhi, pp. 21, 1981.

[5] T. C. Yang, P. Sachdev and K. C. Saraswat, IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1457- 1463, 1999.

61

Nickel Seeded

loa 90 80 - e 70-

P I .- 60 a IL

50 .. - B 40-

5 30- 0

20

10

0 -

Table I: Annealing conditions for crystallization of gate a-Si experiment al and control wafers. Wafers B and C do not have any silicide.

r I I Crvstallization Anneal

- - -

- -

- -

(hours)

800 No AND

I Wafer I Ni I Temperature I Time I Ambient I (hours)

A Yes 500 24 2 N? ...

I

AND 1 500 I 24 1 N2+H2

C I N o I 500 I 24 I NzfH2

io4

1 o3 I

. -

0 20 40 60 80 100 120 140 160 180 1 o d f " " " " 1

Depth In PolySi Gate Elenrode (nm)

Figure 2: Spreading resistance profiles in gate stack. Active concentration of P in wafers A and B is approximately 1 x 1OZ0/cm2 and 5 x 10'9/cm2 respectively.

wale, A

IL 10 6 E 5

0 -3 -2 -1 0 I 2 3

Polysilicon Gate Si0 S ace1 Ni \ (n-type) 2 , p -kk$ 4 Thermal SiO, ' c-SiSubstrate

(n-type) Figure 1: Schematic cross section of capacitor on wafer A showing MIC in gate. The big arrow indicates overall di- rection of MIC. Capacitors on wafers B and C have the same structure without Ni.

-3 -2 -1 0 1 2 3 YG (v)

Figure 3: Low frequency C-V overlay. Each of the curves is an average of 10 identical capacitors.

1 04

1 0 . ~ 100 pm X 100 vm

io-' I \

-12 -10 -8 -6 -4 -2 0 v.3 (VI VG (VI

Figure 4 High frequency C-V overlay. Each of the curves is Figure 5: Inversion LV characteristics. Illumination with vis- an average of 10 identical capacitors. ible light was used to get carriers for inversion. Each of the

curves is an average of 30 identical capacitors. iod I I

Water A

Wafer B

10-1'

10.12

2 4 6 8 10 10 1W VG (v) OBD (Cl")

Figure 6: Accumulation I-V characteristics. curves is an average of 30 identical capacitors.

Each of the Figure 7 Q B D for gate and substrate injection of electrons. Illumination with visible light was used during gate injection.

..

62