A Complete 0.5 pm High Performance Array Family

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Y.S. Yung Fujitsu Microelectronics, Inc.

77 Rio Robles San Jose, CA 95134-1807

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Abstract

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A 3.3 V CMOS gate array and embedded array family with 0.5 p drawn channel length and three metal layers has been developed for high performance applications. With internal toggle frequency at 600 MHz, this array family can be designed to handle over 100 MHz, and even up to 200 MHz system speed. In addition, high speed VO’s. tight clock skew control methodology, embedded macros and high performance BGA’s are developed to provide designers a complete solution for high speed system designs.

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I. Introduction

Today in computing applications, engineers are designing systems over 100 MHz operations using CMOS technology. In communications applications,

engineers are shifting to CMOS technology to handlle high speed data transfer, e.g. at SONET STM-1 156 Mb/s, where ECL or GaAs technologies have been use:d traditionally. This gives users a better solution in terms of power dissipation, system integration and cost. Internally, a 0.5 pm drawn channel length CMOlS technology offers toggle frequency up to 600 MHz. This certainly enables CMOS technology to be able to hand!le over 100 MHz system clock speed. However, internial speed alone cannot satisfy all the high speed performance requirements. In addition, high speed I/O’s, tight clock skew control, high performance embedded macros, and high performance packages are also required in order ‘to provide a complete high performance system solution. With all these criteria taken into considerations, a complete high performance 0.5 p m CMOS array family, the CG51 series gate arrays, and the CE51 series embedded arrays, has been developed. Table 1 shows the product summary of this array family.

CG/CE5 1 - Total Gates

I/O Pads Gate Delay

Power Supple Voltages

Packages QFP PGA BGA

Table 1. CG51 and CE51 Series Product Summary

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11. Technology

The CG/CE51 array family is based on Fujitsu’s silicide gate, 0.5 pm drawn channel length CMOS process with 0.45 pm effective channel length. The process is optimized for 3.3V internal core operation, with two or three metal layers for signal and power routing. The width of the main power bus varies according to the frequency of operation.

111. Array Architecture

The array consists of 1/0 pads, 1/0 cells and internal core cells. The 1/0 cells can be used to implement optimized 3.3V or 5V I/Os. A single 1/0 cell can support output current up to 24 mA. If higher output current drive is required, output buffers can be tied in parallel to satisfy the requirement.

The internal core is optimized to operate at 3.3V power supply. An internal basic cell consists of two P-channel and two N-channel transistors. Therefore a single internal cell be used to implement a 2-input NAND or a 2-input NOR gate. The internal gate achieves an ultra fast speed of 210 ps at a typical loading of F/O of 2 and 1 mm wiring length. The power consumption is extremely low; at 1 MHz operating frequency, an internal gate consumes only 1.2 pW. Hence this array family is highly suitable for high frequency, high gate density designs.

Sea-of-Gates architecture is employed for CG51 series gate arrays. CE51 series embedded arrays have the same die sizes and I/O structures as CG51 series gate arrays. The difference is customized hard macros can be designed and implemented in the internal core of CE51 embedded arrays, with the rest of the area filled with internal basic cells. In this case, embedded arrays achieve the performance of standard cells with lead-time similar to gate arrays. Figure 1 shows the die photo of a CE51164 with six blocks of SRAMs.

Fig. 1. Die Photo of a CE51164 with 6 Blocks of SRAMs

IV. High Speed YOs

For frequency up to 66 MHz, the array family offers common interface standards, e.g. LVTTL and PCI I/O buffers at 3.3V or 5V.

For high speed data communications over 100 MHz, Pseudo Current Mode Logic’ (PCML), and Centered Tapped Termination (CTT) 1/0 buffers are available. Especially the PCML buffers are capable of operating at frequencies in excess of 250 MHz.

A typical PCML 1/0 interface circuit is shown in Fig. 1, with extemal resistors R1, R2, and R3, and supplied voltages Vtl, Vt2, Vt3 and Vr. Single ended PCML input buffer can be implemented by connecting Signal- to an extemal reference voltage, Vref, through a Vref pin. Only Vref pin can supply the reference voltage to the PCML input buffers. The on-chip bias circuits are used to generate the necessary references voltages for the PCML output buffers. The bias circuits consist of a main bias circuits and local bias circuits. One main bias circuit

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Vtl

PCML output ; CWCE51

....................................................... ~ ___.._..... )..,.....

Internal Circuit

i PCMLinput I

VOH = Vtl VOL = Vr, if R l = R2 VOL = 2Vr-Vtl, if R1 = R Z 2

Fig. 1. A Typical PCML 1/0 Interface Circuit

can support up to 14 local bias circuits. Each PCML output has one local bias circuit. Each individual PCML input buffer has a terminal (C) to turn off the short circuit current for IDDS testing. External components and external supplied voltages are required for the PCML output buffers. R1 and R2 are termination resistors connected to Vt. For 50 R transmission line, 50 L2 resistors are used at the receiving end, or 100 R resistors are used at both ends of a bus line. There are 3 types of PCML I/O buffers available: a. b. Differential Input Buffer. c. Each type of input buffer has 3 options for Vcenter values: 1.3V, 1.6V and 2.0V. They are intended for the following interfaces: Vcenter = 1.3V: optimized for interfacing with other

Vcenter = 1.6V: C I T levels. Vcenter = 2.0V: PECL levels.

Single-ended Input Buffer with separate Vref input.

Differential Output Buffer, 50 SZ termination.

Fujitsu ASICs with PCML 1/0 buffers.

A unique feature of the PCML buffers is the center (or reference) voltage, and voltage swing are adjustable, hence these PCML 1/0 buffers can be used to interface with other types of I/Os, e.g. PECL, LVTTL,

etc. Interfacing levels, VOL and VOH, can be set as follows: VOH = Vtl, VOL = Vr, VOL = 2Vr - Vtl,

for Vtl = Vt2 and R1= R2; for Vtl = Vt2 and R1 = R212.

V. Clock Skew & DPLL

As performance and gate density go higher and higher, it becomes more critical to be able to control clock skew. This array family comes with Fujitsu’s innovative Clock Driven Design Methodology2 (CDDM) to minimize clock skew. The main idea of CDDM is to allow “small variations within estimated limits” ratlher than pushing for zero skew. CDDM utilizes 3 levels of clock drivers: the main clock driver, the global clock drivers, and the local clock drivers. It supports up to 50,000 F/Fs automatically: and guarantees a maximum of 400 ps between any 2 F/Fs on the same array, 300 ps among F/Fs on the same global clock net, and 165 ps among F/Fs on the same local clock net. The clock componcnts required for CDDM can be incorporatedl in the Register Transfer Level (RTL) description at the system design level. Clock tree can then be developed in

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parallel with logic synthesis. Therefore physical and logical designs occur concurrently at the very early stage.

BGA Packages

Digital Phase Locked Loops (DPLLs) are also available for implementing clock skew control. In addition, DPLLs can be used for clock synthesis, and clock/data recovery where high speed serial data link is used. There are four types of DPLLs available ranging from 92 MHz to 250 MHz.

Dimension eja (OC/W), 1 m/s air (sq. mm) w heat sink w/o heat sink

256 pin (B) 352 pin (B) 416 pin (C)

27x27 16 21 35x35 16 21 40x40 8 14

Table 2. BGA Packages Dimension & Thermal Characteristics

VIII. Conclusion

VI. Embedded Macros

Embedded macros, e.g. diffused RAMs and ROMs are essential for many of the high performance designs. With system clock frequency approaching 100 MHz or above, it is required to have less than 10 ns RAMs and ROMs. This array family has a RAM/ROM compiler that generates a 7 ns, 512 X 20 DP (dual port, lR/lW) RAM. For smaller DP RAMs, the access time will be under 5 ns. Besides dual port RAMs, the compiler can also generate single and triple port RAMs. Other embedded macros, e.g. analog PLL and customized hard macros, can be designed and implemented in the CE51 series embedded arrays.

VII. Packaging

PQFPs (Plastic Quad Flat Packages) have been the most popular CMOS packages up till now, because they are low cost surface mount packages. However, as package pin and power dissipation requirements go up because of wider bus width, higher gate density and higher frequency applications, it is required to offer reasonable size surface mount package with high thermal resistance. BGA (Ball Grid Array) packages are the logical choice. This array family offers QFPs for low cost, low power applications; and BGAs for high performance applications. Table 2 shows the package dimension and thermal resistance of BGA Dackaees.

A 0.5 pm Array Family has been developed with high speed I/O buffers, embedded macros, innovative clock skew control, and high performance packages such that it can offer a complete solution for high performance designs.

References

1. PCML I/Os - 0.5 Micron ASIC Family Application Note, Fujitsu Microelectronics, Inc., ed. 1.0, May 1995.

2. T. Tanizawa and S. Kawahara, “Clock Driven Design Method (CDDM) for Deep Sub-Micron ASICs”, Proceedings of IEEE 1995 AISC Conference & Exhibit, Sept. 1995.

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