Multiple levels of metallization offer possibilities forcircuit designers to route signals over transistors, and thusto reduce the area needed for wiring. We will first discussmultilevel metallization for submicron technologies(0.8, 0.5, 0.35 and 0.25 m) based on aluminum wiringwith tungsten via plugs (Figure 28.1). The intermetal
Figure 28.1 Cross-sectional view of six-level metal struc-ture (M0 is metal zero). Reproduced from Koburger et al.(1995) by permission of IBM
dielectric is oxide, and it is planarized by CMP. We willthen delve into copper metallization which emerged inthe late 1990s. There CMP is used too, but this time topolish copper. While transistors get speedier the smallerthey are, metallization behaves differently: RC time de-lays increase with downscaling because thinner dielectricsincrease capacitance and narrower and thinner wires havehigher resistances.
28.1 Two-Level MetallizationTwo-level metallizations are extensions of one-level met-allizations, with additional dielectric and metal films andonly minor conceptual differences. The process continuesafter first metal as follows:
Process flow for two-level metallization
Intermetal dielectric deposition PECVD oxidePlanarization Spin-on-glass
with etchbackVia hole lithography and etching CHF3 plasma
oxide etchSecond metal deposition TiW/Al
sputteringSecond metal lithography and
etchingPassivation PECVD nitrideBonding pad patterning (litho
and etch)CF4 plasma etch
Introduction to Microfabrication, Second E dition Sami Franssila 2010 John Wiley & Sons, L td. ISBN: 978-0-470-74983-8
358 Introduction to Microfabrication
Contact hole etching of oxide against silicon demandsa highly selective etch process because both oxide andsilicon are etched by fluorine. Contacts between metallevels (known as via holes) are easier from an etchingpoint of view: fluorine-based oxide etching will stop auto-matically once aluminum is reached. Because there ismetal on the wafer, cleaning solutions after via etchingare limited. The second-metal step coverage in the viahole is often critical. Fortunately, via holes are largerthan contact holes, and aspect ratios are therefore smaller.
There are a number of practical aspects in two-levelmetal processes which demand attention. Each additional(PE)CVD step adds to thermal loads, film stresses andplasma damage. Aluminum lines experience thermalexpansion and are under compressive stresses. Thesestresses are relaxed by hillocks: protrusions of aluminumsticking out. Hillocks can sometimes be micrometers high.
Two-level metallization cannot be extended to threelevels because the topography of the wafer becomes morepronounced after each level, and the gap filling capabil-ity of (PE)CVD dielectric deposition as well as sputteringstep coverage in via holes will reach their limits. Pla-narization helps, but it is no panacea: the surface maybecome flat, which eliminates optical lithography depth-of-focus problems, but, as shown below in Figure 28.2,it creates problems in via hole etching and sputtering be-cause holes will be of different depth.
All devices need metallization, and logic circuits usu-ally require the most complex routing, while memoriessuffice with three levels of metal. Even superconductingdevices require multiple levels of metallization if they arecomplex logic circuits (Figure 28.3).
28.1.1 Spin-coated inorganic films
Spin-on-glasses (SOGs) are silicon-containing polymerswhich can be spun and then cured to produce a silicondioxide-like glassy material (they are sometimes knownas SODs, for spin-on dielectrics, which includes polymers,too). Numerous commercial formulations for SOGs exist,adjusted for molecular weight, viscosity and final filmproperties for specific applications. Two basic types ofSOGs are the organic and inorganic. The inorganic SOGsare silicate based and the organics are siloxane based.
Upon curing the reaction at about 400 C silicate SOGsturn into an oxide-like material which is thermally stableand does not absorb water accordingly. They are, how-ever, subject to volume shrinkage during curing, leadingto high stresses (400 MPa). This limits silicate SOGs tothin layers, about 100200 nm. Multiple coating/curingcycles can be used to build up thickness, at the cost ofquite an increase in the number of process steps. Addingphosphorus to SOG introduces changes similar to thephosphorus alloying of CVD oxide films. The resultingfilms are softer and exhibit less shrinkage, and are bet-ter in filling gaps. However, water absorption increases,which results in less stable films. The gap-filling capabil-ity of SOGs is related to viscosity: low viscosity equalsgood gap fill, but, unfortunately, it is correlated with highshrinkage, too.
Organic SOGs based on siloxane (Figure 28.4) do notresult in pure SiO2-like material, but contain carbon evenafter curing. By tailoring the carbon content, the materialproperties can be modified for lower stress (150 MPa)and consequently thicker films. Siloxane films are, how-ever, polymer-like in their thermal stability, and 400 Cis a practical upper limit.
7000 3000 8000 4000 9000 13000
Field oxide N+ OR P+
Figure 28.2 Variable via depth results from planarization. Reproduced from Brown (1986) by permission of IEEE
Multilevel Metallization 359
Wire 1 Wire 2
Ground PlaneJosephson Junction
Legend: Nb SiO2 Nb2O5 Junction Anodization
MoNx5W/sq. ResistorMo/ Al 0.15W/sq. Resistor
Figure 28.3 Multilevel metallization of a superconducting IC. Reproduced from Abelson and Kerber (2004), copyright2004, by permission of IEEE
O Si OCH3
O Si OC2H5CH3X 100~~
Figure 28.4 Structure of siloxane
28.2 Planarized MultilevelMetallizationTrue multilevel metallization starts at three levels ofmetal. Historically this occurred in the late 1980s whensubmicron CMOS technologies were introduced. In0.25 m technology up to six levels of metal are used inASICs and logic chips, three levels in memory chips. Inthe 45 nm technology generation there can be 10 levelsof metal.
A fully planar structure can be created when contact andvia holes are filled by CVD tungsten, and excess tungstenis removed, by etchback or by CMP (Figure 16.1). Thenumber of metal levels can be increased simply by re-peating the process over and over again because all levelsare planar, Figure 28.1.
Back-end process integration differs from that offront-end in the sense that the thermal budget concepthas a very different meaning. Whereas the front-endthermal budget is about the temperaturediffusion rela-tionship, the back-end thermal budget is about thetemperaturestress relation. For n-level metallizationthere will be 2n steps at 300400 C (for each layerCVD tungsten and PECVD oxide steps), with roomtemperature steps (etching, spin coating, CMP) inbetween. Stress, strain, adhesion, hillocks, voids andcracks have to be understood.
28.2.1 Contact/via plug
In order to get planarized metallization, CVD W-plug fillhas been adopted. Because CVD-W has excellent stepcoverage, the via hole will be completely filled. In orderto improve adhesion, a Ti/TiN adhesion layer is depositedbefore tungsten. Excess metal is etched or polished away,leaving a planar surface. The second metal (Ti/TiN/Al) isthen sputtered (Figure 28.5).
The SEM micrograph of Figure 28.6 shows the structureof a planarized multilevel metallization scheme. The topaluminum wiring levels are very planar. Tungsten has beenused for local interconnects (in the length scale 10 m).All dielectric layers have been etched away to reveal themetallization for analysis (e.g., for failure analysis).
360 Introduction to Microfabrication
Figure 28.5 Aluminum bottom metal with Ti/TiN/Wcontact plug after etchback (left) and with secondTi/TiN/aluminum metal layer (right)
Figure 28.6 Multilevel metallization with all dielectriclayers etched away. TiSi2/poly gates, tungsten plugs andlocal wires, Al global wires. Reproduced from Mann et al.(1995) by permission of IBM
When vias can be stacked on top of each other in a mul-tilevel metallization scheme, a lot of area can be saved,and freedom of wire routing increases. In Figure 28.6tungsten plugs can be seen on top of each other. The top-level plugs are somewhat larger than the bottom plugs,ensuring overlap. Misalignment is still there, but becausethe surfaces are planar, it does not lead to topographybuild-up.
28.3 Copper MetallizationAll ICs used aluminum for metallization till 1997, andmost still do, but copper was introduced into high-performance applications from the 0.25 m generationon. Copper resistivity is clearly smaller than that ofaluminum, 1.8 vs. 3 mohm-cm, and like aluminum, itis an exceptional material that thin film resistivity canbe very close to bulk value. However, copper has manydrawbacks and limitations. It diffuses rapidly in both
silicon and silicon dioxide, and new barrier materialshave to be invented. Copper cannot be plasma etched,so it has to be patterned by polishing (CMP). Copper isan impurity that is harmful for silicon transistors, so thewhole process line has to be designed to prevent copperfrom reaching silicon. This means that lithography,etching, CVD, etc., are duplicated for fabricatingfront-end and back-end.