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RECONFIGURABLE RECONFIGURABLE PLATFORM DESIGN PLATFORM DESIGN FOR WIRELESS FOR WIRELESS PROTOCOL PROCESSORSPROTOCOL PROCESSORS

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ABSTRACTABSTRACT

Low-energy protocol processing is a crucial issue in next generation wireless Low-energy protocol processing is a crucial issue in next generation wireless systems. In modern wireless system design, this problem is tightly coupled with the systems. In modern wireless system design, this problem is tightly coupled with the signal processing needs. Fierce market competition and inventive wireless signal processing needs. Fierce market competition and inventive wireless applications are imposing stricter design requirements in energy consumption, cost, applications are imposing stricter design requirements in energy consumption, cost, size and flexibility. To deal with these unique constraints, we incorporate the size and flexibility. To deal with these unique constraints, we incorporate the platform-based design methodology to deal with these constraints by advocating platform-based design methodology to deal with these constraints by advocating reusability. This paper presents this methodology, and its application on PicoRadio, reusability. This paper presents this methodology, and its application on PicoRadio, a cutting-edge wireless system. In particular, we describe the design of a a cutting-edge wireless system. In particular, we describe the design of a reconfigurable architecture optimized for protocol processing.reconfigurable architecture optimized for protocol processing.

IT-SOC 2002 © 스마트 모빌 Lab컴퓨팅

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TABLE OF CONTENTSTABLE OF CONTENTS

1. INTRODUCTION

2. PLATFORM-BASED DESIGN

3. FUNCTIONAL KERNELS OF WIRELESS PORTOCOL STACKS

4. RECONFIGURABLE ARCHITECTURE

5. CONCLUSION

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1. 1. INTRODUCTIONINTRODUCTION

Modern Design ChallengesModern Design Challenges

ProblemsProblems Need for low-cost, small-sizeNeed for low-cost, small-size Need for low-energy, high-throughput protocol processingNeed for low-energy, high-throughput protocol processing Need for high-speed in internetNeed for high-speed in internet Need for a shorter design time and greater design complexityNeed for a shorter design time and greater design complexity

SolutionsSolutions Research of standard in protocol processing Research of standard in protocol processing Finding a new design methodologies Finding a new design methodologies the design of a low-power the design of a low-power

reconfigurable architecture for processing the lower layers of PicoRadio reconfigurable architecture for processing the lower layers of PicoRadio protocol stackprotocol stack

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2. 2. PLATFORM-BASED DESIGN PLATFORM-BASED DESIGN

Concept of platform-based designConcept of platform-based design purposespurposes

Solution of shorter design time and greater design complexitySolution of shorter design time and greater design complexity Satisfaction for low-energy, high-throughput protocol processing and high-Satisfaction for low-energy, high-throughput protocol processing and high-

speed in internetspeed in internet StructureStructure

It consist of three-phase design methodologyIt consist of three-phase design methodology– The first step : The identification of a system platformThe first step : The identification of a system platform

Kernel Extraction via Functional ProfilingKernel Extraction via Functional Profiling Reconfigurable Fabric ExplorationReconfigurable Fabric Exploration

– The second step :The second step : Platform instantiation Platform instantiation Configurable PlatformConfigurable Platform Functional specificationFunctional specification MappingMapping Performance EvaluationPerformance Evaluation

– The final step : implementation of the systemThe final step : implementation of the system ImplementationImplementation

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Figure 1: Three-phase design methodology

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Two facades in making use of platform-based design Two facades in making use of platform-based design methodologymethodology First façadeFirst façade

Identification of the key functions in target application set by using profiling Identification of the key functions in target application set by using profiling techniques. techniques.

Second façadeSecond façade The exploration of architectural moduleThe exploration of architectural module

ExecutionExecution Phase I : Identify a set of possible architectures for the target applicationsPhase I : Identify a set of possible architectures for the target applications Phase II : Explore how effectively the kernel functions are supported by Phase II : Explore how effectively the kernel functions are supported by

these architecturesthese architectures

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3. 3. FUNCTIONAL KERNELS OF FUNCTIONAL KERNELS OF WIRELESS PROTOCOL STACKSWIRELESS PROTOCOL STACKS

The key operations in protocol processingThe key operations in protocol processing Classification in the nature of the algorithmClassification in the nature of the algorithm

Control processingControl processing Data processing Data processing

Data processingData processing Operations are directly on the feed forward path through the Operations are directly on the feed forward path through the

communication pipelinecommunication pipeline Demanding real-time performance constraintsDemanding real-time performance constraints

Control processingControl processing Operation are not directly pathOperation are not directly path Demanding looser timing constraintsDemanding looser timing constraints

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Two facades in making use of platform-based design Two facades in making use of platform-based design methodologymethodology First façadeFirst façade

Identification of the key functions in target application set by using profiling Identification of the key functions in target application set by using profiling techniques. techniques.

Second façadeSecond façade The exploration of architectural moduleThe exploration of architectural module

ExecutionExecution Phase I : Identify a set of possible architectures for the target applicationsPhase I : Identify a set of possible architectures for the target applications Phase II : Explore how effectively the kernel functions are supported by Phase II : Explore how effectively the kernel functions are supported by

these architecturesthese architectures

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4. 4. RECONFIGURABLE FABRICRECONFIGURABLE FABRIC

Definition of architecturesDefinition of architectures A class of architectures that offer a unique balance between hardware and A class of architectures that offer a unique balance between hardware and

software design implementationsoftware design implementation

RequirementRequirement

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FPGA(field programmable gate arrays) FPGA(field programmable gate arrays) CLB(configurable logic block)CLB(configurable logic block) Consist of LUTs and FFs arraysConsist of LUTs and FFs arrays

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PAL(programmable array logic) PAL(programmable array logic) Consist of programmable AND arrays and fixed OR-arraysConsist of programmable AND arrays and fixed OR-arrays

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Comparison Comparison

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Hybrid structure Hybrid structure Mixed the FPGA and PALMixed the FPGA and PAL

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Block diagram of the PAL block in a hybrid block.Block diagram of the PAL block in a hybrid block.

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Block diagram of the FPGA block in the hybrid block.Block diagram of the FPGA block in the hybrid block.

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The integration of the PAL and the FPGA.The integration of the PAL and the FPGA.

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The layout of the macrocell used in the low-energy PAL.The layout of the macrocell used in the low-energy PAL.

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The layout of the PAL used in a hybrid block.The layout of the PAL used in a hybrid block.

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The layout of the FPGA used in a hybrid block.The layout of the FPGA used in a hybrid block.

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The layout of a hybrid block.The layout of a hybrid block.

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5. 5. CONCLUSIONCONCLUSION

PAL is using to implement control logicPAL is using to implement control logic FPGA is using to implement data logicFPGA is using to implement data logic So hibrid architecture consist of PAL and FPGASo hibrid architecture consist of PAL and FPGA

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Normalized area comparison between the hybrid implementation vs. the non-hybrid implementations.Normalized area comparison between the hybrid implementation vs. the non-hybrid implementations.

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APPENDIX AAPPENDIX A

Various operations typically found in the different layers of a wireless protocol stack

Application characteristics

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APPENDIX BAPPENDIX B

TCI low-level protocol in the Cadence VCC |CADENCE| environment, which consist of concurrent, extended finite state machines

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APPENDIX EAPPENDIX E

Basic memory-based programmable logic with AD_OR planes. Each black dot indicates a connection

Programmable Logic Devices