1854 IEEE ‘I’ICANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 11, NOVEMBER 1986

the surface, related to arsenic segregation at the interface, is also drastic: there is a three order of magnitude decrease of I , as, the chemical base doping is raised from 1.3 X IO2’ to 3.2 X lo2’ cr 1 - 3 . The effect of the anneal temperature was investigated at 850 and 900°C: the collector current is smaller by two orders of magntude for the larger temperature. The results, except for the last one. ,are in qualitative agreement with Joe data for similar conditions [2] and illustrate the properties of this device for studying the polysilic on- silicon interface.

This work was supported by Tektronix Inc. and the Jet Propulsion -ab- oratory. [ l] A. Neugroschel et a l . , IEEE Trans. Electron Devices, vol. ED-3; , p.

907, 1985. [2] G. Patton et a l . , “Impact of processing parameters on base curre 11 in

polysilicon contacted bipolar transistors,” in IEDM Tech. Dig., p 30, 1985.

IVB-3 Computer-Aided Optimization of the p-n-p Load R l i M Cells-Osman Ersed Akcasu, Doug Smith, and Chip Barrett-Smilh, Fairchild Semiconductor, 1111 39th Street S . E., P.O. Box 5000, Puyallup, WA 98373.

In this paper we present a computer-aided optimization tech- nique and its application toward various p-n-p load RAM cells. .The inputs to the model are impurity distribution in the entire R..,hM cell, contact configuration, device operating temperature, and 3p- erating conditions in addition to the appropriate boundary C O I di- tions. The two-dimensional device simulator effectively solves the semiconductor carrier transport equations. The output is the 1:V) characteristics, charge integral as a function of operating COI tli- tions as well as current, field, potential and carrier distributicns. These results are used as a quantitative analysis design and o )ti- mization tool for the RAM cell.

Since four out of five junctions in the PNP load RAM cells are in very heavy injection condition and number of unknowns an. in the order of 120 000, efficiency of the solution technique emp1o;n:d is very critical [I] , [2]. A highly convergent nonlinear equal Ion solution technique is used as an alternative to the Newton’s metliod [2]. This allows the transport equations to be solved directly, i n a single step without any incrementation, damping and project .on techniques in less than eight iterations for the RAM cell simtla- tions.

Using the simulator we give the simulation results on the emi ter tie-back in the injector, deep injector, and deep injector and base. We show how the structures operate to cut down substrate inject on dramatically. These are verified with experimental results wh Ic:h are in excellent agreement with simulations. Finally using the sirn- ulator a set of RAM cell approaches with superior performance are investigated and compared to the conventional devices. Const2- quently a new fully self-aligned lateral SCR action RAM cell wh c;h has superior switching characteristics due to approximately ~ O - ~ I X - cent reduction in the stored charge for the same current operat ng condition is discussed. Besides this major advantage, the new Rlil I v l cell is 10 percent smaller in length and gives reduced substrate iind holding currents. The process flow applicable for standard bipollr, and poly processes will be given as well as the discussions on he circuit model followed by various modifications made to the baric structure as explained previously.

[1] 0. E. Akcasu, Solid-state Electron., vol. 27, no. 4, pp. 319-328, 19 3’4. [ 2 ] 0. E. Akcasu, in SIAM Fall Meeting Tech. Dig , , (Tempe AZ, C c t .

1985), pp. A25-A26.

IVB-4 Performance of p-channel Lateral Insulated Gate Transistors-T. P. Chow, D. N . Pattanayak, S. Al-Mayarati, A. L. Robinson, B. J. Baliga, M. S . Adler, and E. J. Wildi, General Electric Company, Corporate Research and Development, Sche- nectady, NY 12301.

The insulated gate transistor (IGT) (or COMFET) is a merged MOS-bipolar power switching device that provides lower on-resis- tance than the conventional MOSFET. Vertical and discrete de- vices with n- and p-type channel of ratings of 10-100 A and 300- 1200 V have been reported. For power integrated circuits, the lat- eral version of this device is more applicable. n-channel 300-V lateral IGT’s (LIGT’s) have also been presented [1]-[3]. To pro- vide a more flexible circuit design, LIGT’s with a p-type channel is also needed.

In this paper, the fabrication and characterization of p-channel, 300-V lateral insulated gate transistors is reported for the first time. Similar to the vertical counterparts, p-channel LIGT’s showed comparable on-resistance as the n-channel ones. Various static de- vice parameters, such as threshold voltage, forward drop, and breakdown voltage, are characterized as a function of doping in the buffer, base, and drift layers and compared with simulated results. One interesting feature in the I-V characteristic of these p-LIGT’s is the presence of a quasi-saturation region similar to that in dis- crete high-voltage bipolar transistors. Turn-off characteristics and SOA performance of these devices are also measured. Several tech- niques of improving SOA performance have been studied. These included use of n+ substrate, sinker or buried layer or a combina- tion of them. Typical devices with a nf substrate and n+ buried layer had a threshold voltage of -6 V, a forward current of 120 A/cm2 at a forward drop of -2 V and a gate voltage of -20 V.

[l] R. Jayaraman, V. Rumennik, B. Singer, and E. Stupp, in IEDM Tech.

[2] A. L. Robinson, D. N. Pattanayak, M. S. Adler, B. J . Baliga, and E.

[3] M. R . Simpson, P. A. Gough, F. I . Hshieh, and V. Rumennik, in

Dig., pp. 258-261, 1984.

J . Wildi, in IEDM Tech. Dig., pp. 144-747, 1985.

IEDM Tech. Dig. , pp. 740-743, 1985.

IVB-5 On-State Characteristics of the MOS-Controlled Thy- ristor (MCT)-V. A. K. Temple and D. N. Pattanayak, General Electric Company, Corporate Research & Development, Schenec- tady , NY.

The MOS-controlled thyristor, as the name implies, is a thyristor that is turned on and off by applying the appropriate voltage to the MOS gate [ I ] . Later work [2] has described this device as a “MOS- gated GTO,” also an appropriate, though unnecessarily restrictive name.

Our first work [ I ] describing MCT capabilities concentrated on the design criteria for turn-off. Forward drops were stated and shown in a first set of test devices to be similar to those of a thy- ristor but the computer modeling used to compare devices was done with a one-dimensional model only. It was assumed, in fact, that device forward drop would be essentially the same as that of the perfect (no emitter shorts) thyristor region of the device. In the actual devices of [I] , however, the p + anode emitter windows were only about 6 percent of the upper surface, leaving some doubt as to the accuracy of the assumption.

This paper gives recent MCT forward drop experimental results which are compared with a computer modeling experiment on var- ious two-dimensional MCT structures. Two-dimensional current flow patterns are ascertained for different structure variations. After looking at the extremely good temperature and electron irradiation dependencies of experimental MCT’s, we broadened our modeling

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 11, NOVEMBER 1986 1855

work to look at MCT forward drop as a function of temperature to 250°C and carrier lifetime from 0.5 to 5 p s .

The results, both modelling and experimental, bear out the con- tention of [ 11 that the MCT forward drop is essentially the same as the one-dimensional thyristor that it contains. In fact, we are pre- pared to go further in predicting that the very small increase in forward drop of the MCT over the perfect thyristor, seen in the modeling work, only 40 mV at 1000 Aicm2, is even less than would occur in present day emitter-shorted thyristors. One might also add, that with the MCT FET channel in the off-state, the MCT holding current is extremely small unless the occasional standard emitter short is included in the device and, further, that MCT turn-on di/dt capability will be very much larger than that of a regular thy- ristor. In addition to improved dildt capability MCT’s should have better dvldt capability. In fact, with the FET channel in the on- state the MCT has a virtually infinite dv/dt capability.

[l] V. A. K . Temple, ‘“OS controlled thyristor,” in ZEDM Tech. Dig., p. 282, 1984.

[2] M. Stoisiek and H. Strack, “MOS GTO-A turn-off thyristor with MOS-controlled emitter shorts,” in ZEDM Tech. Dig. , paper 6.6, 1985.

IVB-6 A 27-Percent Efficient Silicon Solar Cell-Y. Kwark, R. Sinton, J . Gan, and R. M. Swanson, Stanford University, Stan- ford, CA 94305.

By employing light trapping techniques, we have successfully fabricated and tested a silicon point contact concentrator cell with a conversion efficiency of 27 percent, the highest reported for a single junction structure.

An indirect gap semiconductor, silicon is weakly absorbing es- pecially for near-bandgap photons. This requires that silicon cells be relatively thick. However, modeling of the point contact cell indicates that thin structures (less than 80 pm) are necessary to avoid quantum efficiency losses due to auger recombination at high insolation levels [l]. By suitably texturizing the front surface, and by providing a high reflectivity backside reflector, incident photons can be trapped within the photogeneration region of the cell. The effective path length for incident photons can be increased by as much as a factor of 25 thereby greatly increasing the near-bandgap photogeneration. It is important to note that the texturized surfaces need to be well passivated since the surface recombination velocity needs to be kept small in optimized structures.

Conventional cell structures use a full area sintered backside contact; these act as active recombination sinks for photogenerated carriers, and the optical reflectivity of the backside tends to be poor. These limitations are circumvented in the point contact cell which reduces the contacts to a point array on the backside. Most of sur- face of the cell is covered by a high-quality thermal oxide which exhibits low surface recombination velocities and whose thickness can be tailored to enhance reflectance of the backside metal.

Light trapping occurs if phase coherence is lost after one or at most a few photon scattering events [ 2 ] . This requires that the sur- face texture possess sufficient disorder that randomization is as- sured. An anisotropic etch was used to lithographically define a pseudo-random array of pyramids delineated by crystallographic (111) planes on the (100) surface of the cell. The initial concern that the higher recombination activity associated with (1 11) planes (as compared to (100)) coupled with the increased surface area pro- duced by the texturization would lead to a higher surface recom- bination velocity, was unfounded as photoconductivity decay mea- surements showed no significant difference between the planar and textured surfaces.

A 1 10-pm-thick textured cell with a simple thermal oxide for the frontside antireflection layer and using the backside point contact configuration previously reported [3] displayed a conversion effi-

ciency of 27 percent at 100 suns and 26”C, decreasing to 25.7 percent at 300 suns due to series resistance losses in the nonopti- mized metallization grid. The photocurrent (of 415 mA/W (which compares to 380 mAiW for a comparable structure with a double layer antireflection coating but which is not texturized) is the pri- mary reason for the increased efficiency over the last reported result [3]. The care that was taken to maintain the surface passivation, bulk lifetime, and backside reflectivity are primarily responsible for the success of this approach.

R. Swanson, “Point contact silicon solar cells,” EPRI AP-2859, May 1983. E. Yablonovitch and G. Cody, “Intensity enhancement in textured op- tical sheets for solar cells,” IEEE Trans. Electron Devices, vol. ED-29, p. 300, Feb. 1982. R . Sinton, Y . Kwark, P. Gruenbaum, and R . Swanson, “Silicom point contact concentrator solar cells,” presented at the Photovoltaics Spe- cialists Conf., Las Vegas, Oct. 1985.

IVB-7 The Sidewall Resistor-A Novel Test Structure to Re- liably Extract Specific Contact Resistivity-W. M. Loh, P. J . Wright, T . A. Schreyer, S. E. Swirhun, K. C. Saraswat, and J. D. Meindl, Dept. of Electrical Engineering Stanford University, Stan- ford, CA 94305.

An attempt has been made to understand the electrical charac- teristics of Al, PtSi, and CVD W contacts to n i and p+ Si and of A1 contacts to WSi,. We have fabricated conventionally used test structures with contacts as small as 0.3 pm X 0.3 pm and found that for very low values of specific contact resistivity the accuracy is reduced considerably due to the two-dimlensional nature of the current flow. In order to overcome this problem, a new structure has been developed and fabricated.

In our previous work [l], [2], we have examined the test struc- tures commonly used for measuring specifil: contact resistivity. Using two-dimensional numerical simulations, we have accurately predicted the 2-D current crowding effects of these devices. This enables us to extract resistivity to a greater degree of accuracy than that afforded by previous models.

Our 2-D model has been used to analyze the resistance of sub- micron contacts. Using direct-write electron-beam technology, we have successfully fabricated test structures with contact areas as small as 0.3 pm X 0.3 pm and resistance as small as 26 Q. We have also extracted the specific contact resistivity of PtSi, W, and A1 contacts to Si. Our analyses show that for ].ow values of contact resistivity, the measurements become strongly dependent on the geometry of the contact, and relatively insensitive to the actual re- sistivity. Hence it becomes increasingly difficult to accurately ex- tract very low values of resistivity using conventional structures as the contact dimensions are scaled down. These geometrical effects can become noticeable on typical metal-silicon contacts when the resistivity is on the order of Q . cm2 OT less.

A novel test structure which eliminates the problem of current crowding, the sidewall resistor, has been made. This device makes electrical contact to the sidewall of an interconnect, instead of on its top surface. Because the contact is perpendicular to the current path, and because it is the same size as the i!nterconnect stripe, the current is distributed uniformly across the contact. No complicated modelling is necessary, and the measured resistance is given by p , / (contact area). The sidewall resistor is especially useful in mea- suring contacts between levels of interconnect, or between metal and polysilicon. Using an extraction technique similar to that de- scribed by Berger [3], the resistance is measured between two sidewall contacts of varying separation distance. Because contacts are on the side of the interconnect, the contact area can be made to be very small. Hence the resolution of this extraction is governed