Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

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© Digital Integrated Circuits2nd Wires

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

The WireThe Wire

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

July 30, 2002

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The WireThe Wire

transmitters receivers

schematics physical

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Interconnect Impact on ChipInterconnect Impact on Chip

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Wire ModelsWire Models

All-inclusive model Capacitance-only

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Impact of Interconnect Impact of Interconnect ParasiticsParasitics

Interconnect parasiticsreduce reliabilityaffect performance and power consumption

Classes of parasiticsCapacitiveResistiveInductive

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10 100 1,000 10,000 100,000Length (u)

No

of n

ets

(Log

Sca

le)

Pentium Pro (R)Pentium(R) IIPentium (MMX)Pentium (R)Pentium (R) II

Nature of InterconnectNature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnologySGlobal = SDie

Sour

ce: I

ntel

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INTERCONNECTINTERCONNECT

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Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model

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Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

ε=

LLCwire SSS

SS 1=

⋅=

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PermittivityPermittivity

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Fringing CapacitanceFringing Capacitance

W - H/2H

+

(a)

(b)

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Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

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InterwireInterwire CapacitanceCapacitance

fringing parallel

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Impact of Impact of InterwireInterwire CapacitanceCapacitance

(from [Bakoglu89])

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Wiring Capacitances (0.25 Wiring Capacitances (0.25 µµm CMOS)m CMOS)

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Wire Resistance Wire Resistance

W

LH

R = ρH W

L

Sheet ResistanceRo

R1 R2

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Interconnect Resistance Interconnect Resistance

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Dealing with ResistanceDealing with Resistance

Selective Technology ScalingUse Better Interconnect Materials

reduce average wire-lengthe.g. copper, silicides

More Interconnect Layersreduce average wire-length

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PolycidePolycide Gate MOSFETGate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi 2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

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Sheet ResistanceSheet Resistance

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Modern InterconnectModern Interconnect

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Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

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InterconnectInterconnectModelingModeling

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The Lumped ModelThe Lumped Model

Vout

Driver

cwire

VinClumped

RdriverVout

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The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore Delay

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The The EllmoreEllmore DelayDelayRC ChainRC Chain

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Wire ModelWire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

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The Distributed RCThe Distributed RC--lineline

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StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

lta

ge

(V

)

x= L/10

x = L/4

x = L/2

x= L

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RCRC--ModelsModels

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Driving an RCDriving an RC--lineline

Vin

Rs Vout

(rw,cw,L)

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Design Rules of ThumbDesign Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> √ tpgate/0.38rcrc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RCwhen not met, the change in the signal is slower than the propagation delay of the wire

© MJIrwin, PSU, 2000

Documents

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic