Extended Abstracts of the 20th (1988 International) Conference on Solid State Devices and Materials, Tokyo, 1988, pp. 37-40

6000Y Double Gate GTOs

Tsuneo OGURA, Akio NAKAGAWA, Katsuhiko TAKIGAIII,Masaki ATSUTA and Yoshio KAIIEI

Research and Developnent Center, Toshiba Corp.,1, Konukai Toshiba-cho, Saiwai-ku,Kawasaki-shi 2lO, Japan

A double gate GTO, consisting of an n-buffer and a second gate on then-buffer layer, has been developed. A forward blocking voltage of 6000 V wasrealized, even at 150 oC. Turn-off switching power loss can be reduced toapproxinately 1l2O of that for a single gate GTO with the n-buffer and anodeshort structure for an identical n-base width.

1. INTRODUCTION

HiSh power gate turn-off thyristors(GTOs) have received much attention as key

switching devices for high power invertersand choppers. It is desirable to develop

higher power and higher switching frequency

GT0s, to make these power systens smaller,and to inprove energy conversionefficiency. The main problen in satisfyingthese requirenent for the GT0s is a

significant increase in on-state voltageand switching power loss, caused by theincrease in n-base width. In order toattain high blocking voltage sinultaneouslywith low switching power loss, variousdevice structures have already been

proposed 1)-4) . The authors also have

proposed a 6000 V GTO with a combination ofan n-buffer and anode short structure 5).

However, the maximum operational frequency,

even at this GT0, is still limited to lessthan I kHz. In order to attain highblocking voltage simultaneously with low

turn-off switching Loss, a double gate GTO

has been developed and evaluated. The

A-2-4

device was fabricated on a 33 mm diameter

silicon wafer, using conventional diffusionand PEP techniques.

2. EXPERIMENTAL RESULTS

2.7 Forward blocking characteristicsGenerally, there are three GTO

structure categories: reverse blocking,anode short and n-buffer structures. The

n-buffer structure is the most suitable toachieve high frequency operation in hiehblocking voltage GT0s, because the n-basewidth for n-buffer structure is thenarrowest in these three structures 5).

Therefore, the double gate structure has

been cornbined with the n-buffer, os

indicated in Fig.1, A second gate is placedon the n-buffer layer. A forward blockingvoltage of 6000 V was real ized by a SS0 &n

n-base with the n-buffer, even at 1S0 "C,

when the second gate was shorted to theanode electrode, as in Fig.2. This isbecause the hole injection from. thep-euritter layer can be suppressed by

shorting between the second gate and the

37

anode electrode. The maximum allowablejunction tenperature for conventional GTOs

is 725 oC, so that a double Sate GTO can

operate at higher temperature than the

conventional GTOs.

2.2 Turn-off characteristicsIt was found that the turn-off

switching loss can be greatly reduced by

adjusting the tine interval (atd between

two turn-off gate pulse triggering tinesfor the first and second gates. The

turn-off waveforms for three AtG cases are

shown in FiSs.3 (a), (b) and (c),respectively. Figure 3 (a) shows theturn-off waveforms for anode voltage (Va)

and anode current (IA), when only the firstgate is reverse biased at turn-off period.Figure 3 (b) shows the turn-off waveforms

when the first and second gates are

sinultaneously reversed biased. From a

comparison between these two turn-offwaveforms, it can be considered that thesecond gate does not operate effectively toreduce turn-off loss, in case of FiS.3 (b).The turn-off gain (GUip ) for the second

gate is given as

Cgp = 6np4pn+qcnp-l

where ftpn and ecnp are snall-signalcurrent gains for npn and pnp transistorportions of a unit GTO. Generally, qonp has

a snall value, compared with ftrpn , because

the n-base is wider than the p-base.

Therefore, the turn-off gain for the second

gate is snaller than that for the firstgate, and the second gate does not have

sufficient effect on reducing the turn-offloss, in case of simultaneously applyingreverse bias (AtG=0 us) to these two gates,

as shorm in FiS.3 (b) . The turn-offwaveforms for anode voltage, anode current,first gate current (IO<) and second gate

current (Im) for AtG=55 1rs are shown inFig.3 (c). It is clearly seen that the tailcurrent is greatly reduced by adopting a

large AtG, such as 55 1rs. Figure 4 shows

the relation between [t6 and the peak value(Itt) for the tail cument. As is obvious

SECOND GATE ANODE

FiS.l Cross-sectional view ofGTO.

double gate

otl(

l-l

vA =o Ti= l5O oC

Vr, looo v/divIl' O.5 mA ldaV

Fie.2 V-I characteristics at 150 "Cdouble gate GTO, when second gateshorted to anode electrode.

for$tas

t

\ .l) -

7

38

v1 ,5oo v/divIA' 20 AldiV| : 2Q ptldiY

Vq,I1=O

(a) Turn-of.f waveforns for anode voltage(Vn) and anode current (IA), when onlyfirst gate is reverse biased.

Vl '5OO V/diVIl ' 20 A/diV| , lO psldiV

V1 .Is=O

(b) Turn-off waveforns for anode voltageand anode current, when first and secondgates are sinultaneously reverse biased(at6' =o ss) .

Vr '5OO V/diVIl' 20 A/diVI r lO prldiV

V1.I1 -O

Ior=o

Iea'oIer' 20 AldiVIar' 2A Aid,iVI r lO prldiV

(c) Turn-off waveforms for anode voltage,anode current, first gate current (IA<) andsecond gate current (ICn) for trt6 =55 gs.

FiS.3 Turn-off waveforms for double gateGTO.

Iaq'lOO AIcr'65 AGs .O.7 pFRs .2O llTi .25'c

-0 20 40 60 g0

80

60

40

20

FI

Af6 [psl

FiS.4 Peak value fordependence on [t6 for double

tail currentgate GTO.

o.4

Ile'lOO Alj1 '65 ACr .O.? pFRr .2O OTi '25'C

\"\_*

o€ 0.3CIv,

=-,.. 0.2lroUJ

0.1

020406080A16 lpsl

FiS.5 Turn-off switching loss (Emf')dependence on [t6 for double gate GTO.

from this figure, Itl can be reduced by

increasing AtG. From these two figures, itcan be concluded that the second gate can

srlreep away the excess carriers in then-base during turn-off transient by

adopting a large AtG. Turn-off loss (ECIF)

dependence on AtG is shown in FiS.S. Thisfigure also shows that the turn-off losscan be reduced by increasing AtG.

39

2,3 0n-staterelation

voltage and trade-off

The on-state voltage for the doublegate GTO has conpared with that for thesingle gate GTO. Figure 6 shows theexperinental results for the n-base

lifetine (ztU) vs on-state voltage (Vf) forthe double gate GTOs and single gate GTOs

without an anode short portion of identicaln-base width. From this figure, it can be

concluded that the decreasing p-enitterarea, caused by the second gate' portion,does not affect the on-stste voltage in thedouble gate GTO. Figure 7 shows a

conparison in the trade-off relations forthe on-state voltage and turn-off switchingloss between the double gate GTO and thesingle gate GTO with n-buffer and anode

R\short u'. The turn-off switching loss isreduced to approxinately ll20 of that forthe single gate GTO by the double gate

structure. This is because the turn-offloss can be reduced by adjusting the

interval between two gates, in spite of thesecond gate portion not affecting on the

on-state voltage.

V1

tvlao

t.5

FiS.6 On-staten-base lifetineand single gate

40 60 80 r00

rx [psl

voltage (Vf) dependence on(ztU) for double gate GTO

GTO.

t.5oU,,

3CIvt

=ro||.ILo

lrJ

20

0.5

0

Irm'lOO ACr .O.? pFRr .2O OTj '25'c

-a\ft-'/

SIIIGLE GATE GTO

DOUBLE GATE GTO

0 'f.5 2.o 2.5

2.5

vr tvlFiS.7 Trade-off relations between on-statevoltage (Vf) and turn-off switching loss(hFF) for double gate 'GTO and single gateGTO with n-buffer and anode short.

3. CONCLUSION

The double gate GTO, consisting of then-buffer layer and the second gate on then-buffer, has been developed to achieve low

turn-off loss in high blocking voltageGTOs. The forward blocking voltage of 6000

V was realized, even at 150 "C. The

turn-off switching loss can be reduced toapproxinately ll20 of that for the singlegate GTO by adjusting tines for the firstand second gates.

4. REFERENCES

1) T.Nagano, M.Okamura and T.Ogawa:IEEE-IAS Annual Meeting Record (1978) 1003.2) A.Tada, T.Miyajina, H.Hagino andM. Ishida: International Power ElectronicsConf. Record (1983) 54.3) K.Murakami, N.Itazu, Y.Uetake, K.Maseand M.Takeuchi: International PowerElectronics Conf . Record (fgffi) 42.4, M.Azuna, T. Shinohe, K. Takigani andII.Ohashi: 17th Conf . on Solid State Devicesand Mater. (1985) 393.5) T . Ogura, M. Kitagawa, II. 0hashi andA.Nakagawa: 19th Conf. on Solid StateDevices and Mater. (1987) 63.

1

\\E

o,DOUBLE GATE GTO

T,S|NGLE GATE cTo Il.500 A

Ti =25 'c

ol-9ot

40