[Laptrinh.vn]-KyThuatMIMO Va FPGA

8/4/2019 [Laptrinh.vn]-KyThuatMIMO Va FPGA

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Khoa in t Vin thng HCN - HQGHN

M U

K thut MIMO xut hin rt sm t nhng nm 70 do A.R Kaye v D.A

George ra nm 1970 v W. van Etten nm 1975, 1976. Trong qu trnh pht trin,k thut ny khng ngng c ci tin. Vit Nam, do iu kin k thut cng nghcn kh xa vi th gii nn vic nghin cu cng gp nhiu kh khn, c bit l trongqu trnh xy dng v test mt h MIMO. Tuy nhin, vi nm tr li y Vit Nam bt u c tip cn vi mt cng ngh mi. l cng ngh FPGA. Vi cngngh ny th vic xy dng v test mt h MIMO khng cn qu xa vi.

Vi kin thc ca sinh vin nm cui khoa in t - vin thng em quytnh nhn mt ti kha lun lin quan n FPGA vi tn gi Thit k b pht mWalsh cho h o knh MIMO dng cng ngh FPGA vi mc ch tng bc xydng mt h MIMO trong truyn thng v tuyn. Ni dung ca kha lun gm c 4

chng:Chng 1: GII THIU V MIMO v FPGA. Trong chng ny em i vo

gii thiu v h MIMO v nhng nt chnh v FPGA nh khi nim v cu trc caFPGA.

Chng 2: NGN NG V MI TRNG LP TRNH CHO FPGA: giithiu khi qut v ngn ng lp trnh VHDL, Verilog v mi trng lp trnh choFPGA ca hng Xilinx l ISE.

Chng 3: CC C IM C BN CA KIT VIRTEX 4 V CC PHNMM B TR gii thiu v kit FPGA Virtex 4 ca Xilinx cng c s dng trong

qu trnh nghin cu, thc hin ti v cc phn mm b tr nh MATLAB, FUSE,cng c System Generator.

Chng 4: THC HIN M HNH THIT K VI KIT VIRTEX 4. Chngny a ra cch thc hin mt s thit k c th bng MATLAB cng cc cng csn c c cung cp bi Xilinx. Cui cng l kt qu thu c qua m phng v ktqu quan st c trn giao ng k ti li ra ca thit k.

Kha lun tt nghip o Vn Qun K49B1


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CHNG 1: GII THIU V K THUT MIMO V FPGA

1.1. Gii thiu v MIMO

1.1.1. Khi nimK thut MIMO (MIMO technique) trong lnh vc truyn thng l k thut sdng nhiu anten pht v nhiu anten thu truyn d liu. K thut MIMO tn dngs phn tp (khng gian, thi gian, m ha ...) nhm nng cao cht lng tn hiu, tc d liu ... (khc vi khi nim beam forming ca smart aray antenna nhm nngcao li thu, pht theo khng gian...). Tuy vy, hn ch ca k thut MIMO l chi

ph cho thit b cao hn v gii thut x l tn hiu phc tp hn.K thut MIMO ngy nay ang c ng dng rt rng ri: MIMO-Wifi,

MIMO-UMTS ... nh tnh ti u trong vic s dng hiu qu bng thng, tc d dliu cao, robust vi knh truyn fading ... K thut MIMO tng i a dng v phc

tp.

Hnh 1: M hnh mt h MIMO 4x4.

1.1.2. Lch s pht trin

K thut MIMO vi nhng u im y ca n ch mi xut hin cch ykhng lu, nhng nhng khi nim s khai v h MIMO xut hin rt sm t nhngnm 70 do A.R Kaye v D.A George ra nm 1970, v W. van Etten nm 1975,1976.

Gia thp nin tm mi, Jack Winters v Jack Salz lm vic ti Bell Labs a ra nhng ng dng dng k thut to bp sng - c s dng trong h MIMO sauny.

Nm 1993, Arogyaswami Paulraj v Thomas Kailath xut khi nim hp knhkhng gian s dng h MIMO.

Nm 1996, Greg Raleigh v Gerard J.Foschini a ra phng php mi s dngk thut MIMO da trn vic biu din dung nng nh hm ph thuc vo s anten thu

pht.

Kha lun tt nghip o Vn Qun K49B

S/P

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S4,S3,S2,S1(Cc k hiu truyn)

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http://tudiencongnghe.com/Special:Search/MIMOhttp://tudiencongnghe.com/Special:Search/UMTShttp://tudiencongnghe.com/Special:Search/MIMOhttp://tudiencongnghe.com/Special:Search/UMTS


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Nm 1998, ln u tin trong lch s Bell Labs chng minh th nghim m hnhhp knh khng gian (SM).

Nm 2001, sn phm thng mi u tin s dng cng ngh MIMO OFDMAc a ra th trng bi hip hi Iospan Wireless Inc. Sn phm ny h tr c m

phn tp v hp knh khng gian.Nm 2006, mt s cng ty vin thng ln (Beceem Communicatios, Samsung,

Runcom Technology ) tp trung pht trin k thut MIMO OFDMA lm gii phpcho chun di ng bng rng WIMAX IEEE 802.16e. Cng trong nm 2006 mt scng ty (Broadcom, Intel ) pht trin k thut MIMO OFDM chun b cho k thutWiFi theo chun IEEE 802.11n.

Trong tng lai k thut MIMO vn cn rt quan trng trong h 4G, v vn angc nhiu nh nghin cu quan tm pht trin.

1.1.3. Phn loi

MIMO c th chia thnh 3 mng chnh: M trc (Precoding), hp knh khnggian SM, v m phn tp.

M trc l cch to bp sng nhiu lp. Trong cch to bp sng n lp mianten pht s pht cc tn hiu ging nhau vi cc trng s pha thch hp cc icng sut ti u thu. Kt qu t to bp sng lm tng h s cng sut thng qua cutrc tng hp, v lm gim hiu ng fading do a ng. Nu mi trng khng ctn x th cch to bp sng ny rt c hiu qu. Nhng tht khng may nhng hthng trong thc t u khng nh vy. Khi s dng nhiu anten nhn th bn phtkhng th to bp sng cc i tn hiu trn tt c cc anten nhn. Khi m trc

cn c s dng. Trong k thut ny, nhiu lung tn hiu c lp c pht ngthi t cc anten pht vi cc trng s thch hp sao cho thng lng ti b thu cci. M trc yu cu bn pht phi bit thng tin trng thi knh (CSI).

Hp knh khng gian: yu cu cu hnh anten ph hp. Trong hp knh khnggian, tn hiu tc cao c chia thnh nhiu lung tc thp hn, mi lung c

pht bi mt anten khc nhau trn cng mt bng tn. Nu cc lung tn hiu ny nb thu c s khc bit k hiu khng gian thch hp th b thu c th tch bit cclung ny, to thnh cc knh song song. Hp knh khng gian rt hu hiu lm tngdung nng ng k trong trng hp t s SNR cao. S lung khng gian cc i ng

bng hoc nh hn s anten nh nht bn pht v bn thu. Hp knh khng giankhng yu cu bn pht phi bit knh.

M phn tp l k thut khi bn pht khng bit thng tin trng thi knh. Khngnh k thut SM, m phn tp ch pht i mt lung tn hiu c m ho theo k thutc gi l m khng thi gian. Cc anten pht tn hiu m ho trc giao. K thut

phn tp khai thc tnh c lp ca fading trong h nhiu anten nng cao s phntp ca tn hiu. V bn pht khng bit knh nn m phn tp khng to bp sng.

Trong thc t ngi ta c th kt hp k thut hp knh khng gian vi m trckhi bn pht bit trng thi knh, hoc kt hp vi m phn tp trong trng hpngc li.



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1.1.4. ng dng ca MIMO

Li ch chnh ca h MIMO l tng ng k tc d liu v tin cy ca knhtruyn. K thut hp knh khng gian i hi phc tp ca b thu, do n thngc kt hp vi k thut hp knh phn chia theo tn s trc giao (OFDM), hoc

OFDMA. Chun IEEE 802.16e kt hp cht ch vi k thut MIMO OFDMA vchun IEEE 802.11n s dng MIMO OFDM.

H MIMO cng c s dng trong chun di ng 3GPP v 3GPP2 v angc pht trin k thut truyn thng MIMO nng cao nh l k thut xuyn lp, kthut nhiu ngi dng v ad hoc trong MIMO.

Xuyn lp MIMO gii quyt cc vn xuyn lp xy ra trong h thng MIMO,do lm tng hiu qu s dng knh. K thut xuyn lp ny cng lm tng hiu qus dng knh SISO. Cc k thut xuyn lp thng gp l iu ch v m ho thchnghi (AMC), lin kt thch nghi.

MIMO nhiu ngi dng c th khai thc s giao thoa cng sut ca nhiu ngis dng nh l mt ti nguyn khng gian cho k thut x l pht tin tin, cn trongch mt ngi dng, h MIMO ch s dng nhiu anten. V d cho x l pht tintin ca h MIMO nhiu ngi dng l giao thoa lin quan n m trc.

Ad hoc MIMO l mt k thut rt hu dng cho mng t bo tng lai, n tptrung vo mng v tuyn mt co hay mng v tuyn ad hoc. Trong mng ad hocnhiu nt pht lin lc vi nhiu nt thu. c th ti u dung nng ca knh Ad hoc, khi nim v k thut MIMO c p dng cho cc lin kt trong cm nt thu v

pht. Khng ging vi h anten trong h MIMO mt ngi dng, cc nt ny c tnh mt hng phn b. t c dung nng trong mng ny cn qun l s phn bti nguyn sng v tuyn hiu qu nh s hot ng ng thi ca cc nt v khinim m trang nhim bn.

Tm li, h MIMO vi nhng k thut phn tp, m trc v nhiu ngi dnglm tng ng k tc d liu v tin cy knh truyn, ang rt c quan tmnghin cu pht trin ha hn m li cho chng ta nhiu li ch hn na trong truynthng v tuyn.

1.2. Gii thiu v FPGA

1.2.1. Khi nim

Field-programmable gate array (FPGA) l vi mch dng cu trc mng phnt logic m ngi dng c th lp trnh c. (Ch field y mun ch n kh nngti lp trnh bn ngoi ca ngi s dng, khng ph thuc vo dy chuyn sn xut

phc tp ca nh my bn dn). Vi mch FPGA c cu thnh t cc b phn (hnh2):

Cc khi logic c bn lp trnh c (logic block).

H thng mch lin kt lp trnh c.

Khi vo/ra (I/O Pads).

Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...

http://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/wiki/RAMhttp://vi.wikipedia.org/wiki/ROMhttp://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/wiki/RAMhttp://vi.wikipedia.org/wiki/ROM


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Hnh 2: Cu trc c bn ca FPGA

FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhngnu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vinlogic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trongkh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit hn chc th ti cu trc li khi ang s dng, cng on thit k n gin do vy chi phgim, rt ngn thi gian a sn phm vo s dng.

Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trcmng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v tilp trnh ca FPGA thc hin n gin hn; kh nng lp trnh linh ng hn; v khc

bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha khi lng

ln cng logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n.Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m

t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln nhXilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnhthit k, cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny nhSynopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bcca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi lm RTL).

FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty Xilinx

vo nm 1984, kin trc mi ca FPGA cho php tnh hp s lng tng i ln ccphn t bn dn vo mt vi mch so vi kin trc trc l CPLD. FPGA c khnng cha ti t 100.000 n hng vi t cng logic, trong khi CPLD ch cha t10.000 n 100.000 cng logic; con s ny i vi PAL, PLA cn thp hn na cht vi nghn n 10.000.

CPLD c cu trc t s lng nht nh cc khi SPLD (Simple programabledevices, thut ng chung ch chung ch PAL, PLA). SPLD thng l mt mng logicAND/OR lp trnh c c kch thc xc nh v cha mt s lng hn ch cc

phn t nhng b (clocked register). Cu trc ny hn ch kh nng thc hin

http://vi.wikipedia.org/wiki/ASIChttp://vi.wikipedia.org/wiki/ASIC#ASIC_.C4.91.E1.BA.B7c_ch.E1.BA.BF_ho.C3.A0n_to.C3.A0nhttp://vi.wikipedia.org/wiki/ASIC#ASIC_thi.E1.BA.BFt_k.E1.BA.BF_tr.C3.AAn_th.C6.B0_vi.E1.BB.87n_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_thi.E1.BA.BFt_k.E1.BA.BF_tr.C3.AAn_th.C6.B0_vi.E1.BB.87n_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_d.E1.BB.B1a_tr.C3.AAn_m.E1.BA.A3ng_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_d.E1.BB.B1a_tr.C3.AAn_m.E1.BA.A3ng_logichttp://vi.wikipedia.org/wiki/PLAhttp://vi.wikipedia.org/w/index.php?title=PAL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=CPLD&action=edit&redlink=1http://vi.wikipedia.org/wiki/FPGAhttp://vi.wikipedia.org/w/index.php?title=C%E1%BB%95ng_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=HDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=VHDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Verilog&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=AHDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Xilinx&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Altera&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Synopsys&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Synplify&action=edit&redlink=1http://vi.wikipedia.org/wiki/IChttp://vi.wikipedia.org/w/index.php?title=RTL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Ross_Freeman&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=CPLD&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=SPLD&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Ph%E1%BA%A7n_t%E1%BB%AD_nh%E1%BB%9B&action=edit&redlink=1http://vi.wikipedia.org/wiki/ASIChttp://vi.wikipedia.org/wiki/ASIC#ASIC_.C4.91.E1.BA.B7c_ch.E1.BA.BF_ho.C3.A0n_to.C3.A0nhttp://vi.wikipedia.org/wiki/ASIC#ASIC_thi.E1.BA.BFt_k.E1.BA.BF_tr.C3.AAn_th.C6.B0_vi.E1.BB.87n_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_thi.E1.BA.BFt_k.E1.BA.BF_tr.C3.AAn_th.C6.B0_vi.E1.BB.87n_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_d.E1.BB.B1a_tr.C3.AAn_m.E1.BA.A3ng_logichttp://vi.wikipedia.org/wiki/ASIC#ASIC_d.E1.BB.B1a_tr.C3.AAn_m.E1.BA.A3ng_logichttp://vi.wikipedia.org/wiki/PLAhttp://vi.wikipedia.org/w/index.php?title=PAL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=CPLD&action=edit&redlink=1http://vi.wikipedia.org/wiki/FPGAhttp://vi.wikipedia.org/w/index.php?title=C%E1%BB%95ng_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=HDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=VHDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Verilog&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=AHDL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Xilinx&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Altera&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Synopsys&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Synplify&action=edit&redlink=1http://vi.wikipedia.org/wiki/IChttp://vi.wikipedia.org/w/index.php?title=RTL&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Ross_Freeman&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=CPLD&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=SPLD&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Ph%E1%BA%A7n_t%E1%BB%AD_nh%E1%BB%9B&action=edit&redlink=1


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nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph thuc vocu trc c th ca vi mch hn l vo yu cu bi ton.

Kin trc ca FPGA l kin trc mng cc khi logic, khi logic, nh hn nhiunu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha nhiu hn

cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t logic v hthng mch kt ni, t c mc ch ny th kin trc ca FPGA phc tp hnnhiu so vi CPLD.

Mt im khc bit vi CPLD l trong nhng FPGA hin i c tch hpnhiu nhng b logic s hc s b ti u ha, h tr RAM, ROM, tc cao, hayccb nhn cng (multication and accumulation, MAC), thut ng ting Anh l DSPslice dng cho nhng ng dng x l tn hiu s DSP.

Ngoi kh nng ti cu trc vi mch ton cc, mt s FPGA hin i cn h trti cu trc cc b, tc l kh nng ti cu trc mt b phn ring l trong khi vn m

bo hot ng bnh thng cho cc b phn khc.1.2.2. ng dng

ng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng khng,v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), cc h thng iukhin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m hc, m hnh

phn cng my tnh...

Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lpnhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi ranh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi

lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.Khi logic

Phn t chnh ca FPGA l cc khi logic (logic blocks). Khi logic c cuthnh t LUT v mt phn t nh ng b flip-flop, LUT (Look up table) l khi logicc th thc hin bt k hm logic no t 4 u vo, kt qu ca hm ny ty vo mcch m gi ra ngoi khi logic trc tip hay thng qua phn t nh flip-flop.

Hnh 3: Khi logic trong FPGA

Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi nimSLICE, mt Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t vinghn n vi chc nghn ty theo loi FPGA.


Look UpTable(LUT)

Flip-Flop

Input

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http://vi.wikipedia.org/wiki/FPGA#Kh.E1.BB.91i_logichttp://vi.wikipedia.org/w/index.php?title=B%E1%BB%99_nh%C3%A2n_c%E1%BB%99ng&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP&action=edit&redlink=1http://vi.wikipedia.org/wiki/ASIChttp://vi.wikipedia.org/w/index.php?title=C%E1%BB%95ng_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Flip-flop&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=LUT&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=SLICE&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_logic&action=edit&redlink=1http://vi.wikipedia.org/wiki/FPGA#Kh.E1.BB.91i_logichttp://vi.wikipedia.org/w/index.php?title=B%E1%BB%99_nh%C3%A2n_c%E1%BB%99ng&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slice&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP&action=edit&redlink=1http://vi.wikipedia.org/wiki/ASIChttp://vi.wikipedia.org/w/index.php?title=C%E1%BB%95ng_logic&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Flip-flop&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=LUT&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=SLICE&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_logic&action=edit&redlink=1


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Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h trthm 2 u vo b xung t cc khi logic phn b trc v sau n nng tng s uvo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic.

1.2.3. H thng mch lin kt

Khi chuyn mch ca FPGA l mng lin kt trong FPGA c cu thnh tcc ng kt ni theo hai phng ngang v ng, ty theo tng loi FPGA m ccng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c3 loi kt ni: ngn, di v rt di. Cc ng kt ni c ni vi nhau thng qua cckhi chuyn mch lp trnh c (programable switch), trong mt khi chuyn mchcha mt s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tpkhc nhau.

1.2.4. Cc phn t tch hp sn

Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch

hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5 caXilinx c cha nhn s l PowerPC, hay trong Atmel FPSLIC tch hp nhn ARV,hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp cc DSPSlice lb nhn cng tc cao, thc hin hm A*B+C, v d dng Virtex ca Xilinxcha t vi chc n hng trm DSP slices vi A, B, C 18-bit.

Ngy nay ngnh cng ngh ch to phn cng lun c nhng t ph khngngng. T cc mch in n gin n cc mch s, mch tch hp, kin trc mchtr nn ngy mt phc tp hn. Nh nhng u im hn hn so vi cc phng php

phn tch, m hnh ho, thit k mch s kiu truyn thng m phng php sdng cc ngn ng m phng phn cng (HDL - Hardware Description Languages)ang tr thnh mt phng php thit k cc h thng in t s ph bin trn tonth gii. Trong kha lun ny em xin gii thiu hai loi ngn ng m phng phn cng l VHDL (Very high speed intergrated circuit Hardware Description Language) vVerilog l hai ngn ng ch yu c s dng m phng phn cng trong cngngh CPLD, FPGA, ASIC

Nhng u im ca phng php thit k h thng s bng ngn ngm phng phn cng (HDL).

Ngy nay, cc mch tch hp ngy cng thc hin c nhiu chc nng do m vn thit k mch cng tr nn phc tp. Nhng phng php truyn thngnh dng phng php ti thiu ho hm Boolean hay dng s cc phn t khngcn p ng c cc yu cu t ra khi thit k. Nhc im ln nht ca cc

phng php ny l chng ch m t c h thng di dng mng ni cc phn tvi nhau. Ngi thit k cn phi i qua hai bc thc hin hon ton th cng: l chuyn t cc yu cu v chc nng ca h thng sang biu din theo dng hmBoolean, sau cc bc ti thiu ho hm ny ta li phi chuyn t hm Boolean sangs mch ca h thng. Cng tng t khi phn tch mt h thng ngi phntch cn phi phn tch s mch ca h thng, ri chuyn n thnh cc hmBoolean, sau mi lp li cc chc nng, hot ng ca h thng. Tt c cc bcni trn hon ton phi thc hin th cng khng c bt k s tr gip no ca my

http://vi.wikipedia.org/w/index.php?title=H%C3%ACnnh:switch_box.svg&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_chuy%E1%BB%83n_m%E1%BA%A1ch&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=PowerPC&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=ARV&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_Slide&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_Slide&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=B%E1%BB%99_nh%C3%A2n_c%E1%BB%99ng&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slices&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=H%C3%ACnnh:switch_box.svg&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=Kh%E1%BB%91i_chuy%E1%BB%83n_m%E1%BA%A1ch&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=PowerPC&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=ARV&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_Slide&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_Slide&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=B%E1%BB%99_nh%C3%A2n_c%E1%BB%99ng&action=edit&redlink=1http://vi.wikipedia.org/w/index.php?title=DSP_slices&action=edit&redlink=1


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tnh. Ngi thit k ch c th s dng my tnh lm cng c h tr trong vic v s mch ca h thng v chuyn t s mch sang cng c tng hp mch vt ldng cng c Synthesis. Mt nhc im khc na ca phng php thit k truynthng l s gii hn v phc tp ca h thng c thit k. Phng php dnghm Boolean ch c th dng thit k h thng ln nht biu din bi vi trm hm.Cn phng php da trn s ch c th dng thit k h thng ln nht chakhong vi nghn phn t.

Phng php thit k, th nghim, phn tch cc h thng s s dng cc ngnng m t phn cng ni bt ln vi cc u im hn hn v s dn thay th cc

phng php truyn thng. S ra i ca ngn ng m phng phn cng gii quytc rt nhiu nhc im ln ca cc phng php thit k trc y: Nu cc

phng php c i hi phi chuyn i t m t h thng (cc ch tiu v chcnng) sang tp hp cc hm logic bng tay th bc chuyn hon ton khng cnthit khi dng HDL. Hu ht cc cng c thit k dng ngn ng m phng phn

cng u cho php s dng biu trng thi (finite-state-machine) cho cc h thngtun t cng nh cho php s dng bng chn l cho h thng tng hp. Vicchuyn i t cc biu trng thi v bng chn l sang m ngn ng m phng

phn cng c thc hin hon ton t ng.

Nh tnh d kim tra th nghim h thng trong sut qu trnh thit k mngi thit k c th d dng pht hin cc li thit k ngay t nhng giai on u,giai on cha a vo sn xut th, do tit kim c lng chi ph ng k bit tng thit k n to ra sn phm ng nh mong mun l mt vic rt khtrnh khi nhng kh khn, tht bi.

Khi mi lnh vc ca khoa hc u pht trin khng ngng th s phc tp cah thng in t cng ngy mt tng theo v gn nh khng th tin hnh thit k thcng m khng c s tr gip cu cc loi my tnh hin i. Ngy nay, ngn ngm t phn cng HDL c dng nhiu thit k cho cc thit b logic lp trnhc PLD t loi n gin n cc loi phc tp nh ma trn cng lp trnh cFPGA.



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CHNG 2: NGN NG V MI TRNG LP TRNH CHO FPGA

2.1. Ngn ng lp trnh cho FPGA

2.1.1 Gii thiuC nhiu ngn ng c th lp trnh cho FPGA nh VHDL, Verilog, C Mingn ng li c u nhc im ring. V d nh Verilog l ngn ng c pht trinv s dng ch yu M. y l mt ngn ng rt gn vi C, chnh v vy s rtthun tin cho ai quen lp trnh vi ngn ng C. Tuy nhin, chu u th ngita li quen dng VHDL hn. u im ca ngn ng ny l ngi lm vic vi n sc ci nhn rt thu o v phn cng. Trong chng ny em xin c gii thiu chyu v v ngn ng VHDL ngn ng m em tm hiu trong qu trnh hc tp vlm thc nghim vi FPGA trn phng SIS (Smart Integrated Systems) v a ra vint gii thiu khi qut v Verilog cng l mt ngn ng rt thng dng i vi lp

trnh FPGA hin nay.2.1.2. Ngn ng VHDL

2.1.2.1. Khi nim

VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mtloi ngn ng m t phn cng c pht trin dng cho chng trnh VHSIC (VeryHigh Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trinVHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho

php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc hthng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics,

IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm 1983. Phinbn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chcIEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL(tiu chun IEEE-1076-1987).

VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay iv lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti lium t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu k lng tiliu . Vi mt ngn ng m phng phn cng tt vic xem xt cc ti liu m ttr nn d dng hn v b ti liu c th c thc thi m phng hot ng ca

h thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trongmt m hnh thng nht.

VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit kc th t do la chn cng ngh, phng php thit k trong khi ch s dng mtngn ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc k ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc:

- Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnhph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh

sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng.



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- Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDLcho php thit k bng nhiu phng php v d phng php thit k t trn xung,hay t di ln da vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng cxy dng mch nh s dng cng ngh ng b hay khng ng b, s dng ma trnlp trnh c hay s dng mng ngu nhin.

- Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng nghch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th cchuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch to phncng mi ra i n c th c p dng ngay cho cc h thng thit k.

- Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phncng t mc h thng s cho n mc cng. VHDL c kh nng m t hot ng cah thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mimc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m tchi tit.

- Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chpnhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu chunVHDL. Cc kt qu m t h thng c th c trao i gia cc nh thit k s dngcng c thit k khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mtnhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thngln (trong cc h con c thit k c lp).

- Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thitk: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th cs dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bntrong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia sthit k. V n cng cho php dng li cc phn c sn.

2.1.2.2. Cu trc mt m hnh h thng m t bng VHDL

Mc ch ca phn ny l nhm gii thiu s qua v cu trc khung c bn caVHDL khi m t cho mt m hnh thit k thc. Thng thng mt m hnh VHDL

bao gm ba phn: thc th (entity), kin trc (architecture) v cc cu hnh. i khi tas dng cc gi (packages) v m hnh kim tra hot ng ca h thng (testbench).

+ Thc th (entity)

y l ni cha cc khai bo thc th (l cc port giao tip gia FPGA v cc tnhiu bn ngoi cc port ny c s dng nh l lp v ca kin trc thit k) v c

th bao gm cc ty chn generic l khai bo chung c th d dng sa i khi cn.+ Kin trc (architecture)

Phn th hai trong m hnh VHDL l khai bo kin trc ca chng trnh. Mimt khai bo thc th u phi i km vi t nht mt kin trc tng ng. VHDLcho php to ra hn mt kin trc cho mt thc th. Phn khai bo kin trc c th

bao gm cc khai bo v cc tn hiu bn trong, cc phn t bn trong h thng, haycc hm v th tc m t hot ng ca h thng. Tn ca kin trc l nhn ct tu theo ngi x dng. C hai cch m t kin trc ca mt phn t (hoc hthng) l m hnh hot ng (Behaviour) hay m t theo m hnh cu trc

(Structure). Tuy nhin mt h thng c th bao gm c m t theo m hnh hot ng



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v m t theo m hnh cu trc.

+ M t kin trc theo m hnh hot ng

M hnh hot ng m t cc hot ng ca h thng (h thng p ng vi cctn hiu vo nh th no v a ra kt qu g u ra) di dng cc cu trc ngnng lp trnh bc cao. Cu trc c th l PROCESS, WAIT, IF, CASE, FOR-LOOP

+ M t kin trc theo m hnh cu trc

M hnh cu trc ca mt phn t (hoc h thng) c th bao gm nhiu cpcu trc bt u t mt cng logic n gin n xy dng m t cho mt h thnghon thin. Thc cht ca vic m t theo m hnh cu trc l m t cc phn t con

bn trong h thng v s kt ni ca cc phn t con . Nh vi v d m t mhnh cu trc mt flip-flop RS gm hai cng NAND c th m t cng NAND cnh ngha tng t nh v d vi cng NOT, sau m t s mc ni cc phn t

NAND to thnh trig RS.

+ Cu trc process

Process l khi c bn ca vic m t theo hot ng. Process cxt n nh l mt chui cc hnh ng n trong sut qu trnh dch.

Hnh 4: Cu trc process

S: M hnh cu trcB: M hnh hot ng

S/B: M hnh kt hp

Cu trc tng qut

[Process label]

Process [(sensitive_list )]

Process declarative part

Begin


S

S B

SS/BS

B B B B B B

11


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.

End process

Trong cc phn t trong du [ ] th c th c hoc khng.

- process_label: (nhn lnh) l tu thuc ngi lp trnh t tn- sensitivity_list: Danh sch cc yu t kch thch hot ng.

+ Mi trng kim tra (testbench)

Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tramt m hnh VHDL c thc hin bng cch quan st hot ng ca n trong khim phng v cc gi tr thu c c th em so snh vi yu cu thit k.

Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kimtra sinh ra cc tc ng ln bn thit k v cho php quan st hoc so snh kt quhot ng ca bn m t thit k. Thng thng th cc bn m t u cung cp

chng trnh th. Nhng ta cng c th t xy dng chng trnh th (testbench).Mch th thc cht l s kt hp ca tng hp nhiu thnh phn. N gm ba thnh

phn. M hnh VHDL qua kim tra, ngun d liu v b quan st. Hot ng cam hnh VHDL c kch thch bi cc ngun d liu v kim tra tnh ng nthng qua b quan st.

Hnh 5: S khi ca Testbench

Trong : DUT: (device under test) m hnh VHDL cn kim tra.

Observer: khi quan st kt qu.Data source: ngun d liu (khi to ra cc tn hiu kch thch).

2.1.3. Gii thiu khi qut v ngn ng Verilog

Verilog HDL l mt trong hai ngn ng m phng phn cng thng dng nhtcng vi VHDL c dng trong thit k IC. Verilog HDL cho php m phng ccthit k d dng, sa cha li, hoc thc nghim bng nhng cu trc khc nhau. Ccthit k c m t trong Verilog HDL l nhng k thut c lp, d thit k, d thog v thng d c hn dng biu , c bit l cc mch in ln.

Verilog thng c dng m t thit k bn dng


Data Source(stimuli

Generator)ObserverDUT

Generics

Testbench Entity

12


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Thut ton (mt s lnh ging ngn ng C nh: if, case, for,while).

Chuyn i thanh ghi (kt ni bng cc biu thc Boolean).

Cc cng kt ni (cng: OR, AND, NOT).

Chuyn mch (BJT, MOSFET).Ngn ng ny cng ch r cch thc kt ni, iu khin vo/ra trong m phng.

Khai bo module

Mt module l bn thit k ch yu tn ti trong Verilog. Dng u tin ca khaibo module ch r danh sch tn v port (cc i s). Nhng dng k tip ch r dngI/O (input, output, hoc inout) v chiu rng ca mi port. Mc nh chiu rng port l1 bit.

Sau , nhng bin port phi c khai bo wire, wand, , reg. Mc nh l

wire. Nhng ng vo c trng l wire khi d liu c cht bean ngoi module. Ccng ra l dng reg nu nhng tn hiu ca chng c cha trong khi always hocinitial.

Ch th lin tip

Cc ch nh lin tip c dng gn mt gi tr ln trn mt wire trong mtmodule. l cc ch nh thng thng bn ngoi khi always hoc khi initial. Ccch nh lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s chnh mt gi tr n mt wire trong lc khai bo. Ch rng, cc lnh ch nh lintip th tn ti v c chy lin tc trong sut qu trnh m phng. Th t cc lnhgn khng quan trng. Mi thay i bn phi ca bt c ng vo s lp tc thay i

bn tri ca cc ng ra.

Module instantiations

Nhng khai bo module l nhng khun mu m n c to nn t cc itng thc t (instantiation). Cc module n c bn trong cc module khc, v midn chng to mt i tng c nht t khun mu. Ngoi tr l module mc trnl nhng dn chng t chnh chng. Cc port ca module v d phi tha nhng nhngha trong khun mu. y l mt l thuyt: bng tn, s dng du chm (.) .tn

port khun mu (tn ca wire kt ni n port). Bng v tr, t nhng port nhng vtr ging nhau trong danh sch port ca c khun mu ln instance.

BEHAVIORAL

Verilog c 4 mc khun mu:

Chuyn mch.

Cng.

Mc trn d liu.

Hnh vi hoc th tc c cp bn di.

Cc lnh th tc Verilog c dng to mt mu thit k mc cao hn. Chng ch ra

nhng cch thc mnh ca vc lm ra nhng thit k phc tp. Tuy nhin, nhng thay



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i nh n phng php m ha c th gy ra bin i ln trong phn cng. Cc lnhth tc ch c th c dng trong nhng th tc.

Nhng ch nh theo th tc:

L nhng ch nh dng trong phm vi th tc Verilog (khi always v initial). Ch

bin reg v integers (hoc chn n bit/ nhm bit ca chng hoc kt ni thng tin) cth c t bn tri du = trong th tc. Bn phi ca ch nh l mt biu thc mc th dng bt c dng ton t no.

Delay trong ch nh:

Trong ch nh tr t l khong thi gian tri qua trc khi mt lnh c thc thi vbn tri lnh gn c to ra. Vi nhiu ch nh tr (intra-assignment delay), bn phic nh gi tr trc tip nhng c mt delay ca t trc khi kt qu c t bntri lnh gn. Nu thm mt qu trnh thay i na cnh bn phi tn hiu trongkhong thi gian t, th khng cho kt qu ng ra. Delay khng c h tr bi cc

cng c.Cu trc chng trnh dng ngn ng Verilog

// Khai bo module

Module tn chng trnh (tn bin I/O); // tn chng trnh trng tn file.v.

Input [msb:lsb] bin;

Output [msb:lsb] bin;

Reg [msb:lsb] bin reg;

Wire [msb: lsb] bin wire;

// Khai bo khi always, hoc khi initial.

cc lnh

2.2. Mi trng lp trnh cho FPGA

Hin nay, c nhiu nh cung cp sn phm FPGA trn th trng nh Altera,Xilinx, Actel Sn phm ca mi nh cung cp li c nhng u, nhc im ring docc hng u sn xut theo cng ngh ring ca mnh. Chnh v vy mi hng li a

ra mt sn phm phn mm ring i km lm mi trng thit k v np cho chipFPGA ca hng nh ca Altera l Quartus II, Actel c Actel Libero cn Xilinx cISE. Trong kha lun ny em ch xin gii thiu v ISE phn mm h tr cho KitVirtex 4 ca Xilinx m em s dng thc hin kha lun ny.

2.2.1. ISE

H thng phn mm ISE ca Xilinx l mt mi trng thit k tch hp bao gmthit k chng trnh, m phng v thc hin cc thit k trn cc thit b FPGA hayCPLD. ISE c th tham gia vo vic iu khin mi giai on trong quy trnh thit

k.Thng qua giao din ca ISE, ngi dng c th can thip vo cc thit k v s



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Hnh 7: Cc la chn to project vi Virtex 4.

2.2.2.2. To m ngun VHDL

to ra file m ngun VHDL cho Project ta lm nh sau:

Chn New Source trong New Project Wizard.

Chn kiu m ngun VHDL Module.

G t bn phm tn ca file m ngun l counter (v d l to ra m ngun chocounter).

Quan st thy rng h kim tra Add to project c la chn.

Kch Next.

Khai bo cc cng cho b counter bng cch in cc thng tin nh hnh diy:

Hnh 8: Khai bo cc cng cho mt v d to mt counter 4 bit.

Kich Next cho ti khi kt thc v mt file VHDL c to ra vi cc khai boban u l cc cng in, out



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T y ta c th vit m ngun VHDL cho b counter nhng ta cng c th lycounter trong v d c sn ca ISE. s dng v d ny ta lm nh sau:

M v d bng cch: Edit > Language Template

Dng biu tng + duyt n m ngun ca v d nh sau: VHDL >

Synthesis Constructs >Coding Examples>Counters>Binary>Up/Down Couter>SimpleCounter.

dng la chn Simple Counter ta chn Edit > Use in File hoc chn nt UseTemplate in File trn Toolbar.

ng ca s Language Template.

Nh vy m VHDL trong v d c chn vo file m ngun m ta mun to.

chng trnh ny c th chy ng c ta phi quan st v sa li mt sch cho ph hp vi khai bo ban u. l nhng v tr m chng trnh nh du

trong du cui cng ta c file m ngun c ni dung nh sau:entity counter is

Port ( Clock : in STD_LOGIC;

Direction : in STD_LOGIC;

c : out STD_LOGIC_VECTOR (3 downto 0));

end counter;

architecture Behavioral of counter is

beginprocess (Clock)

begin

if Clock='1' and Clock'event then

if Direction ='1' then

c


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Chn file Counter t ca s Source.

To mt test bench t Project > New Source.

Trong ca s New Source Wizard chn Test Bench WaveForm v g t bn phmcounter_tbw trong trng tn file ri kick Next cho n khi xut hin ca s:

Hnh 9: Thit lp cc tham s m phng.

t cc thng s nh hnh 9 v kch Finish:

chy m phng ta thit lp cc thng s nh khong thi gian m tin, thi gianm li bng cch kch chut vo v tr m ta mun cho kt thc m tin khi dngxung bt u t s v tr logic 0 v bt u m li. Ta c th ty chn cc khongm tin hoc li theo mun.

Hnh 10: Thit lp thi gian m tin, li cho counter.

Sau ng ca s ny li v chuyn sang bc m phng.

M phng

Ti ca s Source ta chn Behavioral Simulation v chn counter_tbw.



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Ti ca s Process ta kch chut vo du + ri kch p vo Generate ExpectedSimulation Results thc hin m phng. Ta c kt qu nh sau:

Hnh 11: Kt qu m phng ca counter.

2.2.2.4. To rng buc thi gian

Bc ny s to ra rng buc v thi gian, l thi gian m ta rng buc khi chytrong FPGA.

Chn Synthesis/Implementatorn.

Chn file ngun counter HDL.Kch vo du + User Constraints v chn Create Timing Constraints.

Sau bc ny s to ra cho bn file.UCF v ta c th thit lp cc thng s theotnh ton m thit k s phi p ng.

2.2.2.5. Gn chn

Chn file ngun l counter trn ca s Source.

Chn Assign Package Pins trong ca s Process.

T y ta c th gn chn c th a thit k vo phn cng tht. Ty tngdng c th m ta t chn cn c vo bng chn c cung cp bi nh sn xut.

Kt thc bc ny ta c th a thit k vo phn cng v quan st trn cc li vo raca phn cng bng nhng thit b h tr quan st nh giao ng k hay n LED.



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CHNG 3: CC C IM C BN CA VIRTEX 4 V CC PHNMM H TR

3.1. Nhng c im c bn ca XtremeDSP Development Kit Pro (Virtex IV)

3.1.1. Gii thiu chung

L cng ty u tin nghin cu ra FPGA, Xilinx lun l mt hng i u trongvic nghin cu v cho ra nhng dng sn phm h tr cho gio dc cng nh cc bKit chuyn dng s dng trong nhiu ng dng c th. The XtremeDSP DevelopmentKit l b Kit c kh nng cung cp mt nn tng pht trin cao cho Cng Ngh FPGA.y l mt cng c rt mnh c s dng trong nhiu ng dng c bit l cc ngdng v DSP. Virtex 4 c hai b ADC v hai b DAC vi phn gii l 14 bit vitc xung nhp cao cho php ngi dng c th lp trnh v x l cho nhiu ngdng khng ch ring trong DSP nh cc ng dng Software Defined Radio, 3G

Wireless, Networking, HDTV hoc hnh nh Video. B KIT c cha mt bo mch chni vi mt module nm trn mt board mu xanh. Bo mch ch c gi lBenONE-Kit Motherboard v module trn c gi l BenADDA DIME-II module.BenONE-Kit l mt dng gn ln cc module h tr cho cc tnh nng khc.

Di y l mt s h tr ca BenONE-Kit:

H tr cho module BenADDA DIME-II.

H tr giao din USB hoc 3.3V/5V PCI.

H tr giao din PCI 3.3V/5V 32 bit/33-MHz v giao din USB 1.1.

Cc LED hin th. Mch to cu hnh JTAG.

Cc chn cm ni trc tip vi ngi dng c th lp trnh c (FPGA I/O).

Module BenADDA DIME-II.

Chp FPGA: XC4VSX35-10FF668.

Hai knh DAC c lp: AD6645 ADC (14-bits 105 MSPS).

Hai knh ADC c lp: AD9772 DAC (14-bits 160MSPS).

H tr clock ngoi, b dao ng onboard v clock c th lp trnh. Hai b nh SRAM (133MHz, 512Kx32 bits mi bn).

Cc LED hin th.

Di y l mt s hnh nh m t v Kit Virtex 4.



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Hnh 12: Giao din ngoi ca XtremeDSP Development Kit Pro.

Hnh 13: Giao din pha trong v cc thnh phn ca Virtex IV Pro.

3.1.2. Cc thnh phn chnh ca Virtex 4

Chp FPGA (XC4VSX35-10FF668)

Cc c im chnh ca XC4VSX35-10FF668:

- Rocket IO Transceiver Blocks: 8

- PowerPC Processor Blocks: 2

- LogicCells: 30,816

- Slices: 13,696

- Max DistrRAM (Kb): 428

- 18 X 18 Bit Multiplier Blocks: 136

- 18 Kb Blocks: 136

- Max Block RAM (Kb): 2,448

- DCMs: 8

- Maximum User I/ O Pads: 644



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Cc b ADC

Module BenADDA DIME-II s dng trong XtremeDSP Development Kit Proc hai knh vo tng t, mi knh c d liu v tn hiu iu khin c lp tiFPGA.Hai ADC (AD6645) cho php thc hin hai thit lp d liu vi rng 14 bit.

Tn hiu a vo ADC v tn hiu ra thng qua chun kt ni MCX. S khi thhin kt ni gia cc b ADC c th hin nh hnh 14. Vi kit Virtex 4 hay mt sdng kit ca Xilinx c h tr XC2V80-4CS114 c nhim v iu khin xung Clockcho ADC. Nh vy, ta c th la chn c tc ly mu ph hp vi yu cu thitk vi tng bi ton c th.

Hnh 14: S tn hiu qua ADC vo FPGA.

Cc c im chnh ca khi ADC (AD6645) Cung cp ADC 14-bit, kiu m b 2.

Tc ly mu 105MSPS.

Tr khng vo 50 cho tn hiu t l hay li vo thay i vi phn.

B lc bc 3 li vo.

Clock ADC c th thay i c.

Hnh 15: S khi ca b ADC (AD6645).



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Cc c im chnh ca DAC (AD9772A)

Cung cp DAC 14-bit.

Tc d liu li ra ti a 160MSPS.

S dng clock LVPECL li vo ly t XC2V80-4CS144 Clock FPGA. B nhn ng h c vng kha pha trong.

Tr khng li ra 50 thng qua chun kt ni MCX.

Hnh 18: S khi tip b DAC.

DAC clock

Mi DAC c th c clock trc tip, c lp thng qua tn hiu LVPECL. Tn

hiu LVPECL c th c iu khin bi Virtex-II XC2V80-4CS144 FPGA (ClockFPGA). Mt s cc clock c th s dng thng qua clock FPGA:

- Clock 105 MHZ on board bng tinh th.

- Clock ngoi a vo thng qua chun kt ni MCX.

- Clock lp trnh qua b dao ng trn KIT.

B nh ZBT SRAM

B KIT cung cp 2 b nh c lp ZBT SRAM. Mi b c th cu hnh 512k x32. B nh ny c kh nng lu d liu trn board thng qua bus d liu 32-bit ti mi

b nh.c im chnh ca ZBT SRAM

Thi gian chu k nhanh: 6ns, 7.5ns v 10ns.

100% bus c tn dng.

iu khin qua giao din tn hiu ti thiu.

C cc chn iu khin c/vit ring.

S dng tn hiu iu khin, a ch thanh ghi, d liu vo ra, c th thit lp

c clock.



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Cho php d liu vo ra thng thng.

C mode tuyn tnh hoc ghp xen.

Hnh 19: S ZBT SRAM.ZBT SRAM Clocking

Hai b nh ZBT SRAM trn b KIT c th c g nhp c lp thng qua vicchn thm tn hiu xung nhp phn hi. Mi b nh c mt tn hiu c th c hiuchnh trong FPGA m bo cho xung nhp gia ZBT SRAM v chn phn hi c xungnhp cng nhau vi sai khc nh nht. Qu trnh ny m bo cho logic trong ckha pha vi d liu a vo.

Bng1: K hiu chn ca ZBT SRAM clocking.Vo ra s

Mt s c im vo ra ca b KIT:

Mt u bus 14 chn trn bo mch ch. N cho php 12 kt ni trc tip haichiu ti FPGA vi hai chn ni t.

Mt u bus 34 chn hiu chnh trn bo mch ch. N cho php 28 kt ni trctip hai chiu ti chip FPGA. Cc phn cn li cho cc kt ni 3,3V, ni t v 'khngc ni'.

Hai u vo ra 2 chn cung cp 2 kt ni hai chiu ti chip FPGA.



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Clock

B KIT XtremeDSP Development Kit c mt h thng qun l clock ton dinv linh hot. Sau y l mt s c im ca h thng clock:

- B KIT c mt ngun pht tinh th 105 MHz trn module chnh cung cp clock

cho cc thit b tng t.- Mt li vo cho clock ngoi trn bo mch ch c th thit lp c tn s

- Mt khe cm cho b dao ng trn bo mch ch. Ch rng trn bo mch chkhng c b dao ng m ch c socket ngi dng s dng cc b dao ng chocc ng dng ring bit.

DIME-II System Clocks

Module BenADDA DIME-II c th to ra ba h thng clock cho FPGA, ccclock c gi l CLKA, CLKB v CLKC. Cc tn hiu clock c to ra trn bo

mch ch DIME-II v c a vo vng module ni t module BenADDA DIME-II.Cc clock ny c th c iu khin bi ngi dng v c a n cc chnGlobal Clock cung cp mt cch linh hot nht cho FPGA. Tuy nhin cn ch rngchc nng ca cc DIME-II clock ny c xc nh bi bo mch ch. Khi moduleBenADDA DIME-II c t vo bo mch ch BenONE-Kit, khi trong cu hnhKIT XtremeDSP Development Kit, cc clock ca DIME-II l :

- CLKA: clock do b to dao ng c th lp trnh trn bo mch ch BenONE-Kit

- CLKB: clock do b to dao ng c th lp trnh trn bo mch ch BenONE-

Kit- CLKC: kt ni ti mt socket h tr b to dao ng tinh th.

Hnh 20: S h thng clock.



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LED hin th

XtremeDSP Development Kit c mt s user-definable v cc LED hin th chophp ngi dng kim tra trng thi hot ng ca b KIT. C cc LED kim tra cuhnh ngi dng v cc LED hin th trng thi h thng, cu hnh cc giao din v

ngun (Interface LEDs). Cc LED s dng b KIT c ba mu. Mi LED hin th tngcng ba mu khc nhau: , Xanh v Vng/Dacam. Vi s tr gip ca cc LED hinth ny ngi thit k c th kim tra mt cch trc quan phn ng ca phn cng ivi cc yu cu thit k. Tuy ch l mt ng dng nh nhng i khi n c ngha rtquan trng c bit cho nhng ngi bt u tip cn vi FPGA hay lm chc nng

bo hiu k c trong cc project ln.

Hnh 21: S cc LED trng thi nhn t ngoi.

Hnh 22: Cc LED bn trong Kit Virtex 4.

Trn y ch l nhng nt gii thiu rt s lc v mt s c tnh ca Kit Virtex4. c th s dng Virtex 4 nh mt cng c h tr c lc cho vic nghin cu, xydng cc m hnh th nghim th cn cn phi i su vo tm hiu, nghin cu tng

c tnh nh nh s chn giao tip vi cc tn hiu bn ngoi v cc chn tn hiu



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giao tip gia cc modul trong Kit... Ngoi ra vic s dng clock trong Virtex-IV cngrt phc tp i hi ngi nghin cu phi c mt thi gian tm hiu v lm thc tp.

3.2. Cc phn mm chuyn dng h tr kit Virtex 4

3.2.1. FUSE

Phn mm FUSE ca hng Nallatech cho php ngi dng c th cu hnh, iukhin v thc hin giao tip gia h thng ch v cc phn cng my tnh FPGA ca

Nallatech. Phn mm ny c pht trin c th thit k cc h thng x l phctp nh 1 khi thng nht gia phn mm, phn cng v cc ng dng FPGA.

FUSE cung cp mt s giao din, bao gm ngn ng lp trnh DIMEscrip. FUSEProbe Tool; FUSE cn c pht trin cho cc ngn ng bc cao nh C/C++, Javahoc Matlab. FUSE c th ci t c trong cc h iu hnh Windows hoc Linux.Cc c im c bn nht ca FUSE c th k ra nh sau:

* Cu hnh thit b nhanh chng v n gin.

* H tr nhiu Card.

* H tr nhiu giao din.

* H tr cc giao din v iu khin cho cc thit b phn cng caNallatech.

Hnh 23: M t giao tip gia FUSE vi Computer v FPGA.

3.2.2. Matlab v cc gi cng c Xilinx h tr cho Matlab

System Generator

System generator l mt cng c thit k h thng gip cho vic thit k cc ngdng phn cng trong FPGA v m phng Simulink. l mt mi trng thit k rtmnh trong vic thit k phn cng. Systerm Generator c kh nng m hnh ha caov c th dch cc thit k ca ngi dng sang ngn ng phn cng trong FPGA mt

cch t ng ch vi mt thao tc n gin nh n mt nt. Thm vo System



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Generator cn cho php xm nhp vo cc ti nguyn trong FPGA mc thp hn,qua cho php ngi s dng thc hin cc thit k c hiu sut cao.

Vic lp trnh mt b FPGA bng System Generator bao gm cc bc sau: Mphng thit k, to ra mt bn thit k theo ngn ng bc thp c th a cc thit b

phn cng nh FPGA t thit k m phng ny, sau a bn thit k mi to ra nyvo trong file cu hnh ca FPGA gi l bitsream. Bc cui cng, a thit k phncng vo trong bitstream c th thc hin bng cc phn mm khc.

Mt trong nhng mt vt tri ca System Generator so vi cc phn mm khcl chc nng chy m phng phn cng Co-Simulation, chc nng ny s c ni rthm trong phn sau.

Cc khi Block Set DSP Xilinx

System Generator xy dng khong hn 90 khi x l tn hiu s (DSP) htr ngi dng trong vic m phng cc thit k. Cc khi ny gm cc khi DSP ph

bin nh khi cng, nhn, thanh ghi...Ngoi ra, n cn bao gm cc khi DSP phctp hn nh khi sa li tin, FFT, cc b lc v b nh. Cc khi ny lm cho victhit k m phng tr nn n gin v thun tin hn nhiu.

Hnh 24: Mt s khi c bn h tr Matlab cung cp bi Xilinx.

Cc thut ton trong Matlab c th kt hp cht ch vo trong System Generatorthng qua AccelDSP. AccelDSP bao gm cc thut ton mnh c th chuyn cc thitk dng du chm ng (floating-point) trong Matlab sang dng du chm c nh(fix-point) l loi hay c dng trong System Generator. Ngoi ra System generatorcn bao gm khi Mcode cho php ngi dng s dng cc thut ton khng c trongMatlab thit k v thc hin cc hot ng iu khin n gin.

nh gi, c lng ti nguyn h thng

System Generator cung cp khi c lng ti nguyn cho php nh gi mtcch nhanh chng cc ti nguyn dng cho thit k trc khi thc hin n trong thct. iu ny c li ch rt ln i vi c vic thit k phn mm ln phn cng gip



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cho cc nh thit k c th tn dng ti a cc ti nguyn trong FPGA (ln n 550 bnhn trong thit b Virtex 5).

Hnh 25: Ca s c lng ti nguyn.

M phng phn cng Co-Simulation

Cc khi blocksets c h tr trong System Generator cho php ngi dng xydng cc thit k m phng vi chnh xc cao. Tuy nhin cc k s thit k vnmun xem xt mt cch chi tit vic thit k ca mnh chy trong phn cng nh th

no. System Generator cung cp giao din m phng Cosimulation gip kt hp chtch v trc tip vic chy thc t trn FPGA vo m phng simulink. thc hin m

phng Cosimulation, trc ht ta a thit k vo bitstream, sau System Generatort ng hp nht cu hnh phn cng FPGA vi bitstream tr li thit k m phnggi l khi run-time. Khi thit k c m phng trong mi trng Simulink, kt quca thit k cng c tnh ton trong phn cng. iu ny cho php chy th ccthit k trong phn cng tht s v lm tng tnh thc t cho cc m phng.

Kh nng kt hp cc mi trng thit k

System Generator cung cp 1 mi trng thng nht cho cc thit k DSP

FPGAs, cho php cc thnh phn nh c vit bi cc ngn ng khc nhau nh RTL,Simulink, Matlab v C/C++ c th lm vic cng nhau trong cng mt thit k.System Generator h tr khi black box cho php a RTL vo thc hin m phng

phn mm v phn cng bng c ModelSim hoc Xilinx ISE Simulator.

Nh vy, vi cng c l Kit Virtex 4 ta khng ch c mt phn cng hin i,chuyn dng vi lng ti nguyn FPGA ln m cn km theo l nhiu cng c htr rt mnh nh System Generator, Co-Simulation cho php ta d dng trin khaicc nghin cu, thit k.



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Hnh 26: S m t kh nng kt hp gia cc mi trng thit k.



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CHNG 4: THC HIN M HNH THIT K VI KIT VIRTEX-4

(Thit k b pht m Walsh cho h o knh MIMO)

4.1. Gii thiuVic thit k FPGA thc hin cc chc nng theo mt yu cu no bngngn ng VHDL tit kim ti nguyn FPGA tr ln rt ph bin v mang linhng li ch r rt. Tuy nhin trong thc t c nhng m hnh ln nh trong cc mhnh thu pht tn hiu MIMO (Multiple Input, Multiple Output) i hi ngi thchin phi thc hin mt khi lng cng vic rt ln vi vic vit cu lnh VHDL mi khi mc ch ch l kim tra tnh kh thi ca m hnh nu ra. Hn na, vi cngngh FPGA pht trin nh ngy nay th ti nguyn trong chip FPGA i vi cc mhnh nh th khng cn l vn qu quan trng. Xilinx l hng i tin phong tronglnh vc pht trin cc cng c b tr cho cc kit chuyn dng vi cng c System

Generator nh gii thiu chng 3 nhm gim nh cng vic cho ngi thit kh thng, ng thi gip ngi thit k bin nhng m hnh m phng tr thnh mngun c th nhng trc tip vo trong phn cng (FPGA) Tt nhin iu ny c thkhin m ngun ca thit k di hn v tn ti nguyn phn cng hn nhng n limang li gi tr rt ln l rt ngn thi gian trong qui trnh thit k. Chng ny s giithiu v cch s dng cng c h tr system generator thc hin mt m hnh thitk thng qua vic thc hin mt m hnh pht tn hiu qua m ha Walsh.

4.2. Hai khi chc nng chnh trong s

4.2.1. Khi to m Walsh

Hnh 27: Khi to d liu Walsh.

4.2.1.1. L thuyt v m WalshM Walsh c chiu di n =2 k l mt tp cc t m trc giao hon ton c th

c nh ngha bi ma trn hng 2k x 2k. Vi ma trn ban u 1 x 1 l H 1 = [0],cc ma trn Hadamard th t cao hn c th ly t ma trn trc n theo cng thctng qut sau:

H k2 =

11

11

22

22

kk

kk

HH

HH

V d:



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H1 =[0]

H 2 =

10

00

H 4 =

0110

1100

1010

0000

Do vy cc t m Walsh biu din m lng cc ( 1 ) l

[ ]1

2

4

1

1 1

1 1

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

H

H

H

= +

+ +

= + + + + +

+ + = + + + +

* c im

+ u im

Tt c cc t m u trc giao ln nhau hay cc cp t m bt k u bng 0.

+ Nhc im

- Cc m khng n, nh t tng quan hp.

- Tri khng bao trm ht di thng tuy nhin bao trm ht thnh phn tn sri rc.

- Tng quan cho khng lun lun bng 0 cho cc ng dng khng ng b.

- V cu trc c bit c sn trong m Walsh n c bit nh tng quan catp hp vi 2k t m Walsh tnh ton kt qu vi phc tp O(n.logn) s dng

bin i Hadamard nhanh (FHT). FHT c cu trc cnh bm (butterfly) tngt bin i Fourier nhanh (FFT). Nhng FHTc cc h s l 1 tt hn hm lutha phc.

Gii m (m ph c bn gii m Walsh)

M Walsh c gii m tt nht bng b gii m Walsh vi vic tnh ton cnh, phc tp. Trong phn ny em xin gii thiu phng php hiu qu tng ngtnh ton phc v BER da trn cu trc ton hc ca m Walsh.



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Mt ma trn tng qut cho m nh phn tuyn tnh C l ma trn G c cc hngl c s ca C. Do vy cc t m trong cu trc nh phn c th c tnh ton tngqut nh sau:

C = xG vi mi ma trn hng nh phn x c dng 1 x k.

Ma tn tng qut m Walsh (6,64) c s dng trong IS-95 l 6 x 64, gmc 6 hng v 64 ct.

G=

1101010

1001100

1. . .110000

1000000

1000000

1000000

T ma trn tng qut ny ta c th gii m ho Walsh m khng kim tra tonb cc t m.

Gii m cc b (Local Decoding)

Cu trc c bit ca m Walsh cho php nh gi 6 bit li vo m ch cnquan st duy nht hai trong 64 Symbol ca t m Walsh c nhn, thng qua bx l gi l Local Decoding, tnh ton phc v truyn t m tt.

hiu cng ngh ny ta t nhn Symbol ca cc t m l c= [c0, c1, c2, .,c63 ]. Cc gi tr l gi tr thp phn ca p ng nh phn vect ct trong ma trnG. Mc ch chng ta gii m cc v tr 0 ca vect x = [x 0, x1, x2, x3, x4, x5 ] ninhn khi khng c nhiu. Ta c th thu c gi tr ca x0 bng cch cng module2 vi bt k thnh phn t m c i v cj m i, j l cc p ng ct trong G khc duynht v tr cc bt 0.

( )5 5 5

0 0 0

i j s si t tj s si sj

s t s

c c x G x G x G G= = =

= =

( ) ( )5

0 0 0 0

1

=x i i s si sis

G G x G G x=

=



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4.2.1.2. Thc hin trong thit k

Ma trn Hadamard dng trong s l:

0110100110010110

1100001100111100

1010010101011010

0000111111110000

1001100101100110

0011001111001100

0101010110101010

1111111100000000

1001011010010110

0011110000111100

0101101001011010

1111000011110000

0110011001100110

1100110011001100

1010101010101010

0000000000000000

B to m Walsh trong s l b to m Walsh (4,16) v (3,16) (y ch l mtla chn ngu nhin v c th thay i d dng trong thit k) tc l dng hng th 4

v th trong ma trn Hadamard 16. Khi biu din di dng lng cc th ta c:[-1 1 1 -1 -1 1 1 -1 -1 1 1 -1 -1 1 1 -1]

v [-1 -1 1 1 -1 -1 1 1 -1 -1 1 1-1 -1 1 1]

Cc gi tr c np vo khi ROM th hin mt chui Walsh s l chui lin tip ccbit 0 v 1. Vi yu cu thit k cho knh MIMO vi hai ng tn hiu qua b mWalsh th ta chn hai chui Walsh (4,16) v (3,16) nh sau:

H(4,16): [0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0]

H(3,16): [0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1]

4.2.1.3. S v kt qu m phng b to 2 dy Walsh (4,16) v (3,16)



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Hnh 28: S m phng b to Walsh.

Kt qu m phng:

Hnh 29: Kt qu m phng b to Walsh (4,16) v (3,16).

4.2.2. Khi m ha cosin tng (Raised-Cosine)

4.2.2.1. L thuyt

Trong cc h thng truyn dn, tn hiu di nn c bn (baseband) c iu chln sng mang truyn i. Vic lc tn hiu xy ra mt s giai on trong qu trnhtruyn dn. Bn thn tn hiu baseband b hn ch bng thng bi vic lc ngnvic to ra cc tn hiu di bn (sideband) vt qu trong qu trnh iu ch. Tn hiu iu ch c lc bng thng tip theo trong qu trnh khuch i ca my pht. ni m cc tuyn truyn (hu tuyn, v tuyn) to thnh knh truyn th p tuyn tns ca knh truyn cng phi c tnh ti. pha thu, vic lc bng thng tn hiu til cn thit loi b nhiu (noise) c a vo giai on ny. Nh vy tn hiu i

qua mt s giai on lc v nh hng ca chng ti dng sng s phi c tnh ti.



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Trn ton b tuyn truyn dn t my pht ti my thu ph ca xung u ra my thuV(f) c xc nh bi ph ca xung u vo Vi(f), p tuyn b lc ca my phtHT(f), p tuyn tn s ca knh HCH(f), v p tuyn b lc my thu HR(f). Hnh 30minh ha iu ny, v ta c phng trnh:

V(f) = Vi(f) HT (f) HCH(f) HR(f) (4.1)

Hnh 30: Cc thnh phn ph tn s ca phng trnh 8.

Cc thnh phn in cm v in dung l cc thnh phn vn c ca qu trnhlc. Chng khng tiu hao nng lng tn hiu, nhng nng lng c tun hontheo chu k gia in trng, t trng v tn hiu. Thi gian cn thit cho qu trnhtrao i nng lng ny lm cho mt phn ca tn hiu b tr, do vy cc xung hnhvung i vo pha my pht c th c dng "hnh chung" v dao ng khi n i ra

pha my thu. Hnh 31a minh ha iu nu. V thng tin c m ha s di dngsng nn mo xut hin trong dng xung l khng quan trng cho ti khi my thu cn

phn bit c cc xung nh phn 1 vi cc xung nh phn 0. Vic ny i hi dngsng phi c ly mu cc khong cch ng xc nh ng cc tnh ca n.Vi dng sng lin tc, cc ui to thnh t hnh chung t tt c cc xung trc c th kt hp can nhiu vi xung ring cn ly mu. Hin tng gi l cannhiu gia cc symbol (Intersymbol Interference ISI) v n c th gy li trong xcnh cc tnh ca tn hiu. Khng th loi b cc hnh chung nhng c th to dngcc xung sao cho vic ly mu xung cho xy ra khi cc ui cc im ct cho

bng khng nh minh ha hnh 31b. cng l ni dung ca cc nh lut Nyquistv loi b nh hng ca can nhiu gia cc symbol. Trong thc t khng th to dngxung hon thin, do vy s c ISI, nhng n c th c gim n mc nh c th bqua.Vic to dng xung c thc hin bng cch kim sot ph ca xung thu c quaiu chnh cc thnh phn c lin quan nh trnh by trong cng thc (4.1). Mt mhnh l thuyt ca ph thch ng vi vic l p tuyn (hoc b lc) cosin tng:B lc cosin tng l mt b lc in t c th, thng c s dng to dng xung

trong iu ch s do kh nng ti thiu ha ISI ca n. Tn ca b lc bt ngun tmt thc t l phn khc khng ca ph tn s trong dng n gin nht ca n (=1)l hm cosin, tng ln pha trn ca trc ngang f.


HT(f)

HCH

(f) HR(f)


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1/2T


A

A

f

f

(a

(b

Hnh 31: a, Dng hnh chung ca xung

b, Ly mu trnh ISIM t ton hc:

B lc cosin tng l mt thc hin ca b lc Nyquist thng thp, c tnh cht ixng theo trc ng. Ph ca n biu hin i xng l xung quanh gi tr (1/2T), vi Tl chu k symbol ca h thng thng tin. Trong min tn s b lc c m t bicng thc (4.2), l hm hnh chung (hnh 32). N c c trng bi hai gi tr: h sroll-off , v chu k lp ca symbol T (T=1/Rs vi Rs l tn s symbol).

Hnh 32: p tuyn bin (tn s) ca b lc cosin tng vi cc h s roll-off khcnhau


=0

=0.35

=0.25

=1

H(f)

1/T f

t

t


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10

21

21,

___,0

)2

1(c o s12

1

2

1,0.1

)(


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Cc th ch ra s thay i ca p tuyn bin khi thay i gia 0 v 1, vs thay i tng ng vi p tuyn xung. Ta thy mc gn sng min thi gian tngkhi gim. T cc th ta cng thy c th gim bng thng vt qu ca b lc khigim (hnh 32) nhng gi t ca vic ko di p tuyn xung, c ngha l ko dikhong thi gian gy can nhiu gia cc symbol k nhau (hnh 33).

= 0

Khi tin ti khng min roll-off tr nn v cng hp, v vy khi 0 lim H(f)= rect (fT), vi rect(.) l hm ch nht, p ng xung c dng sinc(t/T). iu ny cngha l n hi t ti b lc l tng c cc vch dng ng.

= 1

Khi =1 phn khc khng ca ph l cosin tng thun ty, dn n cng thcn gin (4.5).

[ ]

+

==l ac o nh o pt r u o n g

Tff T

fH

___,0

1,)c o s (121

|)( 1

(4.5)

Bng thng

Bng thng ca b lc cosin tng c nh ngha nh phn khc khng ca phca n, c ngha l:

BW = (1/2) Rs (1 + ) (4.6)ng dng

Hnh 34 biu din dy cc xung cosin tng lin tip vi ISI = 0. Khi c sdng lc symbol stream, b lc Nyquist c tnh cht loi b ISI v p tuyn xungca n bng khng tt c cc gi tr nT (vi n l s nguyn), tr gi tr n=0. Do vynu dng sng pht c ly mu chnh xc my thu th cc gi tr symbol gc ckhi phc hon ton. Tuy nhin hu ht cc h thng thng tin thc t phi s dng blc phi hp loi b nh hng ca nhiu trng. C ngha l phi tun theo iukin:

)()()(),()(*

fHfHfHhayfHfH TRTR===

(4.7) tha mn iu kin (4.7) trong khi vn m bo ISI bng khng, b lc cn

bc hai cosin tng thng c s dng hai pha pht v thu ca h thng thng tin.Khi p tuyn ton b ca h thng s l cosin tng.



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tT 2T 3T-T-2T-3T

h(t)


Hnh 34: Cc xung cosin tng lin tip biu th ISI bng 0.

Tm li, b lc cosin tng l mt dng b lc in t c th, c thit k

khc phc can nhiu gia cc symbol (ISI), gip cho h thng s trnh nhm ln khixc nh symbol. Thng s quan trng nht ca b lc l h s roll-off , , v chu ksymbol, T. Khi thay i th bng thng vt qu ca b lc cng thay i V ngha vt l c th hiu nh sau: khi min rol-off cng hp ( 0) th bng thngvt qu gim, bng thng thc t ca ton tuyn truyn gim, nhiu thnh phn phca xung vung i qua tuyn s b ct dn n dng xung b mo tng ng vi daong nhiu chu k trong p tuyn xung, d gy can nhiu gia cc xung lin k. Khimin roll-off tng th qu trnh xy ra ngc li, p tuyn xung gn hn, kh nng ISIt hn nhng bng thng b chim l ln hn, hiu sut s dng bng thng v mttng th s km hn. Ty theo phng thc truyn dn (v tinh, cp, mt t) cng

nh s trng thnh ca cng ngh m s c cc gi tr khc nhau, khi hiu suts dng bng thng cng khc nhau.

4.2.2.2. Thc hin trong thit k

Trong thit k b lc Raised Cosine c to nn bi khi FIR Compilerv1_0. Khi ny c chc nng cu trc mt b lc FIR trong FPGA hoc c th cutrc mt b lc FIR t cc slices c vng ti nguyn DSP l cc khi DSP48. cth thit k c mt b lc theo mun ta phi cn thm khi FDATool trong

blockset ca Xilinx (khng phi khi FDATool trong blockset ca Simulink).

Hnh 35: Hai khi FIR Compiler v1_0 v FDATool ca Xilinx.

cu hnh cho b lc ta nhy p vo khi FDATool v la chn cc thams: B lc Raised-Cosine, tn s Fs, tn s ct Fc, v h s Roll-off trn ca s giao

din ca FDATool nh hnh 36:



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Hnh 36: Ca s giao din FDATool.Sau chn Design Filter c c cc h s ca b lc. cc h s ny

c y vo cu hnh trong khi FIR Compiler v1_0 c hai cchCch th nht: Xut cc h s ny ra Workspace vi cc h s l mt bin

mng vi mt tn no (VD l Num nh hnh 37).

Hnh 37: a h s b lc FIR t FDATool.

ng ca s FDATool li.

Tip , FIR Compiler v1_0 nhn c cc h s ny ta nhy p vo b lc FIRCompiler v1_0 s xut hp thoi sau:



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Hnh 38: Cc la chn trong properties ca FIR Compiler c c h s tWorkspace.

Ta la chn cc tham s ph hp nh c khoanh trn hnh ri ng ca s nyli.

Nh vy ta c c mt b lc Cosin tng vi cc h s c thit k tcng c FDATool.Cch th 2: Vi cch ny ta cng thit k b lc t FDATool nhng khng y cc hs ra Workspace m t lnh xlfda_numerator(Ten_cua_khoi_FDATool) trong

properties ca khi FIR Compiler v1_0 sau la chn Filter type l interpolation nh

hnh 39 di y:

Hnh 39: Cc la chn trong properties ca FIR Compiler c c h s trc tipt FDATool.

Sau ng ca s ny li v mt b lc Cosin tng c cu hnh t cc hs c thit k t FDATool. Ngoi ra, ta cng c th cu hnh b lc bng ngun tinguyn DSP48 c sn trong Kit dng cho cc ng dng DSP vi nhiu li ch. Tuynhin trong bi kha lun ny s khng cp n phng php ny.

4.2.3. Khi to d liu



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Trong thc t d liu ny phi c a t ngoi vo thng qua b ADC caKit Virtex 4. Tuy nhin do y cha phi l mt thit k vi mt mc ch thc hintrong mt ng dng c th nn d liu s c to ty bn trong Kit Virtex 4. Dliu ny l d liu s c chn ty c xy dng t cc khi Counter, ROM, vcc b Time Division. Trong , d liu ty c np vo ROM, khi Counter dng cp xung nhp cho ROM y d liu ra, cc b Time Division h tn s ca dliu phi hp vi chui Walsh pht ra t b to Walsh. Trong thit k ny dng Walsh16 nn tc d liu s chm hn tc Walsh 16 ln. Mi b Time Division s chiai tn s ca d liu nn trong thit k ny cn dng 4 b Time Division (B to dliu ny cng c th c to bng nhiu cch khc nhau).

Hnh 40: S khi b to d liu.

4.2.4. Cc khi khc

Trong s cn dng mt s khi khc nh b DAC, XOR. Ngoi ra quan trng

nht l khi System Generator dng qun l cp tn hiu cho ton b cc khi trongs .

Hnh 41: Khi XOR v System Generator.

Cch cu hnh cho khi System Generator s c ni chi tit hn phn thchin m hnh thit k s cp di y.

4.3. M hnh thit k v kt qu thu c



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4.3.1. M hnh m phng vi cc khi trong gi cung cp bi Xilinx v trongSystem Generator

Hnh 42: M hnh thit k b to ra 2 dy tn hiu.

Cu hnh trong System Generator c ch ra nh hnh 37 di y:

Hnh 43: Cc tham s cu hnh trong System Generator.

4.3.2. Kt qu m phng


Dng xut ra (HDL Netlist, Bitfile)

Tn Kit

ng dn lu cc file s xut ra

Ngn ng m t phn cng s xut ra

Chu k m phng.

Chn Clock dng trong thit k


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Hnh 44: Kt qu m phng 1 chui tn hiu c m ha vi 2 dy Walsh khc nhau.

Tn hiu pha trn l chui tn hiu 0101 c m ha vi dy Walsh (4,16)v c lc qua b lc Cosin tng.

Tn hiu pha bn di l chui tn hiu 0101 c m ha vi dy Walsh(3,16) v c a qua b lc Cosin tng.

4.3.3. Thc hin chng trnh trn Kit Virtex 4 v kt qu thu c

4.3.3.1. Thc hin trn Kit Virtex 4

thc hin c trn Kit Virtex 4 t s m phng c xy dng tacn lm cc bc sau:

- Cu hnh cho System Generator nh ch ra phn 4.3.1.

- To ra m ngun t s m phng.

- Dng phn mm ISE ca Xilinx bin dch chng trnh v gn chn cho cc tnhiu vo ra.

- To ra bitfile t ISE (file ny s c np vo FPGA).

- Dng phn mm h tr FUSE m card (m giao tip gia my tnh v FPGA).

- Cu hnh clock cho Kit thng qua thao tc np file nh ngha clock FPGA s thchin trong thit k.

- Np thit k vo trong FPGA.

4.3.3.2. Kt qu thu c



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Hnh 45: Quan st tn hiu m ha Walsh pht ra t Kit Virtex 4.

nh gi kt qu

Kt qu m phng v kt qu quan st c khi thc thc hin trn Kit thcph hp vi kt qu tnh ton l thuyt.

Vic thit k v thc hin thnh cng b pht ra hai dng m Walsh cho knhMIMO dng cng ngh FPGA hon ton c th p dng trong nhng m hnh khc.

S dng Kit Virtex 4 cng vi cc cng c h tr i km thit k FPGA lmt phng php thit k n gin, linh hot v hiu qu.

KT LUN



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K thut MIMO vi nhng u im ca n ang ngy cng c ng dngrng ri cng vi cc nhc im ca k thut ny cng dn dn c khc phctrong qu trnh nghin cu v thc hin. Vi vic s dng FPGA xy dng mt h

Testbed lm gim ng k cho qu trnh thc hin mch in t ng thi tnh khthi cng tng ln rt nhiu. Vi kh nng ti lp trnh ca FPGA ta c th d dng thayi v trin khai cc thut ton x l m khng cn ngh n vic thay i phn cng.

ti kha lun ny tuy mi ch thc hin c mt phn nh trong m hnhxy dng mt h Testbed MIMO nhng n s l tin cho vic nghin cu v honthnh tip nhng chc nng cn li trong h.

Vi vic thc hin thit k thnh cng b m ha Walsh trong knh truynMIMO vi hai ng tn hiu ta c th hon ton p dng c vi cc h MIMO cs lng knh truyn ln hn. Vi thnh cng ny th nhim v xy dng hon thin

mt b Testbed MIMO hon chnh s sm thc hin c.c bit qua qu trnh tm hiu v lm thc nghim em thu c nhiu kin

thc v cng ngh FPGA, cch s dng Kit chuyn dng Virtex 4 l nhng kin thcm khng phi bt k sinh vin no trong trng cng c tip cn.

Mt ln na em xin c cm n TS Trnh Anh V v anh CN.V Xun Thng tn tnh ch bo em v kin thc cng nh to mi iu kin thun li em honthnh ti kha lun ny.

TI LIU THAM KHO



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[1] Mani B. Srivastava. VHDL tutorial. UCLA EE.

[2] System Generator for DSP (Getting started Guide, Reference Guide, User Guide).Xilinx.

[3] Nguyn Trng Hi.Bi ging Verilog. H K thut cng ngh TPHCM.

[4] Nguyn Vit Knh, Trnh Anh V. Thng tin s. NXBGD.

[5] V Xun ThngKnh truyn MIMO v b thu pht cho h o th knh. Kha luntt nghip, trng H Cng ngh - HQGHN.

[6] Website:

www.xilinx.com

www.VNeEpress.com

www.wikipedia.org

MC LC

http://www.wikipedia.org/http://www.wikipedia.org/


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Khi logic ..............................................................................................................6Hnh 3: Khi logic trong FPGA ............................................................................6

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