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EECS 142
Lecture 26: Power Amplifiers
Prof. Ali M. Niknejad
University of California, Berkeley
Copyright c© 2005 by Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 1/25 – p. 1/25
Introduction to PAs
Heat
Pin PL
Pdc
Zin = 50Ω
Zout 6= 50Ω
Power Amplifiers (PA) deliver power to a given load withmaximum efficiency while faithfully transferring themodulation from the input to the output.
Like small-signal amplifiers, PAs are typically matchedat the input. However, the output of the PA is usuallyunmatched in order to maximize efficiency (whichresults in lower power gain).
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 2/25 – p. 2/25
Audio PA Example
Audio Amp
8Ω
1 kWHeat
DC Power
Consider a PA that delivers 1kW of power into 8Ωspeakers.
Assuming a sinusoidal input, the peak voltage andcurrent are
V =√
2RP =√
2 · 8 · 1000 = 126V
I =2P
V= 15.8A
Such large currents and voltages require specialtechniques and/or technology.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 3/25 – p. 3/25
Efficiency
The Power Added Efficiency, or PAE, is a measure ofhow much power is added to a signal normalized by theDC power consumption
PAE = η =PL − Pin
Pdc
If the power gain is large
PAE =PL(1 − G−1
p )
Pdc
≈ PL
Pdc
The drain or collector efficiency is defined as
ηc|d =PL
Pdc
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 4/25 – p. 4/25
Mobile Phone Example
AD
C
VCO
LNA
DA
C
PA
Consider a typical mobile phone that delivers 1W in to a50Ω antenna. Here we find that
V0 =√
2PR =√
2 · 50 = 10V
I0 = 2/10 = 0.2A
Most high-frequency Si transistors cannot handle 10Vdue to breakdown. Thus we need to transform thevoltage down to a safe value.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 5/25 – p. 5/25
High Voltage/Current
4 : 1
50Ω
10V
2.5V
Note that in the process of transforming the voltagedown, the current transforms up, I = 0.8A. This requirescareful layout to minimize “series” parasitic loss. For a1Ω parasitic loss, we throw away nearly 1/3 of the powerto the load
PL,s = 1
2I2R = 320mW
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 6/25 – p. 6/25
Effect of Loss
If the core amplifier efficiency is say 50%, then thisexternal loss cuts the efficiency to
Ploss = 320mW +PL
η= 2.32W
η =1
2.32= 43%
If the transformer has 2 dB of insertion loss, then theefficiency drops to
η =0.63 × PL
Pdc + .27 × PL
= 24%
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 7/25 – p. 7/25
Power Amplifier Considerations
PAs drive large voltages/currents into small loadimpedances. Thus matching networks are critical. Anyloss in the matching network has a severe impact onthe efficiency of the amplifier.
Heat generation is high. We need to carefully provideheat sinks to keep the junction temperatures as low aspossible.
Due to the interface with the external “off-chip” world,packaging and board parasitics are very important.
The spectral “leakage” and harmonic generation in a PAmust be kept to the a minimum in order to minimizeinterference to other users.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 8/25 – p. 8/25
Emitter Follower “PA”
The emitter follower is a popular output stage. It doesnot have any voltage gain but it has a power gain.What’s the efficiency of such an amplifier?
vin
ve vo
IQ
VCC
RL
PL =v2o
2RL
Pdc = VCCIQ
ηc =PL
Pdc
=1
2
vo
RL
vo
VCCIQ
ηc =1
2
(
ioIQ
) (
vo
VCC
)
=1
2iv
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 9/25 – p. 9/25
Normalized Current/Voltage Swing
Apparently in order to maximize the efficiency of thefollower stage, we must maximize the normalizedcurrent swing i and the voltage swing v.
Of course the current and voltage swing are related bythe load impedance, so if it is fixed, we cannotindependently change both.
RL =vo
io
An impedance matching network, therefore, adds onemore degree of freedom to the optimization problem,allowing us to maximize i and v independently.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 10/25 – p
Current Swing
vin
ve vo
IQ
VCC
IQ
Imelt
IQ
Consider the output current io. The BJT can supply anunlimited current to the load during positive excursionsof the input drive but the negative excursion is limited bythe current source IQ.
In order to avoid clipping the waveform, therefore,io ≤ IQ and therefore i ≤ 1.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 11/25 – p
Voltage Swing
The maximum positive output voltage certainly cannotexceed the power supply voltage VCC . Also, if thefollower transistor remains active during the entirecycle, then the maximum voltage is set by the input biaslevel minus VBE.
If the input voltage exceeds the supply, the transistorbase-collector junction forward biases. Under“saturation”, the maximum voltage is therefore given byvomax = VCC − VCE,sat. In reality, we would never pushour transistor this hard because it would generate a lotof distortion.
Likewise, the minimum voltage occurs when wesaturate our current source, at a value of vomin = VCE,sat
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 12/25 – p
Voltage Swing (cont)
VCC VCEsat
VCEsat
VQ,low
VQ,high
VQ,mid
To maximize the swing, we would bias the output at themidpoint
VQ =VCC − 2VCE,sat
2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 13/25 – p
Follower Efficiency
For a follower we see that i ≤ 1 and v depends heavilyon the supply voltage. Let’s take VCC = 3V. Then
v =VCC − 2VCE,sat
2VCC
=1
2− VCE,sat
VCC
Typically VCE,sat ≈ 300mV, and say VCC = 3V. Then
v =1
2− 1
10= 0.4
η ≤ 20%
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 14/25 – p
CE/CS Power Amplifier
vin
vo
VCC
RL
The CE amplifier hasthe advantage ofhigher power gain(there is voltage gainand current gain).The collectorefficiency is given by
ηc =PL
Pdc
=1
2voio
VCCIQ
=1
2v × i
As before, the efficiency is maximized if we can set thevoltage swing and current swing independently.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 15/25 – p
Voltage Swing Waveforms
VCC
VCE,sat
VQ,mid
We see that to avoid clipping, we should bias thetransistor at the midpoint between VCC and VCE,sat.Thus
vo ≤ VCC
2
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 16/25 – p
Current Swing Waveforms
IQ
0A
The current in the transistor cannot go negative.Therefore, the maximum current is set by the biascurrent.
io ≤ IQ
The efficiency is therefore still limited to 25%
η ≤ 1
2× 1
2=
1
4
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 17/25 – p
Optimum Load
It’s important to note that to achieve these optimumefficiencies, the value of the load resistance isconstrained by the current and voltage swing
Ropt =vo
io=
(
v
i
) (
VCC
IQ
)
Since the load resistance is usually fixed (e.g. antennaimpedance), a matching network is required to presentthe optimum load to the amplifier.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 18/25 – p
Inductor Loaded Amplifier
vin
vo
VCC
RL
C∞
RFC
If we AC couple a load RL to the amplifier, then the Qpoint of the amplifier collector voltage is set at VCC
through the choke inductor.
The maximum swing is now nearly twice as large.Notice that the collector voltage can swing above thesupply rail.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 19/25 – p
Inductor Voltage
vin
vo
VCC
RL
+
VCC
+
VC
CVCC
+
Does this bother you? Recall that the voltage polarityacross the inductor is given by dI/dt, which can gonegative. Thus the collector voltage is equal to thesupply minus or plus the absolute voltage across theinductor.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 20/25 – p
Collector Inductor Efficiency
Since the swing is almost double, the efficiency nowapproaches 50%
vo ≤ VCC
η =1
2
iovo
IQVCC
≤ 1
2
In practice, due to losses in the components andback-off from maximum swing to minimize distortion,the actual efficiency can be much lower.
Package parasitics (see later slides) also limit thevoltage swing.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 21/25 – p
Complete PA
vin
vo
VCC
Lres
Cm
Lm R0
Cpar
In practice the collector inductor can double as aresonant element to tune out the collector parasitics.The coupling capacitor Cc can be replaced by amatching capacitor Cm.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 22/25 – p
Package Parasitics
bond pad
package leadbond wire
package lead
bond wire chip
In a normal inexpensive package, the pads of the chipare wire-bonded to the chip leads. Since the aspectratio of the leads is much larger than the pad pitch, longbond wires are required to make the connections,leading to large inductance.
The model of the package/chip should include the pads,the bond wires, as well as the package leads.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 23/25 – p
Emitter Degeneration
vin
vo
VCC
RL
C∞
RFC
+
VLE
Emitter inductance hasa detrimental effect onPA efficiency since itreduces the swing. Thevoltage across theemitter is given by
VE = jωLEio
For a current swing of 1 A at 1 GHz, a typical parasiticinductance of 1 nH will “eat” up 6.28 V of swing! Weneed to reduce LE or to use a much higher VCC .
In practice both approaches are taken. We choose atechnology with the highest breakdown voltage and thepackage with the lowest LE.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 24/25 – p
Advanced Packagingbump
chip via
pads
package lead
bond wirechipdown bond
exposed "paddle"
In flip-chip technology, the chip is flipped and “bumped”onto a carrier substrate (on onto the board directly).This results in small inductance connections.
In an exposed “paddle” package, there is a groundplane inside the package. We use conductive glue tomount the chip onto the package. Short down-bondsthen create low inductance ground connections.
In the extreme case, we can use several down-bonds inparallel surrounding the chip in addition to thinning thedie.
A. M. Niknejad University of California, Berkeley EECS 142 Lecture 26 p. 25/25 – p