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Liquid Design Systems, Inc
Liquid Design Systems, IncSeptember 2009 version
Semiconductor’s IP and EDA distribution venture
Corporate introduction
Index
LDS corporate profileIntroduction of 3D IC-SIS technologiesOur technology and patentsOur business model
Liquid Design Systems, Inc.Semiconductor’s IP and EDA distribution venture.
Founded June 6, 2008Officers Naoya Tohyama (C.E.O.)
Takuya Inoue (C.O.O.)Koichi Kumagai (C.T.O.)
KSP 421B 3-2-1 Kawasaki-city, Kanagawa, Japan 213-0012Phone: +81-44-815-5544Facsimile: +81-44-815-5544http://www.liquiddesign.co.jp
Company Overview
Board members 1/2
Naoya Tohyama C.E.O.CEO, Liquid Design Systems, Inc.Before founding Liquid Design Systems in Jun 2008, he served as VP marketing at System Fabrication Technologies, Inc (SFT) as one of 5 founders since 2003.Prior to joining SFT, he spent 13 years at Cadence Design Systems, Japan, as marketing director.He graduated from State University of New York, Buffalo in 1985, and learned MBA essence course at SANNO Institute of Management in 2008.
Takuya Inoue C.O.O.Regional Director of Altium Japan KK. a leading supplier with low price PCB and FPGA CAD, from 2006 to 2008Semiconductor Industrial Research Manager at IDC Japan, a global market research firm, from 2003 to 2005Operation Manager for PCB & System Business of Cadence Design Systems Japan KK Account Manager at Synopsys Japan KK as a lead for Toshiba businessSales Representative at Texas Instruments Japan for 9 years after graduating universityBS of Industrial Engineering at Musashi Institute of Technology
Board members 2/2Koichi Kumagai, CTO1986-2004 NEC and NEC Electronics ASIC/SoC- circuit design、process design and development2004.8、-2008 System Fabrication Technologies, Director of R &D- System in Silicon2009.1 Liquid Design Systems, CTOTohoku university graduate school
Tokinori Kozawa, executive director2008.9 Liquid Design Systems Executive director2006-2008 ASIP Solutions, Inc., Board director1996-2005 Semiconductor Technology Academic Research Center (STARC) Board director1965-2000 Hitachi Central Research Laboratory Chief Engineer, director Membership
– Fellow, The Institute of Electronics, Information and Communication Engineers, Japan– IEEE Computer Society Golden Core Member– Design Automation Conference (DAC) Asia committee member (1988-1992)– Asia South Pacific Design Automation Conference (ASPDAC) General Chair (1998)– Design Automation and Test in Europe committee member as Asian Representative (1998-2002)– Euro- DAC Topics Chair (1994-1996)
Sigehisa Wakamtsu, executive director1966-2004 NEC, Semiconductor div.
– Manager of ASIC(Gate Array、SoC) development group.– After the previous group, director of Semiconductors’ IPs (patents) group
2004-2008、 System Fabrication Technologies, Inc Board director2008.9 Liquid Design Systems, Executive director
Index
LDS corporate profileIntroduction of 3D IC-SIS technologiesOur technology and patentsOur business model
The potential market of 3DIC chips
32
64
128
256
512
0.5 1 2 4 8 16 Bandwidth (GB/s)
SIP withgenericDRAM
EmbeddedDRAM SoC
Customer Requirement(Our 3D IC architecture)
SIP with generic DRAM eDRAMSoC
Bus width NG (~32bit) OK
Capacity OK(16M~1G) NG(~64M)
Power NG OK
Time to market OK NG
Cost (NRE) OK NG
ASIC pin-count NG (Bonding limit) OK
Memory Capacity(Mbit)
1G
Recent trend of high-end technologies
High speed BUS– Design difficulty of DDR with expensive patent cost– Larger embedded memory capacity (more than 256Mbit)
TSV(Through Silicon Via)– Takes another 2-4 years for mass production cost level– Many players now participate
Japan: Toshiba, Renesas, Elpida/ Qimonda, Zycube, …Inter’n: IBM, Samsung, Fraunhofer, ITRI, IME, CEA-LETI, …
Silicon interposer in Japan – getting common technologyDNPShinkoRenesas (Resin interposer)And more player are coming
Basic concept of SIS-3D IC Architecture
SiIP (Silicon Interposer)
SoC Memory (SISRAM)
Micro Bump
Micro-bumps for the high density connection10% Lower thermal resistance compared to conventional SoCUsing & improving existing EDA and manufacture equipment
Structure of SIS - top view
【 image 】
ASIC
IF Macro
SoC
SISRAMSi interposer
PAD
I/O buffer
Bonding wire
interposer
Stitch
package
【image 】
SoC
Micro-bumps connecting between SoC and
SISRAM(memory)
I/F macro
Si interposer
SISRAM
Our technology was accepted by ISSCC-2006 and ECTC2008 by Kumagai (CTO)
System-in-Silicon Architecture and its Applicationto H.264/AVC Motion Estimation for 1080HDTV
-1-K. KUMAGAI, et al.May 27 – 30, 2008
A Silicon Interposer BGA Package A Silicon Interposer BGA Package with Cuwith Cu--filled TSV and filled TSV and MutiMuti--Layer Layer
Cu Plating InterconnectCu Plating Interconnect
Kouichi Kumagai1, Yuko Yoneda1, Hitoshi Izumino1, Hiroko Shimojo1,Masahiro Sunohara2, Takashi Kurihara2, Mitsutoshi Higashi2,
Yoshihiro Mabuchi1
1System Fabrication Technologies, Inc., Yokohama, Japan 2Shinko Electric Industries Co., LTD., Nagano, Japan
Example of 3D IC model 2 - 2 sides stuck
DRAM
SoC
T/H Under fill
Mother board Bottom-PKG
Top-PKG(BGA)
DRAM
DRAM
DRAM
Source: Sorbus memory
Index
LDS corporate profileIntroduction of 3D IC-SIS technologiesOur technology and patentsOur business model
SISRAM memory stack structure
BANK0BANK1BANK3
BANK2
SoC
DRAM DRAM
•Encapsulated active layers• High thermal conduction through μ-Bumps
BGA with TSVHigh terminal densityVG supply improvement
Memory Stackw/ Wafer-on-Wafer Tech.(for large bit capacity
~4Gbit)Improvement of the datatransfer rate>DDR3-1600 DIMM Dual Channel~30GBps with Random burst
•Reduction of outer balls•Hard IP lineups:FLASH / High speed IO / Voltage regulator …
Platform
Micro bump (~20um)Cost down of Silicon Interposer
Stackable DRAMw/ bank architecture
(Bottom view)Solder bumps
(~150um)
SiS =
SIS with TSV (Through Silicon Via)
Heat Spreader
SiliconInterposer
SoC
Piercedelectrode
SISRAM memory
LDS Technology Patents
Filed in Japan・・・・6Under Examination・・・・9
AbroadFiles in China ・・・・1PCT・・・・・・・・3 (Under examination)Taiwan・・・・・・2 (Under examination)
Score(3rd organization evaluation)IPB patent score:Rating A+ ~ A-
LDS 6 Filed patentsT i t l e o f t h e i n v e n n t i o n
J a p a n e s e P a t e n tA p p l i c a t i o n N o
J a p a n e s e P a t e n t N o O v e r V i e w
S e m ic o n du c to r M e m o ry D e v ic e J P 2 0 0 5 - 2 3 2 1 6 04 0 9 9 4 9 9
( 2 0 0 8 - 3 - 2 1 )
S IS RAM C irc u itA s e m ic o n du c to r m e m o ry de v ic e h a s th e da ta in pu t bu f f e r 6 0 a n d th e da ta o u tpu t bu f f e r 1 0 0in de pe n de n t f ro m e ac h o th e r , bu rs ts f o r w r it in g a n d re a d in g th e da ta c a n a c c e s s w ith n o t t im ela g .A ls o , th e s e m ic o n du c to r m e m o ry de v ic e c a n w r ite th e da ta in to m e m o ry ba n k 8 0 a n d 9 0 o n ea f te r a n o th e r , d iv id in g th e da ta in to 5 1 2 - b it c h u n k s , c o n ve rt th e 5 1 2 - b it da ta re a d f ro m m e m o ryban k s 8 0 a n d 9 0 to s e r ia l da ta a n d re a ds it to o u ts ide o n e a f te r a n o th e r
S e m ic o n du c to r D e v ic e J P 2 0 0 5 - 2 1 5 9 8 93 7 7 4 4 6 8
( 2 0 0 6 - 2 - 1 4 )
S IS ba s ic s tru c tu reIn m o u n tin g a m e m o ry de v ic e c h ip 1 0 3 a n d a n AS IC 1 0 4 o n a w ir in g c h ip 1 0 2 , c o n n e c tio n pa ds 1 1 0 ,1 1 6 a re re s pe c tiv e ly f o rm e d a lo n g o n e o ppo s in g s ide s o f th e m e m o ry de v ic e c h ip 1 0 3 a n d th e AS IC1 0 4 o n th e w ir in g c h ip 1 0 2 , th e a rra n g e m e n t po s it io n s o f th e re s pe c tiv e c o n n e c tio n pa ds 1 1 0 , 1 1 6de f in e th e s h o rte s t d is ta n c e a s s u m e s th e s h o rte s t d is ta n c e . A n d , c o n n e c tio n pa ds 1 1 0 , 1 1 6 a rere s pe c tiv e ly a rra n g e d a lo n g o n e s ide th e re o f in a s ta g g e re d pa tte rn .
S e m ic o n du c to r D e v ic e J P 2 0 0 5 - 3 4 6 1 4 83 8 9 5 7 5 6
( 2 0 0 6 - 1 2 - 5 )
M u ltila y e r S e m ic o n du c to r D e v ic eT h e S e m ic o n du c to r D e v ic e ( th e m u lt ila y e r c h ip 5 0 ) c o m pris e s th e m e m o ry de v ic e c h ip 2 0 a n d th ea pp lic a t io n s pe c if ic c h ip (A S IC 3 0 ) im p le m e n te d a s a f lip- c h ip o n th e f irs t m a in s u rf a c e 1 0 A an d th es e c o n d m a in s u rf a c e 1 0 B o f th e w ir in g c h ip 1 0 . A n d th e m e m o ry de v ic e c h ip 2 0 a n d th e A S IC 3 0a re im p le m e n te d in s u c h a w ay th a t th e ir re s pe c tiv e in pu t a n d o u tpu t do m a in s 2 4 a n d 3 4 ( I/ O a rra y )a re f a c in g w ith e a c h o th e r .
S e m ic o n du c to r D e v ic e w ith I/ O A rra y S tru c tu re
J P 2 0 0 5 - 3 6 2 1 4 44 0 9 9 5 0 2
( 2 0 0 8 - 3 - 2 1 )
I/ O A rra y S tru c tu reT h e s e m ic o n du c to r de v ic e h a s u n it c e ll a re a 3 2 . T h is u n it c e ll a re a 3 2 h a s a ra ile d I/ O c irc u ita rra n g e m e n t a re a 3 2 B w h e re th e I/ O c irc u it o f e a c h c o n n e c te d pad to a tte m pt th e c o n n e c tio nw ith th e o u ts ide ( in pu t c irc u it a n d o u tpu t c irc u it) w as a rra n g e d a n d a lo g ic c irc u it a rra n g e m e n t a re a3 2 C th a t a rra n g e s th e lo g ic c irc u it o f th e ra il in th e lo g ic c irc u it a rra n g e m e n t a re a . In a dd it io n , th isu n it c e ll a re a 3 2 h a s a n e le c tro s ta t ic de s tru c tio n p re v e n tio n c irc u it a rra n g e m e n t a re a 3 2 A th a ta rra n g e s th e e le c tro s ta t ic de s tru c tio n p re v e n tio n c irc u it s e t be tw e e n th e pad a n d th e I/ O c irc u it o fc o n n e c te d pa d g ro u p in th e e le c tro s ta t ic de s tru c tio n p re v e n tio n c irc u it a rra n g e m e n t a re a ispo s s e s s e d . T h e s e m ic o n du c to r de v ic e is p ro v ide d to be I/ O a rra y s tru c tu re to c o n n e c t th e a bo ve -m e n tio n e d in pu t c irc u it in th e a bo ve - m e n tio n e d u n it c e ll a re a th a t a rra n g e s u n it c o n c e rn e d c e lla re a 3 2 w ith th e pa d o f c o n n e c te d pa d g ro u p lik e th e a rra y a n d a d jo in s m u tu a lly e le c tr ic a lly .
T e s t C irc u it J P 2 0 0 5 - 3 6 0 9 6 93 8 8 7 6 5 5
( 2 0 0 6 - 1 2 - 8 )
T e s t c irc u itD a ta f o r te s t in g th e p re s e n c e o f th e de f e c t o f th e m e m o ry c e ll w ith B IS T c irc u it 1 3 2 is g e n e ra te da n d m e m o ry c h ip 1 0 3 is o u tpu t to s y s te m c h ip 1 0 4 . O n th e o th e r h a n d , s y s te m c h ip 1 0 4 o u tpu ts tom e m o ry c h ip 1 0 3 a s da ta to m e m o riz e da ta f o r th e te s t in pu t w h e n da ta c o n c e rn e d is o u tpu t w h e nth e m e m o ry c e ll is u s e d f o r th e m e m o ry o f da ta , a n d th e p re s e n c e o f th e de f e c t o f th e m e m o ryc e ll is te s te d in th e m e m o ry c e ll, a n d ju dg e s th e p re s e n c e o f th e de f e c t o f th e m e m o ry c e ll w itha g re e m e n t d is a g re e m e n t c irc u it 1 3 6 o r a g re e m e n t d is a g re e m e n t c irc u it 1 4 2 ba s e d o n da ta f o r th ete s t re a d f ro m th e m e m o ry a rra y 1 3 0 .
S e m ic o n du c to r D e v ic e J P 2 0 0 5 - 3 4 6 6 6 73 9 0 4 5 8 7
( 2 0 0 7 - 1 - 1 9 )
B u m p D am s tru c tu reT h e s e m ic o n du c to r de v ic e h a s a w ir in g c h ip 1 0 w h e re a m e m o ry c h ip 2 0 a n d a n AS IC 3 0 a rem o u n te d . T h e th ic k n e s s o f a g o ld bu m p 1 6 f o r th e e x te rn a l c o n n e c tio n s e t to e n c lo s e c h ipm o u n tin g a re a s 1 8 A a n d 1 8 B in th e w ir in g c h ip 1 0 is e n la rg e d m o re th a n th e th ic k n e s s o f th e g o ldbu m p 1 3 B , 1 3 A f o r th e c h ip m o u n tin g . A dd it io n a lly , th e g o ld bu m p 1 6 f o r a n e x te rn a l c o n n e c tio n iss e t a t p re s c r ibe d in te rv a ls .A s a re s u lt , ru n n in g a g ro u n d o n th e g o ld bu m p 1 6 o f a c o a tin g re s in 4 2 is c o n tro lle d e v e n if m o n e ybu m p 1 6 a n d th e d is ta n c e in th e m o u n tin g a re a 1 8 A , 1 8 B a n d a n o u ts ide c o n n e c tio n w h e re th em e m o ry c h ip 2 0 a n d th e AS IC 3 0 a re m o u n te d a re s h o rte n e d , a n d th e o ve rc o a tin g o f th e c o a tin gre s in 4 2 o n th e g o ld bu m p 1 6 re s in 4 2 is s u re ly p re ve n te d
Index
LDS corporate profileIntroduction of 3D IC-SIS technologiesOur technology and patentsOur business model
Technology knowhow and patents providerDesign service3D IC market developer such as– 3D IC shuttle service– 3D IC patents pooling – 3D IC simulation tool developing
3D IC technology provider
HierarchicalPartitioning
Hierarchical Flattening
Place & RoutePlace & Route
DRC/LVS
RC-Extract
STA
Net-list(verilog)
GDSIIGDSII
LayoutTiming
3DIC Top-level Design
SiIP Design
3DIC Top-level Verification
RC-Extract
STA DRC/LVS
3DIC_Planner
LEF
LayoutTiming
FloorPlanning
ASIC Design
Memory Library
ASICMask Data
SiIP
Mask Data
DEF
LEF LEF
DEF
:LDS
:Commercial tool
Market/Needs
Low cost 3D IC Shuttle service scheme
Customer
Shuttle coordinator
Bare chip
Chip with Bump
Bumping vendor
LDSModule
Define Flow,PDK
•Bumping Tech.•Flip Chip Bonding Tech.•Evaluation•TSV : Future Plan
Si Fabs. Bumping service @shuttle1. tsmc ○2. IBM ---3. Austriamicro X4. AMIS X
Data Die/Module
Tech./Seeds
Patents pool business scheme
LDS(SIS)
IC developerIDMs, IC ventures, etc
Patent pool(LDS operation)
Profits return
Package licensee
Patent/Lawfirm
• Collecting patents• Patents management• Patents catalogue(WEB)• Patents Evaluation• Technical consulting
Patent pool
Patentscore firm
• Patents Rating• Patents screening
IDMs Zycube/Sorbus memory University
• License agreement doc.• Law matters advice• Patent apply work
Work Consignment
Business and technical consultation