Slide 1

Logic FamiliesPrepared by: Ankur ChangelaFan-InFan-in is the number of inputs a gate can handle.Physical logic gates with a large fan-in tend to be slower than those with a small fan-in, because the complexity of the input circuitry increases the input capacitance of the device.Fan-OutThe maximum number of standard logic inputs that an output can drive reliably.Also known as the loading factor.Fan-In & Fan-Out tpLH: delay time in going from logical 0 to logical 1 state (LOW to HIGH)tpHL: delay time in going from logical 1 to logical 0 state (HIGH to LOW)Measured at 50% points.Trise and TfallPropagation Delays

Every IC needs a certain amount of electrical power to operate.Vcc (TTL)VDD(MOS)Power dissipation determined by Icc and Vcc.Average Icc(avg)= (ICCH + ICCL)/2PD(avg) = Icc(avg) x VccPower Requirements

Pd *td=Vcc*C*VLLets take an Example of 1Watt Packaging..

C = 50 fF, Vcc = 3v, VL =0.5VCase 1 td = 1 ns Find out the no of gates that can be accommodated to Packege.

Case 2 gates /packegeFind out the delays.There is always compromise between Power Dissipation & Delay Power Delay Product

IDEAL INVERTER VOLTAGE TRANSFERCHARTERISTIC (VTC)

Actual Inverter Characteristics

VOH -> max output voltage when output is 1VOL -> min output voltage when output is 0VIL ->max i/p voltage which can be interpreted as 0VIH ->min input voltage which can be interpreted as 1NOISE IMMUNITY AND NOISE MARGINS

What happens if noise causes the input voltage to drop below VIH(min) or rise above VIL(max)?The noise immunity of a logic circuit refers to the circuits ability to tolerate noise without causing spurious changes in the output voltage.Noise margin: Figure 8-4.VNH=VOH(min)-VIH(min)VNL=VIL(max)-VOL(max)Example 8-1.Noise ImmunityFigure 8-4: Noise Margin

Figure 8-1Current-Sourcing and Sinking

DIODE LOGIC

HHHReverse BiasABYHHHDIODE LOGIC

HLLReverse BiasForward BiasABYHLLDIODE LOGIC

LHLForward BiasReverse BiasABYLHLDIODE LOGIC

LLLForward BiasForward BiasABYLLLDIODE LOGICABYLLLLHLHLLHHH

AND GateDTL

DTL 0.2 V

Vp=0.9 V0.7 V5 VReverse BiasForward BiasSaturationIcAll volt drops across the RLOW

DTL 0.2 VVp=0.9 V0.7 V5 VReverse BiasForward BiasCut-offIc=0VR = 0v HIGH0.45 V0.45 VDTL

When transistor switches from satn to cut-off, excess charge from the base (reverse base current)has to be removed.Switching ProblemThere is no any mechanism for this reverse base current to flowDTL

5 V5 VPart of the IB flows through thisDual Power SupplyTTL

0.2 V5 VVp=0.9 VIB =5-0.9/4 =1 mA4K0.2 VEmitter Current flowsTTL

5 V5 VVp=1.4 V4K0.2 V0.7 V0.7 VBase Emitter in R.BBase Collector in F.BTransistor in reverse active modeIn reverse mode collector & emitter terminal are interchanged and is very small around 0.02

5 V0.2 VEmitter Current flowsT2 goes offT3 goes off as base current is supplied by IE of T2base current is supplied by Vcc through 1.4k and T4 goes on

5 V5 VEmitter Current flowsT2 goes onT3 goes on as base current is supplied by IE of T2?

5 V5 VEmitter Current flowsT2 goes onT3 goes on as base current is supplied by IE of T2Vp3-Vp1=0.7 will be shared by two diodes Vp1=0.2 VVp2=0.7 VVp3=0.9 V