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University of Connecticut 88 Low-Power Schottky TTL (74LS) V CC =5V 20kW V OUT Q O Q S Q P 1/4 74LS00 quad 2-input NAND 8kW 120W R B R C R CP V A V B Q P2 Q D 4kW 1.5kW 3kW R BD R CD R EP n Vintage 1975 n Scaled Resistors n DTL input Why did we go back to DTL? n The Schottky diodes can be made smaller than Q I , with lower parasitic capacitances, with post 1975 technology (6mm features). n Q S can not saturate, so it is not neccessary to remove its base charge with a BJT. D D1 D D2

Low-Power Schottky TTL (74LS)

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Page 1: Low-Power Schottky TTL (74LS)

University of Connecticut 88

Low-Power Schottky TTL (74LS)VCC=5V

20kΩ

VOUT

QO

QS

QP

1/4 74LS00quad 2-input NAND

8kΩ 120ΩRB RC

RCP

VA

VB

QP2

QD

4kΩ

1.5kΩ 3kΩ

RBD RCD

REP

n Vintage 1975n Scaled Resistorsn DTL input

Why did we go back to DTL?

n The Schottky diodes can be made smaller than QI, with lower parasitic capacitances, with post 1975 technology (6µm features).

n QS can not saturate, so it is not neccessary to remove its base charge with a BJT.

DD1

DD2

Page 2: Low-Power Schottky TTL (74LS)

University of Connecticut 89

74LS Circuit Designn RB and RC. Dominant in

determining dissipation, these were scaled up by a factor of 8.

n RBD and RCD. These were scaled up with RB and RC to maintain reasonable fanout.

n RCP and REP. These affect speed, not power. They were not scaled significantly from 74S.

n DD1 and DD2. DD1 speeds the turn off of QP2. DD2 sinks current from the load. Both improve tPHL.

VCC=5V

20kΩ

VOUT

QO

QS

QP

1/4 74LS00quad 2-input NAND

8kΩ 120ΩRB RC

RCP

VA

VB

QP2

QD

4kΩ

1.5kΩ 3kΩ

RBD RCD

REPDD1

DD2

Page 3: Low-Power Schottky TTL (74LS)

University of Connecticut 90

74LS DC Dissipation

PH =

PL =

DC =

VCC=5V

20kΩ

VOUT

QO

QS

QP

1/4 74LS00quad 2-input NAND

8kΩ 120ΩRB RC

RCP

VA

VB

QP2

QD

4kΩ

1.5kΩ 3kΩ

RBD RCD

REPDD1

DD2

P

Page 4: Low-Power Schottky TTL (74LS)

University of Connecticut 91

Advanced Low-Power SchottkyTTL (74ALS / 54ALS Series)

1/4 74ALS00quad 2-input NAND

n T.I., circa 1985n Derived from 74LS,

but scaled-up resistors further decrease dissipation

n Improved transistor fabrication (3µm oxide-isolated transistors, vs. 6µm junction-isolatedBJT’s for 74LS)

n Novel input circuitry also improves performance, but requires the use of lateral PNP’s.

VCC=5V

60kΩ

VOUT

QO

QS

QP

15kΩ 50ΩRCS RC

RCP

VAVB

QP2

QD

4kΩ

3kΩ 6kΩ

RBD RCD

REP

QSB

40kΩRB

QIBQIA

DSB

DSA

DD1

DD2

Page 5: Low-Power Schottky TTL (74LS)

University of Connecticut 92

74ALS Circuit Designn QSB increases base

drive for QS, and improves tPHL.

n The input emitter followers compensate for the voltage shift of QSB.

n An added benefit is reduced IIL, and improved fanout.

n DSA and DSB remove base charge from QS, improving tPLH.

tPPPDP

4ns (15pF)1mW4pJ

1/4 74ALS00quad 2-input NAND VCC=5V

60kΩ

VOUT

QO

QS

QP

15kΩRCS RC

RCP

VAVB

QP2

QD

4kΩ

3kΩ 6kΩ

RBD RCD

REP

QSB

40kΩRB

QIBQIA

DSB

DSA

DD1

DD2

Page 6: Low-Power Schottky TTL (74LS)

University of Connecticut 93

Fairchild Advanced Schottky TTL (74F /54F Series, a.k.a. FAST)1/4 74F00quad 2-input NAND n 1985, Fairchild

Semiconductorn Improved BJT

fabricationn DTL input with

emitter follower provides good base drive to QS.

n “Miller killer” greatly improves switching performance

VA

VB

QSB

QS

QD QK

QO

QP2

QP

VCC = 5V

DIA

DIB

DSA

DSB

DV

DBK DCK

DCO

VOUT

RB16kΩ

RCS10kΩ

RC4.1kΩ

RCP45Ω

REP5kΩ

RBS15kΩ

DD1

DD2

RBD2kΩ

RCD3kΩ

Page 7: Low-Power Schottky TTL (74LS)

University of Connecticut 94

74F /54F “Miller killer”

n On a low-to-high transition, the voltage at the emitter of QP begins to increase while QO is still on.

n The varactor diode DV conducts, supplying base current to QK. (“K” for “killer”)

n QK turns on, and rapidly dissipates the charge stored in the base-collector capacitance of QO.

n Dynamic power dissipation is reduced by minimizing simultaneous conduction of thepullup and output transistors.

The “Miller killer” circuit speedsup the low-to-high transition:

QS

QD QK

QO

QP2

QP

VCC = 5V

DV

DBK DCK

DCO

VOUT

RCP45Ω

REP5kΩ

DD1

DD2

RBD2kΩ

RCD3kΩ

Page 8: Low-Power Schottky TTL (74LS)

University of Connecticut 95

74F /54F Electrical Characteristics

VOH / VOLVIH / VILFanoutPtPPDP

4.3 / 0.5V2.1 / 1.8V104mW2.5 ns ( 15pF )10 pJ

1/4 74F00quad 2-input NAND

VA

VB

QSB

QS

QD QK

QO

QP2

QP

VCC = 5V

DIA

DIB

DSA

DSB

DV

DBK DCK

DCO

VOUT

RB16kΩ

RCS10kΩ

RC4.1kΩ

RCP45Ω

REP5kΩ

RBS15kΩ

DD1

DD2

RBD2kΩ

RCD3kΩ

Page 9: Low-Power Schottky TTL (74LS)

University of Connecticut 96

Advanced Schottky TTL (74AS /54AS Series)

1/6 74AS04 hex inverter

QS

QD QK

QO

QP2

QP

VCC = 5V

DV

DBK

DCO

VOUT

RBOD30kΩ

RC2kΩ

RCP26Ω

REP5kΩ

DP

RBD1kΩ

RCD2kΩ

RCk100Ω

RBk25kΩ

QOD

QS2

DS2

RB10kΩ

QI

QIC

VIN

DSI

RBP150kΩ

RBP21kΩ

QP3

DR1

DR2

Page 10: Low-Power Schottky TTL (74LS)

University of Connecticut 97

74AS / 54AS Circuit Design

n Texas Instruments, circa 1985, derivative of 74LS seriesn Input Transistor. Uses a PNP emitter follower like 74ALS. This

lowers IIL and improves the fanout.n Input Clamping. QIC replaces the input clamp diode used in

other designs.n Miller killer. The Miller killer is similar in design and operation to

the subcircuit used in the 74F series.n Pullup . QP3 increases the base drive for QP2 and also provides

extra current to DV in the “Miller killer.”n DP and DS2 help to discharge the base of QP2 during a high-to-

low transition.

Page 11: Low-Power Schottky TTL (74LS)

University of Connecticut 98

ECL 100k

Logic Family Comparison

0.1

1

10

100

0.1 1 10 100

74LS

74

74ALS

74F

74AS 74SECL 10k

930

50 pJline

ECL III

RTL

Po

wer

Dis

sip

atio

n (

mW

)

tP (ns) w/ 15 pF load

Within a particular family of logic gates, the PDP is fixed. Scaling resistors results in an even tradeoff between the power dissipation and the propagation delay.

Improvements in the PDP result from circuit and device improvements.

Page 12: Low-Power Schottky TTL (74LS)

University of Connecticut 99

TTL Off-Chip Data Rates

n State-of-the-art CMOS circuits (0.35µ m feature size in 1997 A.D.) achieve on-chip propagation delays of about 100 ps!

n Driving highly capacitive off-chip loads, TTL outstrips CMOS by a factor of 2.5.

n Motherboards for PC’s and workstations use TTL extensively ... but this is changing as BiCMOS gains ground.

02468

1012

0 50 100

74ACT CMOS

74ALS (1mW)

74F (4mW)74AS (20mW)

tP (ns)

CL (pF)

Page 13: Low-Power Schottky TTL (74LS)

University of Connecticut 100

TTL Logic Design Concepts

Page 14: Low-Power Schottky TTL (74LS)

University of Connecticut 101

TTL AND Gate

n Operation is similar to that of the NAND gate, but an extra inversion stage has been added.

n With all high inputs, QIis RA, QS2 and QSD are SAT, QS and QO are CO, and QP is FA.

n With a low input, QI is SAT, QS2 and QSD are CO, QS and QO are SAT, and QP is CO.

1/4 5408 / 7408quad 2-input AND

RB4kΩ

RC1.6kΩ

RCP130Ω

RD1kΩ

VOUT

VCC=5V

QO

VAQI QS

QP

DL

VB

RCS2kΩ

QSD

RSD800Ω

QS2

DS

NAND

AND

Page 15: Low-Power Schottky TTL (74LS)

University of Connecticut 102

TTL NOR Gaten The NOR gate acts like

two inverters, with paralleled drive splitters and a shared totem pole output.

n With a high input at A, QIAis RA, QSA and QO are SAT, and QP is CO.

n With both low inputs, QIAand QIB are SAT, QSA and QSB are CO, QO is CO, and QP is FA.

n The use of multiple emitters results in the “AND-OR-Invert” function.

1/4 5402 / 7402Quad NOR Gate

RBA4kΩ

RC1.6kΩ

RCP130Ω

RD1kΩ

VOUT

VCC=5V

QO

VAQIA

QSB

QP

DLVB

QSA

RBB4kΩ

QIA

Page 16: Low-Power Schottky TTL (74LS)

University of Connecticut 103

TTL AND-OR-Invert Gatesn Multiple-emitter BJT’s

perform ANDing.n Drive splitters provide

the OR function. Together, the drive splitters and input transistors make up a “three-input expander.”

n The output stage is inverting as usual. Output stages are available alone and are called “line drivers.”

Shown is a“Three-input, two-wide”AND-OR-Invert Gate.

RBA4kΩ

RC1.6kΩ

RCP130Ω

RD1kΩ

VOUT

VCC=5V

QO

QIA

QSB

QP

DL

QSA

RBB4kΩ

VA

VB

VC

QIAVA

VB

VC

Page 17: Low-Power Schottky TTL (74LS)

University of Connecticut 104

TTL XOR Gate1/4 5486 / 7486quad 2-input XOR

VA QX1VB QX2 VOUT

RC1.6kΩ

RCP130Ω

RD1kΩ

VOUT

VCC=5V

QO

QS

QP

DL

RCX2kΩ

QX1

QX2

RBA4kΩ

RC1.9kΩ

1.2kΩ

VAQIA QSA

QSDA

RBB4kΩ

RC1.9kΩ

1.2kΩ

VBQIB QSB

QSDB

Page 18: Low-Power Schottky TTL (74LS)

University of Connecticut 105

Open Collector TTL

n An “open-collector” TTL output can sink current, but can not source current.

n External pullup (inherently passive) is used.

n Open collector outputs can be wired together, resulting in the ANDing of those outputs.

4kΩ 1.6kΩ

1kΩ

VOUT

VCC=5V

QO

VA

VB

VC

QI QS

Page 19: Low-Power Schottky TTL (74LS)

University of Connecticut 106

“Wired Logic” with Open Collector TTL

n If either output A or B goes low, then C goes low. Hence, the wiring together of TTL open collector outputs results in the creation of the AND function.

n Wired logic cannot be implemented successfully with totem pole outputs. Can you see why?

A

B

C

A

B

C

Page 20: Low-Power Schottky TTL (74LS)

University of Connecticut 107

Integrated Injection Logic (I2L)

Page 21: Low-Power Schottky TTL (74LS)

University of Connecticut 108

I2L

n TTL gates with even modest performance involve fairly complex circuits with low packing density. (74LS permits a packing density of 20 gates mm2 using 5µ m technology.)

n I2L allows a factor of ten improvement in packing density compared to 74LS - even approaching the packing density of CMOS.

n I2L exhibits much better PDP’s than TTL - even as low as 1 pJ!

BUT... n I2L can’t compete with CMOS in terms of DC dissipation.n I2L exhibits a small logic swing compared to TTL or CMOS.

Page 22: Low-Power Schottky TTL (74LS)

University of Connecticut 109

Basic I2L

n The output transistors switch between cutoff and saturation.n Multiple collectors are connected together to form “wired logic,” in

similar fashion to open collector TTL outputs.n How is “current hogging” prevented?n What determines the fanout for I2L?n What determines VOH?

The basic I2L building block is a multi-collector BJT with a current source driving the base.

IO

A Q1

IO

B Q2

IO

Q3

A B

A+B

A+B

VCC

Page 23: Low-Power Schottky TTL (74LS)

University of Connecticut 110

I2L and “Merged Transistors”

n The base of the PNP and the emitter of the NPN are both n-type, and connected to ground. They can be “merged.”

n Similarly, the PNP collector and NPN base are “merged.”n Sometimes, I2L is also called MTL (Merged Transistor Logic).n Whatever you call it, the structure is compact and results in high

packing density in gates / mm2.

VCC

p

np

pn

n output

inputVCC

Page 24: Low-Power Schottky TTL (74LS)

University of Connecticut 111

Fabrication of Merged BJT’s

n The PNP is lateral; the NPN is vertical, but “upside down.”n All of the ground connections are made through the substrate,

saving area on the top surface.n The resistors and PNP emitters (“injector rails”) may be shared

by multiple cells (“gate bars”) to further improve the packing density.

n+

n+ substrate

n+n epitaxial layer

n+

C1

p n+ n+p

C3C2input

VCC

Page 25: Low-Power Schottky TTL (74LS)

University of Connecticut 112

Standard I2L Characteristicsn Fantastic on-chip

PDP’s have been achieved (< 1pJ) with a 1V supply

n Off-chip loads are driven through TTL level translators.

n The packing density is ten times better than for 74LS.

n Fanout is limited to about 5.

1nW 10 100 1µW 10 100 1mW

1ms

100

10

1µs

100

10

1ns

pro

pag

atio

n d

elay

power dissipation

Page 26: Low-Power Schottky TTL (74LS)

University of Connecticut 113

Advanced I2L Circuitryn Schottky Integrated Injection Logic. The multiple collector

regions are replaced by Schottky diodes. This improves the packing density. In addition, the reduced voltage swing improves the propagation delays.

n Schottky Transistor Logic. STL is similar to Schottky I2L, but the switch transistors are Schottky clamped. Great performance has been demonstrated (0.2 pJ, 2.5 ns). The problem is complicated fabrication (two types of Schottky diodes must be made to allow finite voltage swing) and consequently low yield.

n Integrated Schottky Logic. ISL is similar to Schottky I2L with two changes: The switch NPN is fabricated with the collector on thebottom and is clamped by an extra PNP.