國立中山大學電機工程學系

碩士論文

Department of Electrical Engineering

National Sun Yat-sen University

Master Thesis

單一神經元仿真器和前級電路之膜片鉗制設置

A Neuron Emulator and Headstage Circuit

for Patch Clamp Setups

研究生：吳彥徵

Yen-Cheng Wu

指導教授：勞伯特律格 博士

Advisor：Robert Rieger, Ph.D.

中華民國 101 年 7 月

July 2012

國

立

中

山

大

學

電

機

工

程

學

系

碩士論文

單一神經元仿真器和前級電路之膜片鉗制設置

研究生：吳彥徵

100

學年度

0學年度

國立中山大學電機工程學系

碩士論文

Department of Electrical Engineering

National Sun Yat-sen University

Master Thesis

單一神經元仿真器和前級電路之膜片鉗制設置

A Neuron Emulator and Headstage Circuit

for Patch Clamp Setups

研究生：吳彥徵

Yen-Cheng Wu

指導教授：勞伯特律格 博士

Advisor：Robert Rieger, Ph.D.

中華民國 101 年 7 月

July 2012

i

中英文論文審定書

ii

iii

Acknowledgements

This thesis is an international collaborative project between Dr. Ying Sun and Dr.

Robert Rieger. Dr. Ying Sun is a professor and director of the biomedical engineering

program in the Department of Electrical, Computer and Biomedical Engineering at the

University of Rhode Island; Dr. Robert Rieger is a professor and director of Bionics

Integrated Systems Laboratory at National Sun Yat-Sen University (NSYSU). The

project was initiated in the summer of 2010 while Dr. Sun was a visiting scholar at

NSYSU. By the time, Dr. Sun and Dr. Rieger synergized their research interests, the

biopotential recording and biomedical instrumentation, to come up with this research

idea.

First of all, I would like to acknowledge Dr. Rieger for his encouragement,

guidance and strong support as my supervisor. I would like to also acknowledge Dr. Yin

Sun for his comments and guidance when he was in Taiwan. I deeply appreciate the

advice and suggestions from Prof. Jia-Jin Chen, Prof. Jih-Ching Chiu, Prof. Chung- Yao

Kao, and Prof. Robert Rieger as the oral defense committee. Special thank is given to

Prof. Jau-Cheng Liou at NSYSU for his generousness. The research would have not

been verified without his support to allow me to use the MultiClamp 700B instrument in

his lab.

I am indebted to many of my colleagues, to name some, Hsin-Lang Teng,

Jing-Yuan Chen, Wan-Ting Lin, Shi-Hao Ou, Jang-Ming Nien. The discussions between

us help a lot in brainstorming. I would like to show my gratitude to my sister, Hsuan-Yi

Wu, and laboratory assistants, Bao-Ting Shih and Pranab Majumdar, for their efforts on

proof-reading. I owe my deepest gratitude to my parents,Tong-Ping Wu and Mei-Chu

Huang; it is impossible to continue the academic career until now without their financial

iv

and spiritual support. Last but not least, thanks to many friends, Yen-Cheng Kao,

Wan-Hsuan Lo, Ya-Fan Su, Ren-Tzer Wang, Wei-Hsiang Chou, , Kuan-Hung Chen

Shang-Jen Yang, Samy Sidis, members of student ambassador and staffs in international

affairs department for their accompanying all the way while I am under huge pressure.

v

摘要

本論文呈現單一神經元仿真器和前級電路之膜片鉗制設置，其中包含模擬、

量測和驗證之結果。此電路被實現在一個印刷電路板上，可被電池驅動且便於攜

帶。使用前級電路從單一電極端來觀察，仿真器提供單一活神經元之被動(靜息電

位)和主動(動作電位)的電子特性，這可作為測試像電流鉗制、電壓鉗制或膜片鉗

制放大器等電生理的設備。微處理器控制動作電位被以電壓和頻率相關的方式產

生在閥值發射電壓為-60 mV到-30 mV 之間的發射頻率為 1 Hz 到 10 Hz，起初，電

荷儲存 110 pC 在電容上，藉由發射神經元，電荷被釋放。與直接用單一電流或電

壓源相比較下，這設計導致更理想化的模擬動作電位根據離子電流在單一活神經

元產生的情形。從原型的測試結果顯示，神經元仿真器符合設計的規格且這能夠

呈現電壓鉗制和速率響應的電流鉗制功能。使用商用的鉗制放大器在實際的記錄

環境下，得到的量測結果證實仿真器運作。

關鍵詞：膜片鉗制、神經元模擬電路、動作電位、電流鉗制、電壓鉗制

vi

Abstract

This thesis presents a neuron emulator and headstage circuit for patch clamp setups

and provides simulation, measurement and verification results. The circuit implemented

on a printed circuit board (PCB) is battery powered and portable. The emulator provides

both passive (resting potential) and active (action potential) electrical properties of a live

neuron as seen from a single electrode by using the headstage circuit. It can be used to

test electrophysiological equipment such as current-clamp, voltage-clamp or patch-clamp

amplifiers. The action potentials (APs) are generated with a voltage-dependent frequency

controlled by a microcontroller implementing a firing range from -60 mV to -30 mV and

firing frequency from 1 Hz to10 Hz. The charge released by firing the neuron is initially

stored on a 110 pC capacitor. Compared to directly using a current or voltage source, this

design results in a more realistic simulation of the APs generated by ionic currents in a

live neuron. The measured results from a prototype demonstrate that the neuron emulator

meets the design specifications and it is capable of performing voltage clamp and rate

responsive current clamp functionality. Measured results using a commercial clamp

amplifier are provided to confirm the emulator operation in a practical recording

environment.

Keywords：neuron emulator, patch clamp, voltage clamp, action potential, single

electrode, headstage

vii

Contents

中英文論文審定書 ........................................................................................................... i

Acknowledgements ........................................................................................................ iii

摘要 ................................................................................................................................. iii

Abstract .......................................................................................................................... vi

List of Figures ................................................................................................................. x

List of Table .................................................................................................................. xiii

List of Abbreviations ................................................................................................... xiv

List of Symbols .............................................................................................................. xv

Chapter 1 Introduction .................................................................................................. 1

1.1 Background ........................................................................................................................................ 1

1.2 Objectives .......................................................................................................................................... 5

1.3 Thesis Chapter Overview ................................................................................................................... 6

Chapter 2 Background for Neuron Model Design ....................................................... 8

2.1 Membrane Potential (MP) ................................................................................................................. 8

2.2 Hodgkin-Huxley Model ................................................................................................................... 12

2.3 Voltage Clamp Technique ................................................................................................................ 14

2.4 Patch Clamp Technique ................................................................................................................... 15

Chapter 3 Circuit Designs ............................................................................................ 17

3.1 Introduction ..................................................................................................................................... 17

3.2 Neuron Emulator and Headstage Circuit Specification ................................................................... 17

3.2.1 Cell Model with AP Generation ............................................................................................... 19

3.2.2 Simplified Model for the Neuron Cell ...................................................................................... 21

viii

3.2.3 Simplified AP Generator .......................................................................................................... 22

3.3 Headstage Amplifiers ....................................................................................................................... 24

3.3.1 Neuron Emulator in C_C ......................................................................................................... 25

3.3.2 Neuron Emulator in V_C.......................................................................................................... 26

3.4 Comparison with CV-7B Headstage ................................................................................................ 28

3.4.1 CV-7B Headstage in C_C ........................................................................................................ 29

3.4.2 CV-7B Headstage in V_C ......................................................................................................... 30

Chapter 4 Simulated Results ....................................................................................... 31

4.1 Introduction ..................................................................................................................................... 31

4.1.1 Cell Model with AP Generation ............................................................................................... 31

4.1.2 Simplified AP Generator .......................................................................................................... 32

4.2 Headstage Amplifiers ....................................................................................................................... 33

4.2.1 Neuron Emulator in C_C ......................................................................................................... 33

4.2.2 Neuron Emulator in V_C.......................................................................................................... 35

4.3 Comparison with CV-7B Headstage ................................................................................................ 38

4.3.1 CV-7B Headstage in C_C ........................................................................................................ 38

4.3.2 CV-7B Headstage in V_C ......................................................................................................... 39

Chapter 5 Hardware Implementation ........................................................................ 40

5.1 Choice of Components .................................................................................................................... 40

5.1.1 Microprocessor Programming ................................................................................................. 42

5.1.2 AP Generator ........................................................................................................................... 45

5.1.3 Current Clamp Amplifier ......................................................................................................... 46

5.1.4 Voltage Clamp Amplifier .......................................................................................................... 46

5.2 Printed Circuit Board Operation ...................................................................................................... 46

5.3 Experimental Results ....................................................................................................................... 49

5.3.1 Results of Current Clamp Mode ............................................................................................... 49

5.3.2 Results of Voltage Clamp Mode ............................................................................................... 53

5.4 Results of Neuron Emulator Mode for CV-7B Headstdage ............................................................. 55

5.4.1 CV-7B Headstdage in C_C ...................................................................................................... 55

ix

5.4.2 CV-7B Headstdage in V_C ....................................................................................................... 57

5.5 Comparison ...................................................................................................................................... 58

Chapter 6 Conclusions and Future Work .................................................................. 61

References ...................................................................................................................... 63

Appendix ..................................................................................................................... - 1 -

A. Equivalent circuits representing the functions provided by the microcontroller ........................... - 1 -

A1. Rest Potential Extractor (RP Extractor) .................................................................................. - 1 -

A2. Voltage Controlled Oscillator (VCO) ...................................................................................... - 3 -

A3. Threshold Comparator ............................................................................................................ - 5 -

B. Assembly code for microcontroller ................................................................................................ - 7 -

x

List of Figures

Fig. 1.1: Principle setup for patch clamp recording of membrane currents. A physical

and electric seal is formed between cell membrane and pipette..................... 2

Fig. 2.1: Diffusion and transportation behavior of ion transporters and ion channels [24]

........................................................................................................................ 8

Fig. 2.2: Ions permeability changes and AP stages in a neuron [25, 27-30] ................ 10

Fig. 2.3: The dependence of AP firing frequency on the level of depolarization [24] . 12

Fig. 2.4: Membrane equivalent electrical circuit model ............................................... 13

Fig. 2.5: Voltage clamp technique for studying membrane properties ......................... 14

Fig. 2.6: Configurations in patch clamp measurements of ionic currents .................... 16

Fig. 3.1: The block diagram of a Neuron Emulator and Headstage Circuit ................. 17

Fig. 3.2: Circuit schematic of potassium and sodium currents contributed to AP ....... 19

Fig. 3.3: Neuron cell equivalent model ........................................................................ 21

Fig. 3.4: AP Generator circuit in two states .................................................................. 23

Fig. 3.5: Headstage consisting of current and voltage clamp amplifiers. ..................... 24

Fig. 3.6: Neuron Emulator circuit for current clamp experiment. Shaded areas will be

implemented on a microcontroller (see Appendix A) ................................... 25

Fig. 3.7: Neuron Emulator for voltage clamp experiment. Shaded areas will be

implemented on a microcontroller (see Appendix A) ................................... 26

Fig. 3.8: Schematic of the AP Generator connected to CV-7B Headstage ................... 29

Fig. 4.1: Simulated Results of Potassium and Sodium Ions contributed to AP ............ 31

Fig. 4.2 (a) and (b) : AP simulation result with Iclamp = 0 nA and 8 nA ........................ 32

Fig. 4.3 (a): Simulated Result of AP Generator in C_C ............................................... 33

Fig. 4.3 (b): Parametric analysis simulation result for emulator circuit in C_C........... 34

xi

Fig. 4.4 (a): Simulated result of AP Generator in V_C................................................. 36

Fig. 4.4 (b): Simulated result of Neuron Emulator circuit in V_C ............................... 37

Fig. 4.5: AP Generator for CV-7B Headstage simulation in C_C ................................ 38

Fig. 4.6: AP Generator for CV-7B Headstage simulation in V_C ................................ 39

Fig. 5.1: The block diagram implementation of the neuron emulator and headstage

circuit ............................................................................................................ 40

Fig. 5.2: Detailed schematic of the neuron emulator and headstage circuit ................. 41

Fig. 5.3 (a): Time-sequence diagram of AP v.s. clock phase ........................................ 43

Fig. 5.3 (b): Flow diagram of the microprocessor program code to generate rate

responsive APs .............................................................................................. 44

Fig. 5.4: AP Generator circuit of RP phase state (left) and AP phase state (right) ....... 45

Fig. 5.5: Photograph of a prototype implementation on a custom-made PCB. ............ 47

Fig. 5.6: Block diagram of the prototype testing setup ................................................ 47

Fig. 5.7: The control signal φap from the microprocessor (top) and the experimental

recording of the APs from the prototype (bottom) ....................................... 50

Fig. 5.8: Oscilloscope screenshots to show the membrane voltage (Vclamp, CH1),

electrode voltage (Ve, CH2) and switch control signal (φap, CH3) as the

clamp current Iclamp is varied. The AP frequency increases as the RP increases

over to the firing threshold -60 mV. ............................................................. 52

Fig. 5.9: Annotated oscilloscope screenshot of the voltage clamp experiment. ........... 54

Fig. 5.10: Measured neuron emulator by MultiClamp 700B from the software of

oscilloscope screenshot of the CV-7B Headstage in the current clamp mode.56

Fig. 5.11: Measured Neuron Emulator by MultiClamp 700B from the software of

oscilloscope screenshot of the CV-7B Headstage in the V_C. ..................... 57

Fig. A1.1: RP Extractor circuit diagram ..................................................................... - 2 -

xii

Fig. A1.2: RP Extractor transient simulation result .................................................... - 2 -

Fig. A1.3: RP Extractor frequency response .............................................................. - 2 -

Fig. A2.1: Voltage Controlled Oscillator circuit diagram ........................................... - 4 -

Fig. A2.2: Simulated result of VCO circuit ................................................................ - 5 -

Fig. A3.1: Threshold Comparator circuit .................................................................... - 5 -

Fig. A3.2: Simulated result of Threshold Comparator circuit .................................... - 6 -

xiii

List of Table

Table 2.1: AP of neuron axon hillock ............................................................................. 9

Table 3.1: A Neuron Emulator and Headstage Circuit for Patch Clamp Setups

Specification ................................................................................................. 18

Table 3.2: The parameters of AP generator circuit ....................................................... 23

Table 4.1: The circuit parameters of ions’ currents contributed to AP ......................... 32

Table 4.2 (a): The results of AP Generator simulation in C_C ..................................... 34

Table 4.2 (b): The results of Neuron Emulator circuit simulation in C_C ................... 35

Table 4.3 (a): The spike parameter table of AP Generator simulation in V_C ............. 36

Table 4.3 (b): The spike parameter table of Neuron Emulator circuit simulation in V_C

...................................................................................................................... 37

Table 4.4: The parameter table of AP Generator for CV-7B Headstage in C_C .......... 38

Table 4.5: The parameter table of AP Generator for CV-7B Headstage in V_C .......... 39

Table 5.1: The truth table of three switches mode in the prototype ............................. 48

Table 5.2: The headstage specification comparison table ............................................ 59

Table 5.3 (a): The comparison table of components and voltage sources .................... 60

Table 5.3 (b): The comparison table of components values ......................................... 60

Table A2.1: The parameters of VCO circuit. .............................................................. - 3 -

Table A3.1: The truth table of Threshold Comparator circuit. ................................... - 6 -

xiv

List of Abbreviations

ADC Analog-to-Digital Converter

AP Action Potential

ASIC Application-Specific Integrated Circuit

C_C Current Clamp Mode

G Gain

GND Ground Reference

H-H Model Hodgkin-Huxley Quantitative Model

H(S) Transfer Function

LPF Low Pass Filter

MP Membrane Potential

N_E Neuron Emulator Mode

Op-Amp Operational Amplifier

RP Resting Potential

V_C Voltage Clamp Mode

VAC Alternating Voltage

VCO Voltage Controlled Oscillator

VDC Constant Voltage

VDD Positive Supply Voltage Source

VSS Negative Supply Voltage Source

xv

List of Symbols

Cap Action Potential Capacitor

Cf Capacitor of Voltage Controlled Oscillator

CK Potassium Capacitor

Cm Membrane Capacitor

CNa Sodium Capacitor

fap Oscillator Frequency of Voltage Controlled Oscillator

gm Conductance of Voltage Controlled Oscillator

Iap Action Potential Current

Iclamp Clamp Current

Ipp Peak to Peak Current

GCl-- Chlorine Conductance

Gk+ Potassium Conductance

GLeak Leakage Conductance

GNa+ Sodium Conductance

Rap Action Potential Resistor

RCl- Chlorine Resistor

Re Electrode Resistor

RI Variable Resistor of Current Source

Rk+ Potassium Resistor

Rm Membrane Resistor

RNa+ Sodium Resistor

Roff Offset Variable Resistor

RLeak Leakage Resistor

xvi

Rv Single-Turn Potentiometer

Vap Action Potential

Vclamp Clamp Voltage

Vcmd Command Voltage

Vconst. Constant Voltage of VCO

Vctrl Amplitude Controlled Voltage of VCO

Vdd Supply Voltage

Ve Electrode Voltage

Vf Frequency Controlled Voltage of Voltage Controlled Oscillator

Vm Membrane Potential

Vp Pipette Voltage

Vpp Peak to Peak Voltage

VpNa Sodium Spike Potential

VpK Potassium Spike Potential

Vrest Resting Membrane Potential

Vspike Spike Potential

Vth Threshold Potential

VthH High Threshold Potential

VthL Low Threshold Potential

VNa Sodium Action Potential

VK Potassium Action Potential

φap Acting Phase

φde Depolarization Phase

φre Repolarization Phase

φr Resting Phase

xvii

τap Action Potential Time Constant

τm Membrane Time Constant

τNa Sodium Time Constant

τK Potassium Time Constant

1

Chapter 1

Introduction

1.1 Background

In experiments in clinical physiological research, a common way is to build the cell

model to discuss the pathogenicity mechanism, and next study the cause and treatment of

the diseases. As an initial step, understanding the typical electrophysiology properties of

a live neuron cell is important for completely establishing a neuron cell model (Fig. 2.4).

Subsequently, the recording technique, e.g. patch clamp, is used to record cell electrical

properties. The designed emulator is based on the mechanism of MP of a neuron cell and

can be tested by the patch clamp method. The electrical properties can be measured from

this neuron emulator through the voltage or current clamp experiment setup.

In 1946, Graham and Gerard first developed the glass micro-electrode technique

which was used to penetrate into a frog muscle fiber for measuring membrane potentials

[1]. In 1949, Ling and Gerard used the same technique but tinier electrode tip to get

precise values of resting membrane potential from a Frog Sartorius Muscle [2]. In 1952,

papers were published by A.L. Hodgkin and A.F. Huxley who advocated that the

neuronal AP current originates from the concentration variation of the sodium and

potassium ions between the cell membrane by the use of voltage clamp technique [3－5].

2

They model, quantify and derive the membrane current and potential equations that meet

the experimental results [6]. The initial voltage clamp technique is developed by K. Cole

[7]. The membrane voltage is held at a constant potential via a clamp amplifier with

negative feedback loop. Membrane current in response to changes in the clamp voltage

can thus be studied. This technique originally requires insertion of two electrodes into a

neuron, one for measuring voltage and the other for injecting clamp current. The

two-electrode setting is not only inappropriate for most of tiny neurons or neurons

embedded in tissues but also likely to physically hurt the cell. The patch clamp technique

developed by E. Neher and B. Sakmann [8] does not necessitate punctuating through the

membrane with an electrode. Instead, the electrode attaches with the cell surface forming

an extremely high seal resistance which isolates a cell patch and enables recording the

currents from single ion channels using the single electrode with respect to a remote

ground reference in a lower noise environment (Fig. 1.1).

Fig. 1.1: Principle setup for patch clamp recording of membrane currents. A physical and

electric seal is formed between cell membrane and pipette.

3

Giga seal and whole cell patch-clamp technique have been improved and produced

in varying manufacturing processes, structures and materials for successfully measuring

more accurate values [11－19]. Single-electrode patch-clamp amplifier systems are

continuously being developed tested and calibrated which often require taking neuron

cell as the measurement samples [9, 10].

The artificial neuron emulator setup planned in this study is intended to be used with

the patch clamp method. The voltage and current clamp technique is well established for

studying the mechanisms of ions across the nerve cell membrane in excitation and

inhibition. This setup provides the measurement results in testing neuron emulator. The

main function of clamp amplifiers is to stimulate the neuron with limited current drive

strength. It is possible to produce an easier operated, portable and less expensive clamp

amplifier system for testing the neuron because of the high development of electronic

elements.

The neuron emulator prototype should provide both the passive properties (resting

potential) and the active properties (action potential) of a live neuron. Replacing the live

cell with this emulator enables straight-forward setups with well specified and

reproducible results. A similar project resulted in a neuron emulator for two-electrode

settings [20], the present emulator features the clamp currents used to generate an AP

4

delivered by a pre-charged capacitor [21]. The available charge is thus limited, yielding a

more realistic condition for single-electrode testing. This result is firstly confirmed by the

custom-made voltage and current clamp amplifiers. The same measurement results will

be verified by a commercial instrument.

5

1.2 Objectives

Three stages of study are proposed to accomplish the research; firstly, the

development of a neuron emulator; secondly, clamp amplifier setup; and thirdly,

verification and comparing the performance with a commercial device.

This research is to achieve the following objectives. Firstly, it is to develop a neuron

emulator prototype which is embedded in an easily portable implementation of printed

circuit board with a simple manipulation method. The emulator designed and proposed

should provide both the passive properties (resting potential) and the active properties

(action potential) of a live neuron. Secondly, it is to perform the neuron emulator

implementation in a single electrode setting for multi-clamp amplifier. This application

should feature three switch measuring modes for general neuron emulator, adjustable

speed current clamp recorder and patch clamp recorder. Thirdly, it is to verify the neuron

emulator system compared with a widely used instrument Multi Clamp 700B [26].

6

1.3 Thesis Chapter Overview

There are five chapters in this thesis. In Chapter 1, an introduction is provided.

Chapter 2 describes the background of the neuron model design which involves

membrane potential (2.1) and the Hodgkin-Huxley model (2.2). Following, the voltage

clamp (2.3) and patch clamp (2.4) techniques are introduced.

Next, from chapter 3 to chapter 5, the design and implementation of the neuron

emulator, various measurement setups, and the simulated and measured results are

performed. The details of the designed neuron emulator and a headstage circuit for patch

clamp setting are given in chapter 3 to give an introduction (3.1), and further to explain

the specification choices (3.2), the ideal circuit simulates the cell model with AP

generation (3.2.1), and this result is deducing a simplified model for the neuron cell (3.2.2)

and the simplified AP generator (3.2.3). The operating theory, formula derivation,

simulation result and parametric tables for the circuit models of a neuron emulator and a

headstage circuit are provided in Section (3.2.3) to (3.4.2) and Appendix A. For testing

the emulator, the designed headstage amplifier circuit (3.3) is used in current clamp mode

(3.3.1) and voltage clamp mode (3.3.2) respectively. The commercial device, CV-7B

Headstage, is also used to test the neuron emulator in current clamp mode (3.4.1) or

voltage clamp mode (3.4.2).

In chapter 4, a hardware implementation of the emulator and headstage are stated.

7

The choice of components (4.1) is included the microprocessor programming (4.1.1), AP

generator (4.1.2), current and voltage clamp amplifiers (4.1.3) and (4.1.4) are illustrated

in this section. The final PCB product is described in (4.2). Then, the results of the

measurement from the experiments are shown in (4.3) and (4.4). The results are

compared in (4.5)

In chapter 5, the conclusions and future work is stated.

8

Chapter 2

Background for Neuron Model Design

2.1 Membrane Potential (MP)

MP is the electrical potential difference between the interior and the exterior of a

biological cell. The voltage variation mostly alters from the ions interacting among the

membrane and the proceedings of trans-membrane proteins. The neuron cells are

surrounded by the plasma membrane, which is primarily composed of a semi permeable

lipid bi-layer with various types of proteins embedded working as an insulator and a

diffusion barrier to the movement of ions. Fig. 2.1 illustrates the ions’ diffusion and

transportation activities. Ions are actively passed through the neuron cell membranes

(also called plasma membrane or plasma lemma) by ion transporter/pump/carrier proteins

which create ion concentration gradients across the membrane. Ion channel proteins

passively diffuse ions to move across the membrane from high to low concentration [24].

Fig. 2.1: Diffusion and transportation behavior of ion transporters and ion channels [24]

9

The specific dynamic electrochemical phenomena, action potentials (APs) are

primarily generated by voltage-gated channels of potassium and sodium in the excitable

cells. The action of a neuron emitting an AP is shown in Fig. 2.2. The temporal sequence

of APs is called “spike train” (Fig. 2.3). The resting potential (RP) is the MP of quiescent

cells.

In Fig. 2.2, the changes in the cellular ion permeability are shown. AP is the result of

sodium and potassium current flows. The currents which flow in and out of the opened

channels, is related to the permeability and ions concentration. The sodium conductance

rises rapidly to a peak and then exponentially decays until the ions concentration is

balanced. The potassium conductance rises more slowly and is maintained at a lower

peak level for longer periods of time. The AP of neuron axon hillock displays the typical

values in Table 2.1 [6].

Cell type

RP

(mV)

AP increase

(mV)

AP duration

(ms)

Threshold

potential (mV)

Neuron axon hillock −70 ～ −90 110 0.75 -55

Table 2.1: AP of neuron axon hillock

10

Fig. 2.2: Ions permeability changes and AP stages in a neuron [25, 27-30]

APs are recorded in different shapes from different type of cells [24, 26], however,

the shape of the AP is representative thus the amplitude and time course for all

APs rapidly rise and fall in a short-lasting event, following a consistent trajectory in a

given cell. Fig. 2.2 marks the stages of AP signal generation process described as below

[25, 27-30].

Static RP：

Almost all of the ion channels are closed thus the MP nears the RP level which

constantly maintains from -70 to -90 mV.

11

Stimulus critical threshold potential：

Few sodium channels are triggered to open by electrical signals. Ion currents of

sodium flows into the cell that cause MP increased to a certain level. The typical

threshold voltage is usually 15 mV higher than the RP value [30].

Depolarization (Rising phase)：

As the MP climbs above a critical threshold potential around -60 mV, a rapid

increase in permeability which allows more sodium ions moves into the cell that evokes

an AP. The inward of sodium ions reverses the MP polarity leading the cell positive inter

and negative outer.

Spike (Overshoot, Peak phase)：

As soon as the MP jumps to the spike point +40 mV, the sodium channels are shut

down to stop ion transfer. The MP induces potassium channels open.

Repolarization (Falling phase)：

Potassium ions leave from the intercellular by opened potassium channels. The

outward movements of potassium ions make the MP decrease steeply down to RP value

thus the potassium channels are closed.

Hyperpolarization (Undershoot, Refractory period)：

12

The MP slightly declines below the RP that is corrected by the sodium-potassium

pump, which restores the ions concentration equilibrium the inside and outside of the

membrane in non-excitable cell at resting state.

Fig. 2.3 shows a periodic firing picture, a square depolarizing current injected into

neuron cell to stimulate the firing APs at a relatively steady frequency. The firing

frequency depends on the level of depolarization. Many types of neurons emit at rates of

10~100 per second. Some types are much quieter for minutes or longer [24].

Fig. 2.3: The dependence of AP firing frequency on the level of depolarization [24]

2.2 Hodgkin-Huxley Model

In 1952, Alan Hodgkin and Andrew Huxley started a series of experiments to

elucidate the ions current flow through an axonal membrane by choosing the giant squid

axon as a model system for their experiments [3-5]. These results lead to the formulation

of the Hodgkin-Huxley model using a voltage clamp technique [6].

13

In the Hodgkin-Huxley quantitative model (H-H Model), the AP of a cell membrane

can be represented as an electrical circuit as shown in Fig. 2.4 where membrane current

(Im) through the cell membrane can be divided into four currents: potassium current (IK+),

sodium current (INa+), chlorine current (ICl

-), and a small leakage current (ILeak) caused by

other ions. These currents are modeled by the voltage sources (EK+, ENa

+, ECl

- and ELeak)

connecting with conductances (GK+, GNa

+, GCl

- and GLeak) respectively. As acquired the

energy (ATP), ion pump actively makes ions flow through the membrane capacitance

(Cm) shown in parallel with each component. This model could mainly represents the

changed ion permeability due to ion flows and cause the change of MP (Vm) but not

represents the neuron properties of the firing threshold, oscillation and transmission in

whole cell recording.

Fig. 2.4: Membrane equivalent electrical circuit model

14

2.3 Voltage Clamp Technique

Fig. 2.5 provides the measurement picture for APs of neuron. The voltage clamp

technique was invented by Kenneth Cole in 1940s. This device is named by its function

which independently controls or clamps the MP at any desired level and measures the

amount of ionic current flowing through opened ion channels in cells simultaneously. A

negative feedback Op-Amp is implemented for measuring the injected current and

sustains the cell potential by applying a command voltage with two respective electrodes.

The injected current is passing across the membrane thus the experiment can indicate how

MP influences the ionic current flowing through the neuronal membrane and the currents

records of ion channels prove their involvement in AP conduction [6, 24].

Fig. 2.5: Voltage clamp technique for studying membrane properties

Another technique, current clamp is injecting a constant positive or negative current

into a neuronal cell and observing the MP behavior. This demonstrates how ionic current

affects the MP in a cell.

15

2.4 Patch Clamp Technique

A laboratory technique, patch clamp, is a refinement of the voltage-clamp used

in electrophysiology study in 1970s. This recording uses a glass micropipette as

an electrode, equipped with a very small open tip to seal a tiny surface or patch of a

neuronal membrane so that the mild suction of membrane assists to form a ‘gigaohm’ seal

between the glass pipette and the membrane. This high resistance seal not only provides

mechanical stability to the recording but also electronically isolates the currents measured

across the membrane patch [8, 28].

The four recording methods for patch-clamp are as shown in Fig. 2.6. The

micropipette tip is pressed against a cell membrane. Cell-attached: As the pipette closely

touches to the cell membrane surface, mild suction is applied to make a tight seal between

the pipette and the membrane. Whole-cell: By shortly applying strong suction, the

membrane is disrupted then cytoplasm is continuous with pipette interior. Inside-out:

After the cell-attached recording, the pipette is retracted, the patch is separated from the

rest of the membrane, the patch and surface of membrane are both exposed to the air.

Outside-out: After the whole-cell recording, the glass pipette is pulled away resulting in

two disrupted pieces of membrane that reconnect to form a vesicular structure facing to

pipette solution [24]. According to the whole-cell recording method, the neuron emulator

is patched by an electrode resistor for measuring the variation of MP.

16

Fig. 2.6: Configurations in patch clamp measurements of ionic currents

17

Chapter 3

Circuit Design

3.1 Introduction

In this chapter, the operating principle, formula derivation, design processes are

described. The AP generator is designed first, and then the headstage amplifiers are added.

Finally, a model for the CV-7B Headstage is implemented for comparison.

3.2 Neuron Emulator and Headstage Circuit Specification

Fig. 3.1 shows the block diagram of a neuron emulator and headstage. Rest potential

extractor draws out the baseline of membrane potential Vrest from AP signal Vclamp

(produced by AP generator) as the reference voltages (of controlled frequency) for VCO

and Threshold Comparator (allowing the AP signal to pass in the threshold range called

membrane voltage Vm). CV-7B headstage or the designed headstage injects a clamping

current Iclamp through the single electrode resistor Re to the neuron cell in current or

voltage clamp mode (C_C or V_C).

Fig. 3.1: The block diagram of a Neuron Emulator and Headstage Circuit

18

According to the specification parameter from Table 3.1, a neuron emulator and a

headstage circuit for patch clamp settings are designed for testing the whole cell

recording instrument. The AP model is designed as a kind of neuron with AP firing at the

time constant of AP τap (5 ms). The resistance value of AP, Rap, is much smaller than the

membrane resistor Rm. The membrane model is designed for a much smaller time

constant τm avoiding the effect on the AP signal. The value of membrane capacitance Cm

is according to the size of a neuron cell [6]. In the resting state, the neuron cell keeps the

RP Vrest at -90 mV. The headstage injects nano-ampere current Iclamp passing though

electrode resistor Re to stimulate the neuron cell potential achieving the threshold range

Vth approximately set to the typical value from -60 mV to -30 mV [22]. In this moment,

the AP firing speed fap (1~10 Hz) is following to the changed level of Vrest [24, 31-33], the

MP rapidly jumps up 110 mV [6] (to the spike potential Vspike +20 mV) [6].

Membrane

model

AP model

Threshold

range

Voltage

sources

Electrode Headstage

Rm Cm τm Rap Cap τap Vth fap Vspike Vrest Re Iclamp

5

MΩ

10

pF

0.05

ms

5

KΩ

1

μF

5

ms

-60~-30

mV

1~10

Hz

20

mV

-90

mV

22

MΩ

6~12

nA

Table 3.1: A Neuron Emulator and Headstage Circuit for Patch Clamp Setups

Specification

19

3.2.1 Cell Model with AP Generation

The AP signal is composed from the current of potassium and sodium ions [6]. The

circuit in Fig. 3.2 individually emulates the potassium potential VK and sodium potential

VNa which are summed up with RP Vrest by an adder Op-Amp to generate AP signal Vap.

The circuit parameters, signal shapes, and the equivalent cell model are based on [6] and

extended from the H-H Model as shown in Fig. 2.5. Compare with H-H Model, this

model designs in a realistic circuit for changed resistance instead of the conductance.

Fig. 3.2: Circuit schematic of potassium and sodium currents contributed to AP

20

In the following description the ion permeability is bigger in the depolarization

phase φde (smaller time constant) than in the repolarization phase φre (larger time

constant). The time constants τNa and τK are individually varied with the serial or parallel

connection of resistors RNa and RK which also means that the ion permeability changes

during every phase. Vrest is the initial or final value in each state respectively. The

following equations describe the transient behavior of the resulting voltages VNa and VK of

Fig. 3.2.

φde： Na

t

restpNarestNa eVVVV

)(

(3.1a)

NaNaNaNaNaNa CRRCR )//( 21 (3.1b)

φre： Na

t

pNarestpNaNa eVVVV

)( (3.2a)

NaNaNaNaNaNa CRRCR )( 21 (3.2b)

φde： K

t

restpKrestK eVVVV

)( (3.3a)

KKKKKK CRRCR )//( 21 (3.3b)

φre： K

t

pKrestpKK eVVVV

)( (3.4a)

KKKKKK CRRCR )( 21 (3.4b)

A summing circuit is realized by letting 4321 RRRR . After summation,

voltage Vap results:

)()1)(()1)((1

2

1

2

43

4

1

2

43

4

R

RV

R

R

RR

RV

R

R

RR

RVV KrestNaap

KNarest VVV (3.5)

21

3.2.2 Simplified Model for the Neuron Cell

Fig 3.3 is an equivalent circuit referred from H-H Model where the linear

components are combined into the membrane capacitance Cm and membrane resistor Rm.

The RP Vrest, spike voltage Vspike, AP capacitance Cap and AP resistor Rap are simplified

from the simulation result in Section 3.2.1. The clamp amplifier would connect to the

nodes of the equivalent model labeled external access and axoplasm as in Fig. 2.5.

Fig. 3.3: Neuron cell equivalent model

22

3.2.3 Simplified AP Generator

Fig. 3.4 displays the AP generator circuit in resting state and AP state with a single

electrode resistor Re (which is usually as high as tens of mega ohms) based on the circuit

in Fig. 3.2 and circuit model in Fig 3.3. The circuit presents the characteristics of AP and

RP controlled by the two inverse clocks, φr and φap. An external stimulation is achieved

by adjusting the variable resistor of clamp amplifiers to reach a certain MP value by

injecting a constant current Iclamp. The observation points, Vclamp and Ve, are measured

from the buffer for eliminating loading effects.

During the resting state, the switches φr are closed, and φap are opened. In Fig. 3.4,

the equivalent circuit consists of the parallel connection of Rm and Cm, in series with a

voltage source Vrest, thus Vclamp = Vrest + Iclamp Rm (3.6a). The capacitor, Cap, is pre-charged

with a voltagerestspike VV .

In the beginning, the membrane model (Rm and Cm) is connected with the AP model

(Rap and Cap) serially. An AP is initiated by closing switches φap and opening all other

switches φr. The MP of Vclamp changes immediately by the voltage previously stored on

capacitor Cap which yields a climbed voltagerestspike VV . The AP capacitor Cap

discharges exponentially through its parallel resistor Rap with a time constant τap. The

voltage is changed by the formula (3.6b).

23

φr： mclamprestclamp RIVV (3.6a)

φap： km

t

restspikekmclamprestclamp RReVVRRIVV ap

)()(

ap

t

restspikemclamprest eVVRIV

)( (3.6b)

AP Generator Circuit At Resting State At AP State

Fig. 3.4: AP Generator circuit in two states

Membrane model AP model Voltage sources Electrode

Rm Cm τm Rap Cap τap Vspike Vrest Re

5 MΩ 10 pF 0.05 ms 5 KΩ 1 μF 5 ms 20 mV -90 mV 22 MΩ

Table 3.2: The parameters of AP generator circuit

24

3.3 Headstage Amplifiers

Fig. 3.5 illustrates that the voltage clamp mode V_C and current clamp mode C_C

are using the clamp amplifiers in the headstage. The designs in the following sections

implement the voltage-controlled AP triggering and associated threshold comparison

using equivalent circuit models. In the target implementation these circuit blocks are

replaced by a microcontroller. A description of the equivalent circuits used is given in

Appendix A.

Fig. 3.5: Headstage consisting of current and voltage clamp amplifiers.

25

3.3.1 Neuron Emulator in C_C

Fig. 3.6: Neuron Emulator circuit for current clamp experiment. Shaded areas will be

implemented on a microcontroller (see Appendix A)

The current-clamp experiment is an external stimulation at a constant current level.

From Fig. 3.6, the clamp amplifier is operated as a tiny current source Iclamp with very

high output resistance Re. Iclamp (3.10) is acquired from a bigger current source Is passing

through a current amplifier with gain of

if

IR

RA

which determines the membrane

voltage Vclamp (3.11).

m

restclamp

e

clampe

clampR

VV

R

VVI

(3.10)

26

mclamprestclamp RIVV (3.11)

Adjusting Iclamp allows controlling the voltage level of Vclamp to the threshold range.

Firing an AP increases the voltage to a maximum of Vspike + Iclamp × Rm as described from

where it settles exponentially (3.6b).

3.3.2 Neuron Emulator in V_C

Fig. 3.7: Neuron Emulator for voltage clamp experiment. Shaded areas will be

implemented on a microcontroller (see Appendix A)

In the voltage-clamp experiment, the output voltage Vclamp is held at a constant

potential by the clamp amplifier (m

eV

R

RA

) so that the flow of membrane current can

be observed. The charge Qclamp must be supplied by the clamp amplifier to maintain the

27

clamp-voltage during the AP cycle. It is calculated as below (where Vclamp, Vrest and Vspike

are constants, and Rap<<Rm.).

dtIdtIQQQ

t

clamp

t

apclampapT 00

dtR

VVdt

R

eVV t

m

restclampt

m

t

restspikeap

00

)(

tR

VV

R

eVV

m

restclamp

ap

m

t

restspikeap

)(

tR

VVCR

R

eVV

m

restclamp

apap

m

t

restspikeap

)(

(3.12)

The total charge QT is the sum of the constant charges Qclamp and exponentially

injected charges Qap. The right term in (3.12) is due to the constant Iclamp flowing in the

membrane resistor and the first term is due to firing of an AP. Providing a defined AP

charge is particularly important for testing clamp amplifiers that have a limited capacity

of injecting currents through the time-multiplexed single high electrode resistance Re.

In V_C (Fig. 3.7), the differential voltage between Ve and Vclamp through an adder

connecting to an integrator, thus the total voltage of Ve－Vclamp is integrated by time:

dtIIdtR

VVap

t

clamp

t

e

clampe)(

00

(3.13)

The time course of the voltage is derived as (3.14):

tItR

VVclamp

e

clampe

(3.14)

28

Subtracting (3.13) from (3.14) by a HPF, leaves the small signal t

apdtV0

:

ap

t

ap

t

clampclamp QdtIdtItI 00

(3.15)

So that for the charges Qap to be measured can be solved:

t

ap

e

t

e

apt

apap dtVR

dtR

VdtIQ

000

1 (3.16)

A high pass RC filter is used to eliminate the dc level (constant clamp current) to be

zero with a cut off frequency 0.01 Hz at the integrator output terminal.

3.4 Comparison with CV-7B Headstage

The circuit structure and function are referred from a manual of CV-7B Headstage.

This device is a computer-controlled microelectrode current-and-voltage clamp amplifier

for electrophysiology. It allows switching between low-noise patch-clamp recording and

high-speed current-clamp recording [26]. The circuit configuration of the headstage is

shown in Fig. 3.8.

29

Fig. 3.8: Schematic of the AP Generator connected to CV-7B Headstage

3.4.1 CV-7B Headstage in C_C

In C_C a separate voltage follower is used as shown in Fig. 3.8. A1 provides a very

high input resistance and unity-gain. The output is the pipette voltage, Vp. A2 is a

summing amplifier used for injecting current into the cell. The voltage across the

headstage resistor Rf is equal to Vcmd regardless of Vp. Thus the current through Rf is given

by Ie = If = Vcmd / Rf. If stray capacitances are ignored, all of this current is injected into the

cell [28].

30

3.4.2 CV-7B Headstage in V_C

In V_C, the goal is to hold the interior of an electrode at a command potential while

measuring the currents that flow down the electrode. A resistive feedback I-V converter

achieves this by producing a voltage output that is proportional to the current input, also

shown in Fig. 3.8.

The behavior of this circuit depends on the circuit labeled PROBE in Fig. 3.8:

• High amplifier input resistance. Therefore, the electrode current (Ie) flowing out of

Re must equal the feedback current (If) flowing through the feedback resistor Rf.

• The voltage at the non-inverting terminal is the command voltage Vp, the voltage at

its inverting terminal follows and is also Vp. The voltage across Rf must therefore

be Vp – Vo = If ·Rf.

Therefore, the current is given by Ie = If = (Vp – Vo) / Rf. In practice Rf is a very large

resistor (GΩ) so this circuit can measure very tiny currents (pA). The differential

amplifier in the BOOST CIRCUIT provides Ie. Subsequent amplifiers are used to scale

the gain and remove voltage offsets [26].

31

Chapter 4

Simulated Results

4.1 Introduction

The simulation results of designed circuit in Ch3 are described in this chapter. The

results are obtained with the Cadence Spectre circuit simulator and ideal element models.

The AP generator is simulated first, and then the headstage amplifiers are added. Finally,

a model for the CV-7B Headstage is implemented for comparison.

4.1.1 Cell Model with AP Generation

Fig. 4.1 shows the simulation result according to the designed circuit schematic Fig.

3.1 VNa is seen to change faster than VK. The AP repeats every 3 ms. Table 4.1 displays the

parameters in agreement with the simulation result and paper [6].

Fig. 4.1: Simulated Results of Potassium and Sodium Ions contributed to AP

32

Switch phase Time constant Voltage sources

φde φre τNa τK

0.15 ms

VpK VpNa Vrest

High Low 0.05 ms

32 mV 72 mV 0 V

Low High 0.25 ms 0.45 ms

Table 4.1: The circuit parameters of ions’ currents contributed to AP

4.1.2 Simplified AP Generator

According to the designed circuit schematic Fig. 3.4, Fig. 4.2 (a) and (b) performs

the AP simulation result controlled by switches φap and φr as current Iclamp = 0 and 8 nA in

every 200 ms. Table 4.2 displays the circuit parameters corresponding to the simulation

result and formula (3.6a) and (3.6b).

Fig. 4.2 (a) and (b) : AP simulation result with Iclamp = 0 nA and 8 nA

33

4.2 Headstage Amplifiers

4.2.1 Neuron Emulator in C_C

According to the designed circuit schematic Fig. 3.6, the simulation results of

current-clamp are shown the simulation result from observed points Ve and Vclamp of AP

generator circuit and the flat resting voltage Vrest from the extractor with current clamp

amplifier in Fig. 4.3 (a) and (b). A current source delivers the current Iclamp to set the MP

in-between APs to around -39.8 mV in Fig. 4.3 (a) results shown in Table 4.2 (a). The

current is found to be 10 nA in accordance with (3.10) and (3.11). The AP has peak

amplitude of 110 mV and decays with a 5 ms time-constant as expected.

Fig. 4.3 (a): Simulated Result of AP Generator in C_C

34

Condition Iclamp = 10 nA, fap = 6.25 Hz, τap = 5 ms

Probe point Vclamp Ve

Vpp

Vm~VM

110 mV

-40~70 mV

110 mV

180~290 mV

Table 4.2 (a): The results of AP Generator simulation in C_C

The parametric analysis results of MP for the neuron emulator in C_C are shown in

Fig. 4.3 (b) and Table 4.2 (b). The results are in accordance with (3.10) and (3.11).

By comparing Fig. 4.3 (a) to (b), it is shown that, given controlled fixed time period

and clamp voltage, a clearer version of AP is found, as demonstrated in Fig. 4.3 (a). As

shown in Fig. 4.3 (b), while Vclamp is controlled by Iclamp = 6 nA and 12 nA, AP firing rate

changes according to Vclamp by VCO. As the clamp potential is in the threshold range,

the membrane potential Vm chooses to output the right AP by Threshold Comparator.

Fig. 4.3 (b): Parametric analysis simulation result for emulator circuit in C_C

35

Condition Vth = -60 ~ -30 mV → Iclamp = 6 ~12 nA, τap = 5 ms

Iclamp 5 nA 6 nA 12 nA 13 nA

Vclamp

-65 mV

-60 mV -30 mV

-25 mV Vrest

Vap / Vm~VM -60~50 mV -30~80 mV

Vpp 0 V 110mV 0 V

fap 0 Hz 1 Hz 10 Hz 0 Hz

Table 4.2 (b): The results of Neuron Emulator circuit simulation in C_C

4.2.2 Neuron Emulator in V_C

According to the designed circuit schematic Fig. 3.7, Fig. 4.4 (a) and (b) show the

simulation result of voltage-clamp setting in which voltage Vclamp was held constant at -40

mV. For clarity, Fig. 4.4 (a) shows only the simulated result of AP generator in V_C

excluding the constant clamping current. The charge is produced by the AP firing and the

clamping voltage source (3.12). APs were initiated at intervals of 150 ms. Each AP

requires the source to deliver approximately 110 pC. The parameters listed in Table 4.3 (a)

are in accordance with the first term in (3.12).

36

Fig. 4.4 (a): Simulated result of AP Generator in V_C

Iclamp = 10 nA, fap = 6.67 Hz, τap = 5 ms

Qap T

apdtV0

110 pC 2.42 mV˙s

Table 4.3 (a): The spike parameter table of AP Generator simulation in V_C

Fig. 4.4 (b) shows the parametric analysis result of neuron emulator circuit in V_C.

This simulation is set for three values of Vclmap (-65 mV, -60 mV and -30 mV) which

shows the same amount of charge (110 pC) at different AP train speeds as in Table 4.3 (b).

The clamping voltage -65 mV is out of the threshold range thus no charge is delivered.

37

Fig. 4.4 (b): Simulated result of Neuron Emulator circuit in V_C

Condition τap = 5 ms

Vrest / Vclamp -65 mV -60 mV -30 mV

T

apdtV0

0 mV˙s 2.42 mV˙s

Qap 0 pC 110 pC

Iclamp 5 nA 6 nA 12 nA

fap 0 Hz 1 Hz 10 Hz

Table 4.3 (b): The spike parameter table of Neuron Emulator circuit simulation in V_C

38

4.3 Comparison with CV-7B Headstage

4.3.1 CV-7B Headstage in C_C

According to the circuit schematic diagram Fig. 3.8, Fig. 4.5 shows the simulation

results of the AP generator in C_C, and Table 4.4 shows the parameters agree with the

expected MP and AP values.

Fig. 4.5: AP Generator for CV-7B Headstage simulation in C_C

Condition τap = 5 ms, T = 200 ms

Iclamp = If 1 nA 6 nA 12 nA

Vcomd 50 mV 300 mV 600 mV

Vp = Ve (Vm~VM) -65~45 mV 70~180 mV 235~345 mV

Vclamp -85~25 mV -60~50 mV -30~80 mV

Vpp 110 mV

Table 4.4: The parameter table of AP Generator for CV-7B Headstage in C_C

39

4.3.2 CV-7B Headstage in V_C

According to the circuit schematic diagram Fig. 3.8, Fig. 4.6 and Table 4.5 show the

simulation result in V_C. As the clamp voltage Vclamp is hold at -85 mV, the injected

current Iclamp flows from the headstage is 1.1nA, this current is transformed by the

electrode resistance thus cause the electrode voltage Vp =Ve is about -60 mV. The spike

of AP is also transformed by the electrode resistor from 110 mV to 5 nA. The AP firing

rate is set at 200ms.

Fig. 4.6: AP Generator for CV-7B Headstage simulation in V_C

Condition T=200 ms, τap = 5 ms, Vp = -60 mV, Iclamp = 1.1 nA

Ve = Vp -60 mV

Vrest = Vclamp Vpp = 110 mV, spike:-85~25 mV

Iclamp Ipp = 5 nA, 1.1~-3.9 nA

Table 4.5: The parameter table of AP Generator for CV-7B Headstage in V_C

40

Chapter 5

Hardware Implementation

5.1 Choice of Components

The prototype of neuron emulator and a headstage circuit on a printed circuit board

(PCB) consider the user friendliness and functionality. In this chapter, the ideal

components in the simulation environment are replaced with real electronic components,

comparing Fig. 5.1 to the block diagram in Fig. 3.1. The microprocessor chip realizes the

functions of threshold comparator, VCO and RP extractor. The details of the components

implementation are shown in Fig. 5.2 including the circuit parameters, specification and

structure.

Fig. 5.1: The block diagram implementation of the neuron emulator and headstage circuit

41

Fig. 5.2: Detailed schematic of the neuron emulator and headstage circuit

A 3.3 V voltage output with high drive strength is provided by the microprocessor

(PIC18F4550, Microchip Technology, Chandler, AZ) as a convenient GND reference in

this implementation. As shown in Fig. 5.2, the circuit is powered from a 9 V battery (VDD)

supplied directly to a buffer chip and clamp amplifiers for a maximum voltage handling

range. The buffers are realized by using Op-Amp (TL082) with high input impedance,

low noise and offset voltage drift. The clamp amplifiers are realized by Op-Amp

(LF355N) with high input impedance and offset nulling trimmer Roff, 25 KΩ.

An adjustable voltage regulator (LM317) lowers the battery voltage to a constant Vdd

3.5 V for powering the microcontroller and an analog-switches chip (CD4016BE). The

voltage sources Vspike +20 mV and Vrest -90 mV are referred to a ground reference GND

derived using resistive dividers from Vdd to VSS (Fig. 5.2). The reference voltages of the

ADC in the microprocessor, Vref+ and Vref-, are derived individually as 3.35 V and 1.55 V

42

from a resistive divider with a voltage difference ≦1.8 V according to the

microcontroller datasheet for better sampling resolution at VDD below 3 V.

5.1.1 Microprocessor Programming

The firing rate of APs, fap, is controlled by the switch phases φr and φap which are

clocked via two digital output lines whose state is set by the microcontroller. The

generated phases are complementary and non-overlapping clock signal. The controller

has an integrated 10-bit ADC. The ADC is used to detect the RP value from Vclamp

through a voltage follower amplifier. A real-time control program is developed in

assembly language. It implements a firing threshold ranging from VthL 3.27 V to VthH 3.3

V (referred to VSS) and adjustable firing frequency fap 1~10 Hz (see Section 2.2.5). To

mimic the behavior of a typical neuron, the firing rate is set to increase as the

depolarization of Vrest increases during the AP period [24, 31-33]. The program code is

shown in Appendix B.

The flow diagram of the control program is shown in Fig. 5.3 (a), the time-sequence

diagram of AP v.s. clock phase is shown in Fig. 5.3 (b). In the main program loop, the

ADC is read and a proportional timing value T_value is calculated, which determines

the AP rate. The actual AP phase generation is clocked by using a timer interrupt,

which causes the processor to jump from the main program loop to the interrupt routine

every 5 ms. Within the interrupt cycle the value T_value is decremented and when it

43

reached zero the phases φap and φr are inverted, thus producing signal edges. Variable

T_value is then loaded again with its starting value and the algorithm is executed a second

time (counted by variable Cnt_P), again to invert the phase signal. Thus, well-defined

switch phases are generated. After a full cycle has been completed, a delay of 20 ms

is introduced before the ADC is read again and a new T_value is calculated. The delay

ensures that the ADC reads the MP only after the AP spike has decayed, so that it is

indeed the resting voltage Vrest which is determined.

Fig. 5.3 (a): Time-sequence diagram of AP v.s. clock phase

44

Fig. 5.3 (b): Flow diagram of the microprocessor program code to generate rate

responsive APs

45

5.1.2 AP Generator

The shifting phases φr and φap control an analog-switches chip to transmit and

multiplex the MP signal.

During resting phase φr, the AP model is parallel with the membrane model shown

in Fig 4.4. The Cap is charged with Vspike－Vrest = (3.35－3.24) V = 110 mV. The RP of

3.24 V is measured by output Vclamp.

In the AP phase φap, the AP model is in series with the membrane model shown in

Fig 4.4. The initial Vclamp is immediately jumping from 3.24 V to 3.35 V by the

capacitor stored charges then the capacitor Cap is exponentially discharged with a time

constant τap 5 ms as in equation (3.6). The time constant of AP is set to be 5 ms, thus the

AP width is expected to be about 25 ms (5x decay time).

Fig. 5.4: AP Generator circuit of RP phase state (left) and AP phase state (right)

46

5.1.3 Current Clamp Amplifier

In Fig. 5.2, the current clamp amplifier is capable to inject around nano-ampere

current Iclamp into the cell. The current Iclamp is acquired from an adjustable current source

(LM334) providing micro-ampere current Is flowing through a current amplifier

(LF355N) with current attenuation (KK

AI1

1

200

200

A/A). The current Is is adjusted by

a single-turn variable resistor RI. The MP is shown from Vclamp through a buffer chip.

5.1.4 Voltage Clamp Amplifier

In Fig. 5.2, the voltage clamp amplifier ( 4.45

22

M

MAV

V/V) provides a

command voltage Vclamp with a negative feedback loop realized by an Op-Amp (LF355).

The command voltage is adjusted by a single-turn potentiometer Rv for setting a constant

Vclamp. The probe measures an inverse and amplified AP shown from Ve through a buffer

chip.

5.2 Printed Circuit Board Operation

An emulator prototype with the clamp amplifiers is shown in a photograph of the

implementation in Fig. 5.5. It is built by using a custom-made PCB sized 15 x 10 2cm . In

the block diagram of the prototype measurement setup (Fig. 5.6), the prototype has three

switching modes (current clamp mode, voltage clamp mode, neuron emulator mode) set

as given by Table 3.10.

47

Fig. 5.5: Photograph of a prototype implementation on a custom-made PCB.

Fig. 5.6: Block diagram of the prototype testing setup

48

The prototype is measured in the shielded box for eliminating the interference. The

experiment setup is described as below:

Mode/Switch C_C V_C

Current clamp mode 1 0

Voltage clamp mode 0 1

Neuron emulator mode 0 0

Table 5.1: The truth table of three switches mode in the prototype

A. Current clamp mode (C_C)

In the current clamp mode, the switches V_C is off and C_C is on. The neuron

emulator is connected with the current clamp amplifier from the designed headstage.

Before the measurement, using the multimeter to check the input Op-Amp LF355

connects with a trimmer to null the offset voltage between Ve and Vclamp.

B. Voltage clamp mode (V_C)

In the voltage clamp mode, the switches V_C is on and C_C is off. The neuron

emulator is connected with the voltage clamp amplifier from the designed headstage

circuit. Before the measurement, use the multimeter to check the input of Op-Amp LF355

and use a trimmer to null the offset voltage between Ve and Vclamp.

Implementation of the designed clamp amplifiers, the RP level is adjusted by two

single-turn potentiometers Rv and RI respectively controlling the voltage and current

49

clamp values in C_C and V_C. The probes are connected to the output of clock phases φr

and φap, Ve and Vclamp for showing the waveform on the oscilloscope. The multimeter

could probe to the Vclamp for observing the RP value. Another multimeter measures the

voltage difference of Re between Ve and Vclamp which is divided by the resistance value to

obtain Iclamp.

C. Neuron emulator mode (N_E)

In the neuron emulator mode, the switches V_C is off and C_C is off. The neuron

emulator is connected with the CV-7B Headstdage of Multiclamp 700B.

5.3 Experimental Results

Measured results were obtained from the prototype board (Fig. 5.5). The current

clamp experiment was conducted first (C_C), followed by the voltage clamp (V_C). The

commercial device, MultiClamp 700B, is used for testing neuron emulator in current and

voltage clamp experiment. The CV-7B Headstage is connected with the emulator in N_E.

5.3.1 Results of Current Clamp Mode

Fig. 5.7 shows the testing results of AP generator circuit, the switching signal φap at

5 Hz (top) from the microprocessor was able to drive the analog switch chip, producing

APs (Vpp = 90 mV) (bottom) with Iclamp = 0 nA in agreement with the simulation result in

Fig. 4.2 (a) and Table 4.2 (a).

50

Fig. 5.7: The control signal φap from the microprocessor (top) and the experimental

recording of the APs from the prototype (bottom)

Fig. 5.8 shows the results of the neuron emulator for the designed headstage circuit

in C_C experiment. It is a plot in which several oscilloscope screenshots are lined up to

show the circuit behavior with varying clamp current. The clamp current delivered by the

amplifier and annotated on the plot was verified for each setting by measuring the voltage

drop across Re (3.10). Increasing magnitudes of depolarization of the MP reach to -63 mV

(with Iclamp = 3.8 nA) which is over the lower threshold -60 mV, are achieved by

increasing Iclamp, the firing rate of the AP increased accordingly. The upper firing

threshold is with a clamp current of 10.4 nA (resulting in -30 mV membrane voltage), it is

exceeded with a clamp current of 11.8 nA (resulting in -20 mV membrane voltage) so that

the emulator stops generating APs. The intended stop value should be clamp current

above 12 nA (Table 4.2(b)). Offset voltage is eliminated by the nulling offset trimmer

51

which makes the current value not totally as expected in simulation result Fig. 4.2 (b) and

Table 4.2(b). The largest amplitude of the AP pulses is about 102 mV, slightly smaller

than the expected 110 mV. The resolution of the oscilloscope is not enough to detect

every peak of the spike which is a very high frequency signal. As anticipated, the AP time

constant is around 5 ms.

52

Fig. 5.8: Oscilloscope screenshots to show the membrane voltage (Vclamp,

CH1), electrode voltage (Ve, CH2) and switch control signal (φap, CH3) as

the clamp current Iclamp is varied. The AP frequency increases as the RP

increases over to the firing threshold -60 mV.

53

5.3.2 Results of Voltage Clamp Mode

Fig. 5.9 shows the oscilloscope screenshot of the neuron emulator for the designed

headstage in voltage clamp mode experiment. The clamp amplifier held the membrane

voltage at approximately -68 mV. The membrane voltage is shown on channel CH2,

measured with the oscilloscope probe connected to the unity gain buffer output (Fig. 5.6).

The resting membrane voltage is in a range which triggers APs. CH1 shows the voltage

provided by the clamp amplifier Ve to maintain a constant Vclamp which is derived from a

command voltage source. The spike train is amplified by gain 4.4 V/V, the original spike

range is about 77 mV closing to the measured average range in C_C. The voltage

difference Ve －Vclamp drops across the access resistor Re (3.10). The clamp current Iclamp

which is 3.41 nA (due to the offset is nulling) delivered by the amplifier can thus be

determined from the screenshot as (CH1-CH2)/Re. Also shown is the time integral of

CH1, obtained directly by a function of the oscilloscope. This integral is thus

(3.13) dtIR

VV

R

dtCHCH

tf ap

t

e

clampe

e

t

m )(

)21(

)(0

0

(plus an offset which does not affect the calculation provided here). To obtain only

the AP charge delivered by the amplifier, a line f1 is fitted to fm in a time period where no

AP is active. Since the clamp current is constant in this period, the line is described by

54

(3.14) tR

VVtf

e

clampe )(1

The difference between fm and f1 )14.3()13.3( then yields the charge delivered

by the amplifier for all APs within the chosen time period (3.15) (3.16). From the

graph, the difference over 5 APs is found as 400 pC, i.e. Every AP yields about a charge

of 80 pC which is smaller than the expected value 110 pC in Table 4.3 (a) and simulation

result in Fig. 4.4 (b). The reason could be that the measured result for peak of AP spike is

a high frequency signal affected by loading capacitance. Also shown on CH3 is the

pulsed output of phase φap with a frequency of 2.481 Hz.

Fig. 5.9: Annotated oscilloscope screenshot of the voltage clamp experiment.

55

5.4 Results of Neuron Emulator Mode for CV-7B Headstdage

5.4.1 CV-7B Headstdage in C_C

Fig. 5.10 displays several oscilloscope screenshots to show the circuit behavior with

varying clamp current measured with the CV-7B Headstage. Comparing the experimental

result (Fig. 5.10) to the simulation result (Fig. 4.5) and Table 4.4, the observed voltage

potential Vp subtracts from the pipette offset value -95.69 mV and close to the electrode

voltage Ve in simulation. The clamp current delivered by the amplifier and annotated on

the plot was verified for each setting by measuring the voltage drop across Re (Vp – pipette

offset value = Ve, eqn. 3.10). The pipette offset equals the initial RP Vrest. Increasing

magnitudes of depolarization of the Vp reach to 25.8 mV (with Iclamp = 1 nA) which is

above the lower threshold (achieved by increasing Iclamp). The firing rate of the AP

increased accordingly. The upper firing threshold where the emulator stops generating

APs is at clamp current of 12 nA (resulting in 315.8 mV electrode voltage Ve) as expected

(Table 4.4). The pipette capacitance Cp = 5 pF of the CV-7B Headstage causes the

amplitude of the AP pulses being slightly smaller than expected with only about 85 mV.

The AP time constant is as expected around 5 ms, and this result is the same as the

custom-designed headstage in C_C.

56

Fig. 5.10: Measured neuron emulator by

MultiClamp 700B from the software of

oscilloscope screenshot of the CV-7B Headstage

in the current clamp mode.

57

5.4.2 CV-7B Headstdage in V_C

Fig. 5.11 shows the screenshot of the N_E using the CV-7B Headstage in a voltage

clamp measurement. The clamp amplifier held the electrode voltage Vp at approximately

-60 mV (bottom trace). The observed current Ie shows the spike of the AP current (top).

Due to the pipette offset of -95.69 mV, the current range is from 1.8 nA to -1.8 nA (Ipp =

3.6 nA) which is less than the simulated value from 1.1 nA to -3.9 nA (Ipp = 5 nA) in Fig.

4.6 and Table 4.5. The time constant is 5 ms as expected. Firing an AP, the expected

voltage spike range is Vpp = Vspike – Vrest = 110 mV transforming to the current spike range

by Re equal to Ipp = 5 nA. The experimental current 3.6 nA multiplied by Re is 79.2 mV,

close to the expected voltage spike range 85 mV in C_C.

Fig. 5.11: Measured Neuron Emulator by MultiClamp 700B from the software of

oscilloscope screenshot of the CV-7B Headstage in the V_C.

58

5.5 Comparison

Comparing the CV-7B Headstage with the designed headstage circuit, the

measurement results are the same but with different circuit designed concepts. The

CV-7B Headstage is using a feedback resistor (Rf) to transform between voltage and

current, the designed headstage is using an electrode resistor Re. From the Table 5.2, the

designed headstag circuit has less power consumption and smaller size than Multiclamp

700B and also achieves the same functionality. However, the more functionality such as

automatic correction, switched feedback resistors and computer-controlled interference

are provided by the commercial devices, these features make this instrument is capable

of more accuracy and friendly uses for the users.

Considering the use for users, the system can operate by a 9 V battery, and clamp

current is accurately operated by turning the single-turn potentiometers which are

embedded on the isolated box. Considering the resolution of the built-in ADC, an

amplifier was used for enlarging the action potential signal detected by the

microprocessor. Compared to a similar paper [21], the emulator in this thesis provides

more suitable, lower cost and functional implementation for users. By assembly

programming the signal delay reading function in the microprocessor, the low pass filter

is removed. The design of the shifting reference voltage simplifies the supply voltage

sources as shown in the comparison Table 5.3 (a). The value of AP model is chosen much

59

smaller than membrane model (Table 5.3 (b)) so that the level of RP does not change

significantly at the firing state.

CV-7B Headstage of

Multiclamp 700B

A Neuron Emulator and Headstage Circuit

for Patch Clamp Setups

Dimensions 8.9(H)x48.3(W)x30.5(D) 4(H)x14(W)x9.5(D)

Price / Cost 14060 USD / N/A N/A / 953 TWD

Voltage

Clamp

Amplifier

Rf = 50 GΩ, 5 GΩ, 500 MΩ, 50 MΩ

Holding = ±1000 mV

Pipette offset: ±100 mV

Re = 22 MΩ

Holding = -1000 mV

Nulling offset: ±200 mV

Current

Clamp

Amplifier

Range: ±200 nA(50 MΩ Rf)

±20 nA(500 MΩ Rf)

±2 nA(5 GΩ Rf)

Pipette offset: ± 200 pA

Range:+20 nA(22 MΩ Re)

Nulling offset: ±200 mV

Power

Consumption

85-260 VAC 50-60 Hz, 30 watts 9 VDC 0.162 watts

Table 5.2: The headstage specification comparison table

60

A Neuron Emulator and Headstage Circuit

for Patch Clamp Setups

A Neuron Emulator

for Single-Electrode Settings [21]

Components Power supply voltage (V) Components Power supply voltage (V)

PIC18F4550 0～3.5 PIC18F2520 -1.5～1.5

TL082 0～9 -2.5～2.5

ADC in PIC 1.55～3.35 -0.1～1.5

CD14016BE 0～3.5 -2.5～2.5

Battery 0～9

Hedstage

LF355N 0～9

LM334 0～V+

LM317 0～9

Table 5.3 (a): The comparison table of components and voltage sources

Electrode Membrane model AP model Low-pass filter

Re Rm Cm τm Rap Cap τap Rlpf Clpf τlpf

A Neuron Emulator

for Single-Electrode

Settings [21]

22 MΩ 5 MΩ 10 pF 0.05 ms

5 MΩ 1 nF

5ms

26 KΩ 10 μF 260 ms

A Neuron Emulator and

Headstage Circuit for

Patch Clamp Setups

5 KΩ 1 μF

Table 5.3 (b): The comparison table of components values

61

Chapter 6

Conclusions and Future Work

In this study, a neuron emulator has been developed to provide the passive and

active electrical properties of a neuron as seen from a single electrode. As in a live neuron,

each AP generates a well defined charge 110 mV. It is useful for testing single-electrode

voltage or current clamp experiment in patch clamp setups. The AP firing rate from 1 Hz

to 10 Hz is dependent on the RP level in the threshold range from -60 mV to -30 mV. A

prototype implementation using a microcontroller for the rate responsive AP timing and

discrete components on a PCB is discussed. Measured results confirm the emulator

headstage circuit design included AP firing and delivered AP charges are in agreement

with the simulation results by Cadence software. For driving the system by a single

battery, a GND reference voltage, 3.3 V, is provided by a built-in voltage regulator from

the microprocessor, the battery voltage 9 V is lowered to 3.5 V by a voltage regulator chip.

The voltage sources, 3.5 V and 3.3 V, are derived from a resistive divider.

To improve the functionality, the headstage circuit is implemented for providing the

clamp current to observe the voltage and current properties of the neuron emulator.

Based on the developed single neuron emulator, continuing the development of

neural oscillator project is possible. In this thesis, the ideal simulation is built by the

Cadence software. It is possible to make the achievements of the thesis realized in a chip

62

(ASIC). The size, power consumption, functionality and the accuracy could be improved.

Eventually, multiple neuron emulators could be coupled to test if they can be used to

provide a mock setup for neuronal oscillator experiments.

63

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Anatomy & Physiology, 2011

- 1 -

Appendix

A. Equivalent circuits representing the functions provided by the microcontroller

A1. Rest Potential Extractor (RP Extractor)

Fig. A1.1. is a RP extractor circuit diagram which is also a 2nd

-order low pass filter

(2nd

-LPF). The resistors Rlpf1, Rlpf2 and capacitances Clpf1, Clpf2 of filter are set to eliminate

the AP signal from 1 Hz to 10 Hz. AP signal from terminal Vclamp of AP generator passes

through the filter, a flat dc voltage value Vrest is left. Fig. A1.2 is shown the AP signal at

3.87 Hz eliminated by the LPF and leaves the RP at -49.8 mV. The transfer function H(s)

is expressed in (A1.1):

21212221

2

2121

22

2

1)

11(

1

)()(

lpflpflpflpflpflpflpflpf

lpflpflpflpf

oo

o

CCRRs

RRRRs

CCRR

sQ

s

GsH

(A1.1)

where, G = 1, Q = 121

2121

)( lpflpflpf

lpflpflpflpf

CRR

CCRR

= 0.31,

2121

1

lpflpflpflpf

oCCRR

0.062832(s

rad)

The AC simulation result in Fig. A1.3 provides an under-damped frequency

response result with cut off frequency

2

oof 0.01 Hz and pass-band gain G = 1

V/V. As the frequency of input signal becomes higher than the of , the gain of filter is

lower than 3dB. The more fast speed signal is eliminated by the much lower filter gain.

- 2 -

Fig. A1.1: RP Extractor circuit diagram

Fig. A1.2: RP Extractor transient simulation result

Fig. A1.3: RP Extractor frequency response

- 3 -

A2. Voltage Controlled Oscillator (VCO)

Fig. A2.1 is a VCO circuit diagram. The Vrest is linearly enlarged to be a frequency

controlled voltage Vf (A2.1) relating to the oscillator frequency fap positively. The Vf is

multiplied by a conductance gm to transform as a current charging the capacitance Cf. The

controlled voltage Vctrl decides the amplitude of clock signal. The delay block is designed

for Cf to discharge completely so that the charging signal can make the NMOSFET

switch immediately turns on at a high state. Then the Cf is discharged to the initial state.

The controlled oscillator formula is expressed in (A2.2).

.constrestf VVV as 4321 RRRR (A2.1)

ctrlf

mf

apVC

gVf

(A2.2)

Shifting Amplifier VCO

Vrest Vconst. Vf gm Cf Vctrl fap

-60~-30 mV 63.3 mV 3.3~33.3 mV 0.09 μ 1Ω 100 pF 3 V 1~10 Hz

Table A2.1: The parameters of VCO circuit.

- 4 -

Fig. A2.1: Voltage Controlled Oscillator circuit diagram

Fig. A2.2 shows the simulation result of VCO. The clock signal shows the frequency

at 1 Hz, 5 Hz and 10 Hz, controlled respectively by the Vf at 3.3 mV, 18.3 mV and 33.3

mV. Vf is summed from Vrest and Vconst. which is at -60 mV, -45 mV and -30 mV. The

device parameters in Table A2.1, which respond to the simulation result in Fig. A2.2, are

in accordance with the equations (A2.1) and (A2.2).

- 5 -

Fig. A2.2: Simulated result of VCO circuit

A3. Threshold Comparator

Fig. A3.1 shows the threshold comparator circuit. The LPF outputs Vrest which is

compared with the threshold voltage range from VthH -30 mV to VthL -60 mV. If the

voltage value is in the middle of the threshold, the output of multiplexer, Vm, outputs

Vclamp. If not, Vrest is chosen to be an output signal as shown in Table A3.1. Fig. A3.2

demonstrates the simulation result at Vrest (Is) = -65 mV (5 μA), -45 mV (9 μA) and -25

mV (13 μA). -45 mV (9 μA) is the only one in the threshold voltage range as shown in the

simulation result Fig. A3.2. The Vm chooses the right output signal from Vrest or Vclamp in

these three different voltage situations following to the Table A3.1.

Fig. A3.1: Threshold Comparator circuit

- 6 -

Fig. A3.2: Simulated result of Threshold Comparator circuit

Double Comparator Input And Gate Input Multiplexer Control Input Vm

Vrest ≧ VthH 01 0 Vrest

VthL ＜ Vrest ＜ VthH 11 1 Vclamp

Vrest ≦ VthL 10 0 Vrest

Table A3.1: The truth table of Threshold Comparator circuit.

- 7 -

B. Assembly code for microcontroller

;*********************************************************

;* Adjustment Period Program for 10MHz

;*********************************************************

;*** list p = 18F4550 ;宣告程式使用的微控器

#include <P18F4550.inc> ;加入P18F4550檔

;

AD_val equ 0x20 ;設定暫存器AD_val的初值位址0x20

T_val equ 0x21 ;設定暫存器T_val的初值位址0x21

x0 equ 0x22 ;設定暫存器x0的初值位址0x22

cnt_val equ 0x24 ;設定暫存器cnt_val的初值位址0x24

cnt_p equ 0x25 ;設定暫存器cnt_p的初值位址0x25

p_temp equ 0x26 ;設定暫存器p_temp的初值位址0x26

val_20ms equ 0X27 ;設定暫存器val_20ms的初值位址0x27

cnt_d1ms equ 0x28 ;設定暫存器cnt_d1ms的初值位址0x28

cnt_d20ms equ 0x29 ;設定暫存器cnt_d20ms的初值位址0x29

val_223 equ .223 ;設定變數val_223的初值等於常數223

val_240 equ .240 ;設定變數val_240的初值等於常數240

val_2 equ .2 ;設定變數val_2的初值等於常數2

val_200 equ .200 ;設定變數val_200的初值等於常數200

tmr1_val equ .5000 ;設定變數tmr1_val的初值等於常數5000

org 0x00 ;虛擬指令org宣告程式起始位址為0x00

bra Main ;跳躍到Main程式執行

org 0x18 ;虛擬指令org宣告程式起始位址為0x18

bra int ;跳躍到int程式執行

───────────────────────────────────

Main:

call Init_IO ;呼叫函式Init_IO

call Init_AD ;呼叫函式Init_AD

call Init_tmr1 ;呼叫函式Init_TMR1

bsf RCON,IPEN ;設定RCON(重置控制暫存器)的IPEN(中斷優先順序的

;控制位元)為1(開啟)

goto AD_C ;切換程式至AD_C

;

Init_IO:

clrf TRISB ;TRISB(資料方向暫存器B)清除為0(PORTB設為輸出),

- 8 -

;運算所需資料否為Access Bank的記憶體

movlw b'01011010' ;搬移常數01011010(90)到WREG

movwf PORTB ;WREG的內容傳送到PORTB(01011010)

bsf TRISA,RA0 ;設定TRISA(資料方向暫存器A)中的RA0(Bit0)位元為

;1(PORTA設為輸入)

bsf UCON,USBEN ;開啟USB 這樣才有3.3V的電源

return ;

;

Init_AD:

movlw b'00111110' ;搬移常數00001110(14)到WREG

movwf ADCON1 ;WREG的內容傳送到ADCON1(00001110)

movlw b'10000001' ;搬移常數10000001(129)到WREG

movwf ADCON0 ;WREG的內容傳送到ADCON0(10000001)()

movlw b'10101001'

movwf ADCON2

movlw b'11000100' ;

movwf CVRCON ;

bcf PIE1,ADIE ;清除PIE1(周邊功能中斷設定暫存器)的ADIE(A/D轉

;換模組中斷功能)位元為0(關閉)

return

;

Init_tmr1:

movlw b'10000001' ;搬移常數10000001(129)到WREG

movwf T1CON ;WREG的內容傳送到T1CON(TIMER1暫存器相關的

;T1CON設定暫存器位元內容)(10000001:RD16(bit7):開

;啟TIMER1計時器16位元讀寫模式,TMR1ON(bit0):

;開啟TIMER1計時器)

movlw (.65536-tmr1_val)/.256 ;搬移常數(.65536-TMR1_val)/.256到WREG

movwf TMR1H ;WREG的內容傳送到TMR1H(計數內容的高位元組)

movlw (.65536-tmr1_val)%.256 ;搬移常數(.65536-TMR1_val)%.256到WREG

movwf TMR1L ;WREG的內容傳送到TMR1L(計數內容的低位元組)

bsf IPR1,TMR1IP ;設定IPR1(周邊功能中斷優先設定暫存器)中的

;TMR1IP(計時器溢位中斷優先順序)為1(高優先中斷)

bcf PIR1,TMR1IF ;清除PIR1(周邊功能中斷旗標狀態暫存器)的

;TMR1IF(計時器溢位中斷旗標)位元為0(未發生)

bsf PIE1,TMR1IE ;設定PIE1(周邊功能中斷設定暫存器)中的TMR1IE(計

;時器溢位中斷功能)為1(開啟)

return ;

- 9 -

;

AD_C:

bcf INTCON,GIEH ;設定INTCON(核心功能中斷控制暫存器)的GIEH(所

;有優先位元設定為1的中斷功能)為1(開啟)

bsf ADCON0,GO,0 ;設定ADCON0中的GO為0,運算所需資料否為Access

;Bank的記憶體(ADC開始轉換)

nop ;無動作

btfsc ADCON0,GO ;檢查ADCON0的GO位元為0則跳過

bra $-4 ;無條件切換程式位址至$-4

movff ADRESL,x0 ;將來源ADRESH(第一個位元組)傳送到目標ad_val

movlw val_223 ;搬移val_233的常數233到WREG

cpfsgt x0 ;當AD值大於223且小於240時跳到Clk_out

goto AD_C ;切換程式至AD_C

movlw val_240 ;搬移val_240的常數240到WREG

cpfslt x0

goto AD_C ;切換程式至AD_C

movf x0,0,0

goto seting ;切換程式至seting

; movf ADRESL,0,0 ; test ADC

; movwf LATB,0

; goto AD_C

;

seting:

movlw .2

movwf cnt_p

clrf T_val

call Period_count

bsf INTCON,GIEH

loop: tstfsz T_val

goto loop

decfsz cnt_p

goto do_some

call d_20ms

goto AD_C

;

Period_count:

; movlw .210 ; test function

; movwf x0,0

- 10 -

movlw val_200

subwf x0,0

mullw d'5'

movf PRODL,0,0 ;傳送暫存器PRODL的內容,結果儲存在WREG,運算所

;需資料否為Access Bank的記憶體

sublw d'215' ;215-WREG(WREG = 160-AD值)

movwf T_val ;WREG的內容傳送到T_val = 215-5*(AD_val-200),運算

;所需資料否為Access Bank的記憶體

movwf p_temp

return

;

do_some:

movff p_temp,T_val

goto loop

;

int:

bcf PIR1,TMR1IF ;清除PIR1的TMR1IF位元為0

movlw (.65536-tmr1_val)/.256 ;搬移(.65536-TMR1_val)/.256的常數到WREG

movwf TMR1H ;WREG的內容傳送到TMR1H(計數內容的高位元組)

movlw (.65536-tmr1_val)%.256 ;搬移(.65536-TMR1_val)%.256的常數到WREG

movwf TMR1L ;WREG的內容傳送到TMR1L(計數內容的低位元組)

decfsz T_val,f ;T_val減一,為零則跳過,結果儲存在WREG

retfie ;中斷返回,結束函式的執行(將GIE位元設定為1)

swapf PORTB,1,0 ;PORTB半位元組交換,結果儲存在指令所定義的暫存

;器,運算所需資料否為Access Bank的記憶體

retfie ;中斷返回,結束函式的執行(將GIE位元設定為1)

;

d_20ms:

movlw .20

movwf cnt_d20ms

d_20mlp:

call d_1ms

decfsz cnt_d20ms,f

goto d_20mlp

return

;

d_1ms:

movlw .147

movwf cnt_d1ms

- 11 -

d_1mlp:

call d_5us

decfsz cnt_d1ms,f

goto d_1mlp

return

;

d_5us:

call d_5lp

call d_5lp

nop

nop

d_5lp:

return

;

end

;