Memory and Programmable Logicviplab.cs.nctu.edu.tw/course/DCD2017_Spring/DCD_Lecture...Coincident Decoding A two-dimensional selection scheme Reduce the complexity of the decoding

Digital Circuit Design

Memory and Programmable Logic

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Spring, 2017

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lecture 7


Lan-Da Van DCD-07-2

Outlines

Random-Access Memory

Memory Decoding

Error Detection and Correction

Read-Only Memory

Programmable Logic Array

Programmable Array Logic

Sequential Programmable Logic Devices

Lecture 7


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Introduction

Memory

Information storage

A collection of cells stores binary information

RAM – Random-Access Memory

Read operation

Write operation

ROM – Read-Only Memory

Read operation only

A programmable logic device

Lecture 7


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Volatile

Lose stored information when power is turned off

SRAM:

Information are stored in latches

Remain valid as long as power is applied

More transistors are needed

High speed with short read/write cycle

Less memory capacity

Non-volatile

Retain its stored information

after the removal of power

ROM

EPROM, EEPROM

Flash memory

Introduction

Dynamic

Information are stored in the form of

charges on capacitors

The stored charge tends to

discharge with time and need to be

refreshed (read and write back)

Less transistors are needed

Slow speed

Larger memory capacity

Lecture 7


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Programmable Logic Device (PLD)

ROM

Programmable Logic Array (PLA)

Programmable Array Logic (PAL)

Sequential Programmable Logic Device

Sequential (simple) programmable logic device (SPLD)

Complex programmable logic device (CPLD)

Field programmable gate array (FPGA)

Introduction

Lecture 7


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Random-Access Memory (RAM)

A memory unit

stores binary information in groups of bits (words)

8 bits (a byte), 2 bytes, 4 bytes

Block diagram

Lecture 7


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Contents of 1024 16 Memory

Random-Access Memory (RAM)

Lecture 7


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Write and Read Operations

Write operation• Apply the binary address to the address lines

• Apply the data bits to the data input lines

• Activate the write input

Read operation• Apply the binary address to the address lines

• Activate the read input

Lecture 7


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Timing Waveforms

The operation of the memory unit is controlled by an

external device.

The access time

The time required to select a word and read it

The cycle time

The time required to complete a write operation

Read and write operations must be synchronized with

an external clock.

Example: CPU clock – 50 MHz and the access/cycle

time < 50 ns

Lecture 7


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Write Cycle

Lecture 7



Read Cycle

Lecture 7



Memory Cell

The storage part of the cell is modeled by an SR latch with

associated gates to form a D latch.

The cell is an electronic circuit with four to six transistors.

A 1 in the read/write input provides the read operation by forming a

path from the latch to the output terminal.

A 0 in the read/write input provides the write operation by forming a

path from the input terminal to the latch.

Lecture 7



Block Diagram of 4x4 RAM

Lecture 7



Coincident Decoding

A two-dimensional

selection scheme Reduce the complexity

of the decoding circuits

Example:

A 10-to-1024 decoder

1024 AND gates with

10 inputs per gates

Two 5-to-32 decoders

2 * (32 AND gates with

5 inputs per gates)

Lecture 7



Address Multiplexing

To reduce the

number of pins in

the IC package

Consider a 64M1

DRAM

16-bit address

lines

RAS – row

address strobe

CAS – column

address strobe

Lecture 7




Improve the reliability of a memory unit

A simple error detection scheme

A parity bit

A single bit error can be detected, but cannot be corrected.

An error-correction code

Generate multiple parity check bits

If the check bits are correct, no error has occurred.

If the check bits do not match the stored parity, they

generate a unique pattern, called a syndrome, that can be

used to identify the bit that is in error.

Lecture 7



Hamming Code

Hamming code

Can detect and correct only a single error

Multiple errors may not be detected.

k parity bits are added to an n-bit data word.

(2k –1 n + k)

The bit positions are numbered in sequence from 1 to n + k.

Those positions numbered as a power of 2 are reserved for

the parity bits.

The remaining bits are the data bits.

Lecture 7



8-bit data word 11000100

Include 4 parity bits and the 8-bit word 12 bits

2k –1 n + k, n = 8 k = 4

Bit position: 1 2 3 4 5 6 7 8 9 10 11 12

P1 P2 1 P4 1 0 0 P8 0 1 0 0

Calculate the parity bits: even parity assumption

P1 = XOR of bits (3, 5, 7, 9, 11) = 1 1 0 0 0 = 0

P2 = XOR of bits (3, 6, 7, 10, 11) = 1 0 0 1 0 = 0

P4 = XOR of bits (5, 6, 7, 12) = 1 0 0 0 = 1

P8 = XOR of bits (9, 10, 11, 12) = 0 1 0 0 = 1

Store the 12-bit composite word in memory.

Bit position: 1 2 3 4 5 6 7 8 9 10 11 12

0 0 1 1 1 0 0 1 0 1 0 0

When the 12 bits are read from the memory, check bits are calculated.

C1 = XOR of bits (1, 3, 5, 7, 9, 11)

C2 = XOR of bits (2, 3, 6, 7, 10, 11)

C4 = XOR of bits (4, 5, 6, 7, 12)

C8 = XOR of bits (8, 9, 10, 11, 12)

Hamming Code Example

Lecture 7



If no error has occurred

Bit position: 1 2 3 4 5 6 7 8 9 10 11 12

0 0 1 1 1 0 0 1 0 1 0 0

C = C8C4C2C1 = 0000

If one-bit error has occurred

error in bit 1

C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1

C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0

C4 = XOR of bits (4, 5, 6, 7, 12) = 0

C8 = XOR of bits (8, 9, 10, 11, 12) = 0

C8C4C2C1 = 0001

error in bit 5

C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1

C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0

C4 = XOR of bits (4, 5, 6, 7, 12) = 1

C8 = XOR of bits (8, 9, 10, 11, 12) = 0

C8C4C2C1 = 0101

Hamming Code Example

Lecture 7



The Hamming code can be used for data with

arbitrary length

k check bits

2k –1 n + k

Hamming Code

Lecture 7



Read-Only Memory

Store permanent binary information

2k x n ROM

k address input lines

enable input(s)

three-state outputs

Lecture 7



32 x 8 ROM 5-to-32 decoder

8 OR gates each has 32 inputs

32x8 internal programmable connections

Diagram of 32x8 ROM

Lecture 7



An example of ROM truth table (partial)

Diagram of 32x8 ROM

Lecture 7



programmable interconnections close (two lines are connected)

or open

A fuse that can be blown by applying a high voltage pulse

Diagram of 32x8 ROM

Lecture 7



Combinational Circuit Implementation

ROM: a decoder + OR gates

Sum of minterms

A Boolean function = sum of minterms

For an n-input, m-output combinational ckt

2n m ROM

Design procedure:

Determine the size of ROM

Obtain the programming truth table of the ROM

The truth table = the fuse pattern

Lecture 7



Example 7.1

3 inputs and 6 outputs

B1=0

B0=A0

8X4 ROM

Lecture 7



ROM implementation

Truth table

Example 7.1

Lecture 7



Types of ROM

Types of ROM

mask programming ROM

IC manufacturers

Is economical only if large quantities

PROM: Programmable ROM

Fuses

Universal programmer

EPROM: erasable PROM

Floating gate

Ultraviolet light erasable

EEPROM: electrically erasable PROM

Longer time is needed to write

Flash ROM

Lecture 7



Combinational PLDs

Programmable two-level logic an AND array and an OR array

Lecture 7




PLA An array of programmable AND gates

can generate any product terms of the inputs

An array of programmable OR gates

can generate the sums of the products

More flexible than ROM

Use less circuits than ROM

only the needed product terms are generated

The size of a PLA The number of inputs

The number of product terms (AND gates)

The number of outputs (OR gates)

When implementing with a PLA Reduce the number of distinct product terms

The number of terms in a product is not important

Lecture 7



PLA programming table

Specify the fuse map

PLA Example

Lecture 7



An example

F1 = AB + AC + ABC

F2 = (AC + BC)

XOR gates

can invert the outputs

PLA with three inputs, four product terms, and two outputs

PLA Example

Lecture 7



Examples 7.2 F1(A, B, C) = (0, 1, 2, 4); F2(A, B, C) = (0, 5, 6, 7)

Both the true value and the complement of the function should be

simplified to check

Example 7.2

Lecture 7



F1 = (AB + AC + BC)

F2 = AB + AC + ABC

PLA with three inputs, four product terms, and two outputs

Example 7.2

Lecture 7




PAL

Product terms cannot

be shared.

With four inputs, four

outputs, and a three-

wide AND-OR

structure

Lecture 7



PAL Example

w(A,B,C,D) = (2,12,13)

x(A,B,C,D) = (7,8,9,10,11,12,13,14)

y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15)

z(A,B,C,D) = (1,2,8,12,13)

Simplify the functions

w = ABC + ABCD

x = A + BCD

y = AB + CD + BD

z = ABC + ABCD + ACD + ABCD

= w + ACD + ABCD

Lecture 7



PAL programming table

PAL Example

Lecture 7



w = ABC + ABCD

x = A + BCD

y = AB + CD + BD

z = w + ACD + ABCD

Lecture 7



Sequential Programmable Devices

Sequential programmable device

Configuration:

PLD + flip-flops

Type:

Sequential (simple) programmable logic device (SPLD)

Complex programmable logic device (CPLD)

Field programmable gate array (FPGA)

Lecture 7



Basic Macrocell Logic

Programming features:

AND array

use or bypass the flip-flop

select clock edge polarity

preset or clear for the register

complement an output

programmable input/output

pins

Lecture 7



Complex PLD Put a lot of PLDS on a chip

Add wires between them whose connections can be

programmed

Use fuse/EEPROM technology

Complex Programmable Logic Device (CPLD)

Lecture 7



History:

Xilinx launched the world’s first commercial FPGA in 1985

with XC2000 device family.

Technology:

An FPGA is a VLSI circuit that can be programmed at the

user’s location

100-1000(s) logic blocks surrounded by programmable input

and output blocks and connected together via programmable

interconnections.

Components:

Consist of lookup tables, MUX, gates, and flip-flops.

CAD:

Require extensive computer-aided design (CAD) tools to

facilitate the synthesis procedure.

Field-Programmable Gate Arrays (FPGA)

Lecture 7



Logic blocks To implement combinational

and sequential logic

Interconnect Wires to connect inputs and

outputs to logic blocks

I/O blocks Special logic blocks at

periphery of device forexternal connections

Key questions: How to make logic blocks

programmable?

How to connect the wires?

After the chip has been fabbed

Field-Programmable Gate Arrays

Basic architecture of Xilinx Spartan and predecessor devices

Lecture 7



Configurable Logic Block (CLB)

Lecture 7



Configurable Logic Block (CLB)

Consist of

Programmable look-up table

MUX

Register

Path to control signal

Function generators

Two function generators (F and G) of the look-up table can

generate any arbitrary function of four inputs.

H of the look-up table can generate any arbitrary function of

three inputs.

The H-function block can get its inputs from the F and G

lookup tables or from external inputs.

The three function generators within a CLB can be used as

either a 16x2 dual port RAM or a 32x1 single-port RAM.

Lecture 7



Interconnection

Circuit for a programmable PIPRAM Cell Controlling a PIP Transition Gate

Lecture 7



I/O Block (IOB)

XC4000 series IOB

Lecture 7



I/O Block (IOB)

Used as input, an output, or a bidirectional port.

An IOB that is configured as an input can have direct,

latched, or registered.

An IOB that is configured as a output can have direct

or registered output.

The output buffer of an IOB has skew and slew

control.

The device have embedded logic to support the IEEE

1149.1 (JTAG) boundary scan standard.

On chip test access port (TAP) controller

I/O cells can be configured as a shift register.

Lecture 7



Distributed RAM Cell

Distributed RAM cell formed from a lookup table

Lecture 7



Spartan Dual Port RAM

Lecture 7



Spartan XL Device Attributes

Lecture 7



Spartan II Device Attributes

Lecture 7



Comparison of Spartan Family

Lecture 7



Spartan II Overall Architecture

Lecture 7



Spartan II CLB Slice

Each CLB contains four

logic cells, organized as

a pair of slices.

Each slice has a four-

input lookup table, logic

for carry and control,

and a D-type flip-flop.

Spartan II part family

provides the flexibility

and capacity of an on-

chip block RAM.

1 CLB = 2 slices = 4

logic cells

Lecture 7



Spartan II IOB

Lecture 7



Spartan II IOB

Each IOB has three registers that can function as D-

type flip-flops or as level-sensitive latches.

The first register (TFF) can be used to register the

signal that (synchronously) controls the

programmable output buffer.

The second register (OFF) can be programmed to

register a signal from the internal logic.

The third register (IFF) can register the signal coming

from the I/O pad.

Lecture 7



Virtex II Overall Architecture

Lecture 7



Virtex IOB Block

Lecture 7



Conclusions

We have reviewed and studied the following terms.

Random-Access Memory

Memory Decoding


Programmable logic device

Read-Only Memory



Sequential Programmable Logic Devices

SPLD

CPLD

FPGA

Documents

Memory and Programmable Logicviplab.cs.nctu.edu.tw/course/DCD2017_Spring/DCD_Lecture...Coincident Decoding A two-dimensional selection scheme Reduce the complexity of the decoding