ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

MIPS CPU Lab 1MIPS CPU Lab 1

Student:王奕權

Adviser:吳安宇教授

2004/3/12

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 22004/3/12

A simplified processorA simplified processor

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 32004/3/12

SingleSingle--cycle architecturecycle architecture

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Sign extension unitSign extension unit

16 bit

Input[15:0]

32 bit

output[31:0]

Sign

extension

Sometimes we want to change a 16 bit 2’s complement number to a 32 bit 2’s complement number Input(-5):1111_1111_1111_1011

Output:1111111111111111_1111_1111_1111_1011

Input(+248):0000_0000_1111_1000Output:0000000000000000_0000_0000_1111_1000

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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44--11 MultiplexerMultiplexer

select one of the 4 input signalImplement the module in 2 different ways:

conditional assignment(… ? … : …).use “case” syntax.

Signal_out[15:0]

Ctrl[1:0]

MUX

Signal_1[15:0]Signal_2[15:0]

Signal_3[15:0]Signal_4[15:0]

4-1

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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MultiplexerMultiplexer:I/O pin definition:I/O pin definition

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 72004/3/12

ALU(Arithmetic logic unit)ALU(Arithmetic logic unit)Support several different arithmetic and logic operationsWe need a fast adder in our ALU

N

N

N

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Review of 1 bit Full adderReview of 1 bit Full adder

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Carry ripple adderCarry ripple adder

Carry ripple carry adder has a long critical path and it is very slow

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Carry lookCarry look--ahead(CLA) adderahead(CLA) adder

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CLA adderCLA adderWe want to design the adder “hierarchically”. So follow the next 3 steps

(A)1 bit adder basic block(B)4 bit CLA adder(C)16bit CLA adder

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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((A)1 bit adder basic blockA)1 bit adder basic block

Note: There is NO CARRY OUT pin in this block.

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((B)4 bit CLA adderB)4 bit CLA adder

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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4 4 bit CLA adderbit CLA adder

Note:There is NO CARRY OUT pin in this block.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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((C)16 bit CLA adderC)16 bit CLA adder

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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1616 bit CLA adderbit CLA adder

Note: There is NO CARRY OUT pin in this block.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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NoteNoteYou don’t need to use operator “+” in this CLA design. Use of “+” operation is not allowed.Please complete the design “Hierarchically”.You should use 4 “1 bit adder basic block” in your 4 bit CLA adder module in step B. And you should use 4 “4 bit CLA adder” in your 16bit CLA adder module in step C.This power point file and Lab hand out is on the course website

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Submission listSubmission list4-to-1 Multiplexer verilog source code and simulation waveformsign-extension unit verilog source code and simulation waveformverilog source code of “1 bit adder basic block”(step A)verilog source code of “4 bit CLA adder”(step B)verilog source code and simulation waveform of “16bit CLA adder”(step C)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 192004/3/12

ReferenceReferenceComputer Organization & design, the hardware/Software interfaceDigital Integrated Circuits: A Design Perspective,” 2nd Editioncourse slides of prof. 吳安宇

course slides of prof. 郭斯彥