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Mot so bai tap VHDL
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1. Vit chng trnh VHDL tnh ton biu thc sau: 2axy b
Vi a = 0.01 v b = 2
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
2. Vit chng trnh VHDL tnh ton biu thc sau: 2axy bx c
Vi a = 0.02, b = 0.122 v c = 2
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
3. Vit chng trnh VHDL tnh ton biu thc sau: 3 2ax xy b cx d
Vi a = 0.02, b = 0.122, c = 0.003 v d = 0.01
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Vit chng trnh VHDL tnh ton biu thc sau: 4 3 2ax x xy b c dx e
Vi a = 0.02, b = 0.122, c = 0.003, d = 0.5 v e = 0.01
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
5. Vit chng trnh VHDL nhn hai ma trn sau:
1 11 12 1
2 21 22 2
Y A A X
Y A A X
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
12
1.2 0.3 0.5
0.12 0.5 0.5
Y
Y
6. Vit chng trnh VHDL nhn hai ma trn sau:
1 11 12 13 1
2 21 22 23 2
31 32 33 33
Y A A A X
Y A A A X
A A A XY
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
1
2
3
1.2 0.3 0.3 0.5
0.12 0.5 0.5 0.5
0.5 0.6 0.7 0.5
Y
Y
Y
7. Vit chng trnh VHDL nhn hai ma trn sau:
11 12 11 12 11 12
21 22 21 22 21 22
Y Y A A X X
Y Y A A X X
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
11 12
21 22
1.2 0.3 1.2 0.3
0.12 0.5 0.12 0.5
Y Y
Y Y
8. Vit chng trnh VHDL tnh ton ma trn sau:
1 111 12 13 14
2 221 22 22 22
33 31 32 33 34
41 42 43 44 44
Y XA A A A
Y XA A A A
XY A A A A
A A A A XY
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
0.02 0.03 0.04 0.05 0.2
0.01 0.02 0.03 0.04 0.4
0.03 0.04 0.05 0.06 0.6
0.04 0.05 0.06 0.07 0.8
9. Vit chng trnh VHDL tnh ton ma trn sau:
11 12 13 11 12 13 11 12 13
21 22 23 21 22 23 21 22 23
31 32 33 31 32 33 31 32 33
Y Y Y A A A X X X
Y Y Y A A A X X X
Y Y Y A A A X X X
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 32 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
0.5 0.6 0.7 0.15 0.16 0.17
0.6 0.7 0.8 0.16 0.17 0.18
0.2 0.3 0.4 0.12 0.13 0.14
10. Cho s mch sau:
Yu cu
1. Vit chng trnh VHDL m t s trn.
2. M phng bng vector waveform file
11. Cho php bin i Park nh sau:
os
os
d
q
i iC Sin
i iSin C
Yu cu:
1. To bng d liu hm sin v hm cos.
2. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
3. M phng bng Matlab-Modelsim
12. Cho php bin i Clark nh sau:
2 1 1
3 3 3
1 10
3 3
a
b
c
ii
ii
i
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
2. M phng bng Matlab-Modelsim
13. Cho php bin i Park ngc nh sau:
cos sin
sin cos
de e
qe e
vv
vv
Yu cu:
1. To bng d liu cho hm sin v hm cos.
2. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
3. M phng bng Matlab-Modelsim
14. Cho php bin i Clark ngc nh sau:
1
2
3
ef
ef
ef
1 3
2 2
1 3
2 2
1 0r
r
r
vv
vv
v
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
2. M phng bng Matlab-Modelsim
15. Cho hm sin v hm cos nh sau:
1
2
cos
sin
ey
y
Yu cu:
1. To bng d liu cho hm sin v hm cos.
2. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
3. M phng bng Matlab-Modelsim
16. Cho phng trnh nh sau:
1 1 2 2 3 3* * *Y a x a x a x
Yu cu:
1. Vit chng trnh VHDL dng tun t, tn hiu u vo 16 bit, u ra 16 bit.
2. M phng bng vector waveform file
3. M phng bng Matlab-Modelsim
4. Kim tra kt qu lp trnh bng cc h s sau:
A0 = 0.1, A1 = 0.2001, A2 = -0.4525, X0= 0.2001, X1= 0.2001, X2 = 0.1
Phn 2
Cu 1 Cho mt h thng iu khin c cu trc nh sau:
B PI c thit k vi tn s trch mu l 100 Hz. Khi Plant c thit k vi cc thng
tin:
10; 2n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
H thng lin tc
H thng ri rc
1. Vit chng trnh VHDL m t b iu khin PI trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp v Ki ng ra (Output) bm tt gi tr t u vo
(Input)
Cu 2 Cho mt h thng iu khin c cu trc nh sau:
B PI c thit k vi tn s trch mu l 200 Hz. Khi Plant c thit k vi cc thng
tin:
20; 2n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu khin PI trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp v Ki ng ra (Output) bm tt gi tr t u vo
(Input)
Cu 3 Cho mt h thng iu khin c cu trc nh sau:
H thng lin tc
H thng ri rc
B PI c thit k vi tn s trch mu l 300 Hz. Khi Plant c thit k vi cc thng
tin:
30; 3n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu khin PI trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp v Ki ng ra (Output) bm tt gi tr t u vo
(Input)
Cu 4 Cho mt h thng iu khin c cu trc nh sau:
H thng lin tc
H thng ri rc
B PID c thit k vi tn s trch mu l 300 Hz. Khi Plant c thit k vi cc
thng tin:
30; 3n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu khin PID trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp, Ki v Kd ng ra y(n) bm tt gi tr t u vo x(n)
Cu 5 Cho mt h thng iu khin c cu trc nh sau:
+1
1
z1
z
y(n)
-
x(n)1
1
i
z1
zK
plantpK
)z1(K 1d
+e(n) +
+
u(n)
up(n)
ui(n)
ud(n)
PID controller
Plant
ModelSim
SimuLink
H thng lin tc
H thng ri rc
B PID c thit k vi tn s trch mu l 400 Hz. Khi Plant c thit k vi cc
thng tin:
40; 4n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu khin PID trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp, Ki v Kd ng ra y(n) bm tt gi tr t u vo x(n)
Cu 6 Cho mt h thng iu khin c cu trc nh sau:
+1
1
z1
z
y(n)
-
x(n)1
1
i
z1
zK
plantpK
)z1(K 1d
+e(n) +
+
u(n)
up(n)
ui(n)
ud(n)
PID controller
Plant
ModelSim
SimuLink
H thng lin tc
H thng ri rc
B PID c thit k vi tn s trch mu l 500 Hz. Khi Plant c thit k vi cc
thng tin:
50; 5n
Lu : s dng hm bilinear chuyn qua dng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu khin PID trn, tn hiu u vo 16 bit,
u ra 16 bit.
2. M phng bng Matlab-Modelsim
3. Chn cc thng s Kp, Ki v Kd ng ra y(n) bm tt gi tr t u vo x(n)
Cu 7 Cho b iu ch rng xung (PWM)
+1
1
z1
z
y(n)
-
x(n)1
1
i
z1
zK
plantpK
)z1(K 1d
+e(n) +
+
u(n)
up(n)
ui(n)
ud(n)
PID controller
Plant
ModelSim
SimuLink
H thng lin tc
H thng ri rc
Yu cu:
1. Vit chng trnh VHDL m t b iu ch rng xung trn.
2. M phng bng Matlab-Modelsim
Cu 8 Cho b iu ch rng xung (PWM)
Counter
(8-bit)
Khi so snh
Gi tr so snh T (0~255)
Q(0~255)
Sys_clk
200Hz
T
Q
0
255
Y
Y
Y
256/200 sec
Yu cu:
1. Vit chng trnh VHDL m t b iu ch rng xung trn.
2. M phng bng Matlab-Modelsim
Cu 9 Cho b iu ch rng xung (PWM)
Counter (12-bit)
Khi so snh
Gi tr so snh T (0~4095)
Q(0~4095)
Sys_clk
200Hz
T
Q
0
4095
Y
Y
Y
4096/200 sec
Yu cu:
1. Vit chng trnh VHDL m t b iu ch rng xung trn.
2. M phng bng Matlab-Modelsim
Cu 10 Cho b lc thng thp bc hai nh sau:
2 2
986( )
62.8 986G s
s s
Yu cu:
1. Xy dng mch lc thng thp bc 4 t mch lc thng thp bc hai trn.
2. Chuyn mch lc xy dng bc 1 qua dng ri rc s dng hm Bilinear vi
tn s trch mu 100Hz.
3. Vit chng trnh VHDL m t mch lc thng thp bc 4 xy dng bc 1.
4. M phng bng Matlab-Modelsim vi tn hiu u vo l tng ca hai hm sin
c cu trc v dng sng nh sau:
Counter (16-bit)
Khi so snh
Gi tr so snh T (0~65535)
Q(0~65535)
Sys_clk
200Hz
T
Q
0
65535
Y
Y
Y
Example:
65536/200 sec
5. Dng hm transfer v discrete transfer trong matlab thit k b lc xy dng
bc 1 v bc 2 so snh vi kt qu m phng Matlab/ModelSim.
Cu 11 Cho b lc thng thp bc hai nh sau:
2 2
986( )
62.8 986G s
s s
Yu cu:
1. Xy dng mch lc thng thp bc 4 t mch lc thng thp bc hai trn.
2. Chuyn mch lc xy dng bc 1 qua dng ri rc s dng hm Bilinear vi
tn s trch mu 200Hz.
3. Vit chng trnh VHDL m t mch lc thng thp bc 4 xy dng bc 1.
4. M phng bng Matlab-Modelsim vi tn hiu u vo l tng ca hai hm sin
c cu trc v dng sng nh sau:
5. Dng hm transfer v discrete transfer trong matlab thit k b lc xy dng
bc 1 v bc 2 so snh vi kt qu m phng Matlab/ModelSim.
Cu 12 Cho b lc thng thp bc hai nh sau:
VHDL code
Output
signal
Input signal
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1
-0.5
0
0.5
1
Time (ms)
VHDL code
Output
signal
Input signal
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1
-0.5
0
0.5
1
Time (ms)
2 2
986( )
62.8 986G s
s s
Yu cu:
1. Xy dng mch lc thng thp bc 4 t mch lc thng thp bc hai trn.
2. Chuyn mch lc xy dng bc 1 qua dng ri rc s dng hm Bilinear vi
tn s trch mu 300Hz.
3. Vit chng trnh VHDL m t mch lc thng thp bc 4 xy dng bc 1.
4. M phng bng Matlab-Modelsim vi tn hiu u vo l tng ca hai hm sin
c cu trc v dng sng nh sau:
5. Dng hm transfer v discrete transfer trong matlab thit k b lc xy dng
bc 1 v bc 2 so snh vi kt qu m phng Matlab/ModelSim.
Cu 13 Cho hm step response
Cu 14 Cho hm m
Cu 15 Tra bng Sin & Cosine
Vit chng trnh VHDL tra bng c gi tr Sine v Cosine
1
2
( )*2048
( )*2048
y Sin
y Cos
Bng gi tr hm Sine
VHDL code
Output
signal
Input signal
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1
-0.5
0
0.5
1
Time (ms)
Bng gi tr hm Cosin
on code c hm Sine v Cosine
Cung cp a ch u vo c hm Sine v Cosine
th so snh kt qu m phng bng VHDL v hm Sine ca Matlab
0 0.02 0.04 0.06 0.08 0.1 0.120
100
200
300
400
Time (s)
Waveform of sine
function from Matlab
and VHDL
0 0.02 0.04 0.06 0.08 0.1 0.12-10
-5
0
5
10
0 0.02 0.04 0.06 0.08 0.1 0.12-3000
-2000
-1000
0
1000
2000
3000
Time (s)
Time (s)
(b)
(a)
th so snh kt qu m phng bng VHDL v hm Cosine ca Matlab
Cu 16
Waveform of cosine
function from Matlab
and VHDL
0 0.02 0.04 0.06 0.08 0.1 0.12-3000
-2000
-1000
0
1000
2000
3000
0 0.02 0.04 0.06 0.08 0.1 0.12-2
-1.5
-1
-0.5
0
0.5
1
Time (s)
Time (s)
(a)
(b)