Murali Krishna Ravuru 1613- Gorman street, Apartment-108, Raleigh, NC,27606 mkravuru@ncsu.edu +1(919)-798-6927

OBJECTIVE Obtain a challenging position as a hardware Design/verification engineer in a high-quality engineering environment where I can utilize my expertise in the field of digital design/verification and computer architecture. EDUCATION Master of Science Aug,2015 - May,2017 Computer Engineering, North Carolina State University GPA: 3.8/4.0 Bachelor of Engineering Aug,2010 - May,2015 Electronics and Communication Engineering, BITS-Pilani COURSEWORK Digital ASIC design, ASIC verification, Computer Design and Technology, Design and analysis of algorithms, Architecture of parallel computers, Digital Signal Processing, Computer Networks, Principles of Transistor devices, Analog electronics, Digital electronics SKILL SET Programming Languages : C, C++, Verilog, System Verilog, MATLAB Scripting Languages : Perl (basics) Programming Models : OpenMP, CUDA Design Tools : ModelSIM, Cadence Virtuoso, PSpice, LabVIEW, Design Vision WORK EXPERIENCE R&D intern at National Instruments, Bangalore, India Jun,2014 - Dec,2014

• Worked with the wireless communications team to improve the performance of ACPR measuring device • Designed techniques in LabVIEW to extract high resolution measurements with lower point FFT • Achieved 10-fold performance improvement over the earlier implementation

PROJECTS Functional Verification of LC3 Microcontroller

• Designed a reusable layered test bench in system verilog to verify the functionality of LC3 microcontroller • Achieved high functional coverage by using constrained random testing, directed test cases and

assertions Hardware accelerator for Bellman-Ford algorithm

• Developed a synthesizable RTL code in verilog to implement the Bellman-Ford algorithm • Design is optimized to achieve high performance per unit area

Hardware design to perform inversion of Tri-diagonal matrix

• Implemented the calculation of inverse of a tri-diagonal matrix in verilog HDL • Challenges include timing of the data, effective use of SRAM and implementing the complex FSM

Dynamic instruction scheduling

• Designed a simulator for 8-stage Out-Of-Order super scalar processor which fetches N instructions per cycle • Reorder buffer is used to avoid WAR and WAW hazards involved in Out-Of-Order execution

Cache and Memory hierarchy design

• Implemented a two-level flexible memory hierarchy simulator in C++ • The simulator follows LRU replacement policy and WBWA write policy

Multiprocessor Cache coherency protocols

• Designed a cache coherence protocol (MSI, MESI, MOESI and Dragon) simulator for shared multiprocessor system

• Analyzed the performance of each protocol on various benchmarks Branch predictor design

• Programmed a simulator in C++ to mimic a branch predictor • Modelled G-share, Bimodal and Hybrid branch predictors with 2 bit counters and branch history table