Ngn Ng M T Phn Cng VerilogSinh Vin Thc Hin: CAO VN T- Lp in T 8- K52

Gii ThiuVerilog l mt trong hai ngn ng m t phn cng chnh (gm VHDL v Verilog HDL) c ngi thit k phn cng s dng m t, thit k cc h thng s, v d nh my tnh hay linh kin in t.

Ti sao s dng Verilog HDL ? p ng nhu cu thit k ngy cng phc tp ca phn cng m gin cc cng logic kh c th biu din c. Verilog d hc v d s dng VHDL.Verilog c chun ho theo chun IEEE vo nm 1995 v 2001. Verilog rt ging ngn ng C v c gii chuyn mn nghin cu, s dng nhiu.

Qui c Trong VerilogCc qui c gn vi ngn ng lp trnh C. Li gii thch c t cui cu bi du // hay k hiu /* . . . */. Cc t kha c dnh ring v tt c k t l ch thng. Ngn ng phn bit ch in v ch thng.

Qui c Trong VerilogMt s c th c du hoc khng du c xc nh theo cng thc Trong : + xc nh s bit. + l k t n , l mt trong cc k t b (nh phn), d(thp phn), o(bt phn) v h (thp lc phn). + cha cc ch s ph hp.

Qui c Trong VerilogV D: 4b1101 // s nh phn 4 bit 1101 5d3 // s thp phn 5 bit - 4b11 //s b hai 4 bit ca 0011 l 1101

Module Trong VerilogNgn ng Verilog m t h thng s nh l thit lp mt module Cu trc mt module nh sau: module module_name (danh sch cc port); //cc khai bo input, output, inout, reg, wire, parameter . . . //cc cu lnh Initial statement Always statement Module Instantiation Continuous assignment endmodule

Module Trong VerilogV D: Thit k m hnh hnh vi cho cng NAND: module NAND (in1, in2, out); input in1, in2; output out; assign out=~(in1&in2) endmodule Vi & l ton t and, ~ l ton t o bit. iu lnh assign ch s thay i v phi biu thc v kt qu c gn cho biu thc bn tri (ng ra out).

Kiu D Liu Trong VerilogV mc ch ca Verilog HDL l thit k phn cng s, nn loi d liu c bn thit k l thanh ghi (reg) v dy (wire). Bin reg lu tr gi tr trc , gi tr c gn theo qui trnh, trong khi bin wire m t s kt ni vt l gia cc thc th vt l nh cu trc cc cng. Wire khng lu tr gi tr. Thc t mt bin wire ch l mt nhn trn dy. D liu wire ch l mt trong nhng loi d liu net trong Verilog HDL

Kiu D Liu Trong VerilogCc i tng d liu wire v d liu reg c th c nhng gi tr sau : 0 logic 0 hoc sai 1 logic 1 hoc ng X gi tr logic khng xc nh Z trng thi tng tr cao ca cng ba trng thi Bin reg c gn gi tr ban u l X u chng trnh. Bin wire khng c ni vi bt k ci g cng c gi tr l X.C th xc nh c ca thanh ghi hoc dy trong khai bo.

Kiu D Liu Trong VerilogV d : reg [7:0] A,B; //thanh ghi A v B c 8 bit t 0 n 7, bit cao nht l bit 7 (MSB) wire [3:0] data; //dy data c 4 ng t 0 - 3

Vng Nh Ca VerilogVng nh c nh ngha ging nh vect ca thanh ghi. V d mt vng nh gm 1024 t, mi t 16 bit. reg [15:0] Mem [1024:0]; K hiu Mem[0] s tham chiu n vng nh u tin . . . Ch rng khng th tham chiu n mt bit trong 1 t ca vng nh, mun lm iu ny phi chuyn d liu vo mt thanh ghi trung gian.

Ton T Ca VerilogGm cc ton t quan h so snh 2 ton hng v tr ra gi tr logic. ng l 1, sai l 0. Nu bt k bit no khng xc nh th kt qu ra l khng xc nh. > ln hn >= ln hn hoc bng < nh hn dch phi thanh ghi ?: iu kin

Ton T Ca VerilogV d :Dng iu lnh assign vit mt module gii a hp t 2 ng sang 4 ng (bn c th t vit gii a hp t 3 sang 8 hay 4 sang 16) module demux(data,in1,in0,out0,out1,out2,out3); input data; input in0,in1; output out0,out1,out2,out3; assign out0= data&(~in1)&(~in0); assign out1= data&(~in1)&(in0); assign out2= data&(in1)&(~in0); assign out3= data&(in1)&(in0); endmodule

Cc cu trc iu khinVerilog rt phong ph cc cu lnh iu khin c th s dng trong phn th tc. Hu ht chng rt quen thuc vi nhng ngi lp trnh bng ngn ng C. im khc bit ln nht chnh l thay du ngoc {} trong ngn ng C bng t kha begin v end trong Verilog HDL, du ngoc {,} dng ni chui cc bit.

Cc cu trc iu khin1, Cu trc ifelse

2, Cu trc case khng ging cu trc case trong C ch khng cn lnh break. V d : case (State) st0: State = st1; st1: State = st2; st2: State = st3; st3: State = st0; endcase

Cc cu trc iu khinNgoi ra cn c cc vng lp for, while v repeat. Tuy nhin chng rt him khi s dng trong vic m t cc module nn ta s khng cp n.

Cc cu trc iu khinV d : Mt module 3 trng thi dng always v cu trc if . . .else, nu ng Con l 1 th ng ra bng ng vo, nu Con l 0 th ng ra s trng thi tng tr cao: module tristate(In,Con,Out); input In,Con; output Out; reg Out; always begin if (Con==1'b1) Out=In; else Out=1'bz; end endmodule

iu khin theo s kiniu khin theo s kin c hai loi : iu khin theo tc ng cnh v iu khin theo tc ng mc. iu khin theo tc ng cnh hay mc c dng nh sau : @ s kin iu khin cu lnh

iu khin theo s kinV D: always @(posedge clock) // tc ng cnh ln ca xung clock always @(negedge clock) // tc ng cnh xung ca xung clock always @(register1) // tc ng vi bt k s thay i no trn thanh ghi register1

S Kt Hp Gia Nhiu ModuleDo trong mt module ln, thng thng ngi ta phi chia ra nhiu module nh d vit v d kim sot li hn. Do cn phi c mt top module gp tt c cc module nh li tr thnh mt module duy nht. S kt hp module c dng sau: Tn module (port kt hp); Port kt hp c th khai bo theo dng : .tn port (port mi nh ngha)

S Kt Hp Gia Nhiu ModuleV D: C mt module AND(in1,in2,out) v mt module NOT(in,out), thc hin s kt hp 2 module trn thnh module top: module top(A,B,D); input A; input B; output D; wire C; AND and (.in1(A), .in2(B), .out(C)); NOT not (.in(C), .out(D)); endmodule Lu : and v not l tn mi ca 2 module AND v NOT trong module top.

Non Blocking v Blocking

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