No.232, Yung- Chang Street, Ying-Ko, Taipei, Taiwan, R.O.C. Tel :886-2-2678-7966 Fax:886-2-2678-0160 程式发展流程 Tonyluo

No.232, Yung- Chang Street,Ying-Ko, Taipei, Taiwan, R.O.C.Tel :886-2-2678-7966Fax:886-2-2678-0160

程式发展流程

• Tonyluo


Libraries.ATX.CKT

CKT NAIL TRAN DEBUG

Enter Components.CIR

.CIR

.CKT

.CRP

.OBC

.SMT

.LIS

ATGStep

1

.WOR

.DAI

.IDX

.AXR

.ERR

.ATP

.RPT

.DTP

.MSG

.TPX

Updates.CKT.ATO.IDD.TPG

Creates.NAR.NFR.NLS.NDB

.TPX

.CKT

.ATX

.IDX .TPG

Real Time Debugger.DBT

Modify.INC.ITL

Update.TPU.DBO.TPG

.OBC

.SMT

.IDD

ATGStep

2


CADDATABASE

ANNOTATESCHEMATICWITH NODENUMBERS

CREATEMODE

REVISEMODE

GENERATEMODE

READMODE

CKTGEN

CREATE .CKT FILE MANUALLY USING CDL STATEMENTS

USECKTGEN

.CIR.CRP

.CKT

.CRP(REPORT)

.CKT(CIRCUIT DESCRIPTION)

.NDB(NAIL DATABASE)

.ERC(ERROR LISTING)

.CIR

.CIR

3931.1

Circuit Generation Flow


CKTGEN Mode Function

CREATE Creates a .CIR file from the entered component information in this mode, which can be used by GENERATE or REVISE.

GENERATE Generates a .CKT file from the .CIR file

REVISE Makes changes to an existing .CIR database file

READ Accepts an existing .CKT file and produces a .CIR file that is used by REVISE and GENERATE mode. Use READ mode when a .CKT file needs to be changed and the corresponding CKTGEN database file (.CIR) file does not exist or cannot be located.

ALLOCATE_SPECIAL

Use when .CKT is generated outside of CKTGEN. Compares component types used against system and user libraries and allocates special tester resources such as clock drivers, clock syncs and triggers required by models.


Describes circuit components and how they are connected.

CircuitDescription file is separated into five sections:

/* comments section */

%CIRCUIT, %GROUP,%VALUE,%ADAPTOR

/* comments section */

Comments that identify the pc board for which the program was written.

It is also recommended to use this section for keeping a record of any modifications made to the file.

%CIRCUIT;

Contains the Name, type and circuit connections of every component.

R1 R CR1_A, Q1_B;

%GROUP;

This optional section contains groups of banked devices and cluster devices, which can be tested in parallel.

BANKNAME BANK COMPONENT-NAME LIST;

%VALUE

Contains the value, tolerance, flagspecs and special operator messages.

R1 = 1K, MSG='8875-5446-00';

%ADAPTOR

Defines tester type(s) supported by each %ADAPTOR section: %ADAPTOR:2286TEMP;

Multiple adaptor sections are permitted in each file.

Maps the circuit connections to the test system nails.

Syntax TEST-NAIL(s) = CIRCUIT-NODE(s);

Example F1 = U9_1;


Circuit Description Program Elements

1 2

RESISTOR RESISTANCE(OHMS)

BASIC CIRCUIT ELEMENTS

CAPACITOR(NON-POLARIZED)

CAPACITOR(POLARIZED, UPTO 1 V REVERSEVOLTAGE)

INDUCTOR

DIODE

ZENER DIODE

J UMPER

NO J UMPER

FUSE

OPEN CONTACT

CLOSED CONTACT

POTENTIOMETER

TRANSISTOR(NPN)

R

C

CP

CP1

L

CR

VZ

J

OJ

F

NO

NC

RV

QN

1 2

P N

1 2

P N

A C

A C

1 2

1 2

1 2

1 2

1 3

2

(CCW) (CW)"

1 2

BC

E

CAPACITOR(POLARIZED, NOREVERSE VOLTAGEPERMITTED)

CAPACITANCE(FARADS)

CAPACITANCE(FARADS)

CAPACITANCE(FARADS)

INDUCTANCE(HENRYS)

KNEE VOLTAGE(VOLTS) [.65]

ZENER VOLTAGE(VOLTS)

RESISTANCE(OHMS) [.001]

RESISTANCE(OHMS) [<10]

RESISTANCE(OHMS) [<1]

RESISTANCE(OHMS)

MIN. GAIN[20]

MAX. GAIN[500]

[5%]

[20%]

[30%]

[20%]

[20%]

[5%]

[5%]

[10%]

RHIRESID

RLORESID

ILIM [.128]

[3.2 ohms]

[1.8 ohms]

CHIRESID [20 pF]CLORESID [5 pF]FREQ

[System-optimized]



LERR [1.0]DCR [1 ohm]FREQ

RTOL[No Resistance Test]

[System-optimized]

DR [*]DRHDRLIFV [20 mA]IDR [5 mA]

IZT [(7.8 X 16/VZ) mA]ZZT [(17 X VZ/16) ohms]

RERR [1.0]RHIRESID [3.2 ohms]RLORESID [1.8 ohms]

R23 [0.5 VALUE]RERR [1.0]RHIRESID [3.2 ohms]RLORESID [1.8 ohms]ILIM [.128]PRESETFASTATG

VBE [0.6]VCE [5.0]IC [10 M]FASTATG

RERR [1.0]RLOV [500 ohms]RHIV [1 MEG]FASTATG

CERR [1.0]FASTATG

CERR [1.0]FASTATG

CERR [1.0]FASTATG

LHIRESID [15LLORESID [5

FASTATG

ILIM [.128]

H]H]

[10%]

NOTES: Items enclosed in brackets ([ ]) are defaults for unspecifieditems.See discussions in section 6.12 for program formatdetails.See discussions in section 6.12 for explanations of how to useflagspecs.

* Depends on KNEEVOLTAGE.

DEVICETYPE

CDLSYMBOL

PINASSIGNMENT

VALUE SECTION SPECIFICATIONS

NOMINALCHARACTERISTIC

VALUETOLERANCE

CKTGEN PAGEFLAGSPECS

For additional device flagspecs supported in the analog test library, refer to the GR228X Test Library ProgrammingManual.

DIGJ UMP

3941.1


ATG Monitor Page


File Type Extension (Temp/Final)

ASCII /Non-ASCII

Compiled Circuit Description .WOR N

Circuit Desc. Error Listing .ERR A

In-circuit Diagnostic Data File .IDX/IDD N1&2

Circuit Desc.Extractor Report .ERP A

Cross Reference Report .AXR A1

Automatic Test Options File .ATX/ATO A1

Analog Test Program .ATP A

Analog ATG Results Report .RPT A1

Digital Test Program .DTP A

Digital ATG Results Report .MSG A1

Merged Test Program (Source) .TPX/TPG A1

Fixture Test Program .FTP A1

Connectivity Test Program .CTP A1

1 These files should be archived for Test Set Support.2 These files are needed for the RTS (Run Time system).


Automatic Test Generator (ATG) Flow

Automatic test generation (ATG) using the ATG monitor page is designed to allow specific (Y/N) control to each major ATG process.

ATG is purposely divided into two steps.

ATG STEP-1 processes the input (.CKT) file and necessary component library information into binary (.WOR) and (.IDX) files. An ASCII (.AXR) circuit cross reference report is also generated. By careful review of the (.AXR) file, you validate your CKTGEN data entry and make any necessary corrections before developing actual test programs in ATG STEP-2.


.ATO

#ATG STEP 1

Any

#PRINT.AXR

Errors?

Power Editor

Return toCKTGEN andRevise Mode

Repair All Errors

Circuit Prepare = Yes

IDD Prepare = Yes

Cross Reference = Yes

ANA = NoDIG = NoMER = NONAIL STATE = TempACLuser = NDTLuser = N

(Y if available)

A

.CKT .ACL.DTL

.WOR

.WOR

.WOR .ERR

.IDX .ERP

.AXR

.DTL

B

Evaluate .AXR

.IDX

.TPL

.CPD.ATX

.FWI

.PTP


ATG STEP-2, via user selectable options, generates test programs in separate files including an analysis report for each test program. Each analysis report must be carefully scrutinized for warnings, errors, and post ATG summary information for every component.

Note that it is optional to re-run ATG STEP-1 options during ATG STEP-2.

#ATG STEP 2

Analog = Yes

Digital = Yes

Merge = Yes

ATLusr = NDTLusr = NATXusr = Y ATX =

NAIL = Temp

#

B

.ATX .WOR .ATL

.ATX .DTL

.ATP .DTP

.ATP .RPT

.DTP .MSG

.TPX

C

CIR

=

No

IDD

=

No

Cross

=

No

PTP=Y


Nail Assignment Flow

#PRINT or TYPEIN = .RPT,.MSG,

#

#NAIL ASSIGNMODE = New

LOW NAIL = 1HIGH NAIL = 640TPXin =

.NFR,.NAR

IDXin = Y

CKT = Y

NDB = N

IDD =CKT =ATO =

#

.TPX

.IDX

.CKT

.TPG

.IDD

.CKT

.NFR

.NAR

.NDB

C

UPDATE = YesNFR TYPE = Final

ATX = Y

.ATX

D


Nail Assignment Monitor Page Default File Extensions

Report NameExtension Used …

Nail Fixture Report .NFR1 When wiring the fixture

Nail Assignment Report .NAR1 To keep a record of nail assignments

Nail Data Base Report .NDB1 As a database toward changing subsequent nail assignments

Nail Assignment Listing .NLS To evaluate the nail assignment process

Nail Contact List .NCL1 To verify the contacts in the fixture

Nail Wire Length .NWL1 As a reference when a short-wire fixture is built

Wire Data Base File .WDB1 By some fixture vendors in building short-wire fixtures


NAIL ASSIGNMENT Page


Nail Assignment Process

NAIL WIRE *

assignments)

TEMPORARYNAIL

NUMBERS

.CKT

ATG

.ATX

.TPX

.IDX

.NDB

.TPX

Analyze

NAIL ASSIGNMENT

.ATO

.CKT

.TPG

.IDD

.NFR

.NAR

.NLS

NAILSREPLACE

TEMPORARYNAILS

NAIL FIXTUREREPORT

NAILASSIGNMENT

REPORT

NAILASSIGNMENT

LISTING

ACTUAL

(User-specified

UPDATE

.TPG

.IDD

.CKT

GENERATEOUTPUT

REPORTS

Input Files

.IDX

.NDB .ATO

.ATX

.NCLNAIL

CONTACTLIST

42697.1

.NWL

.NOP

WIRE DATA BASE.WDB

LIBRARIES

.NDBNAIL

DATABASE

.CKTPreprocessor

.FDS.FDS

LENGTH

* The .NWL file is used for a short wire assignment goal.

software tocreate Nail

Assign wiringrestrictions.

(SHORT-WIREonly)


Translate Page


Default File Extensions

MonitorMode File Type

Extension (Temp/Final)

ASCII /Non-ASCII

TRAnslate Test Program Source .TPG A1

Object Code .OBC N1 &2

Error Listing .LIS A

Symbol Table .SMT N1

1 These files should be archived for Test Set Support2 This file is needed for the RTS (Run Time System).


Translate and Debug Development Flow

#TRANSLATE

Debug the

TPG =

#

Build YourFixture

OBC =SMT =LIS =

Test Program

.TPG

.OBC

.SMT

.LIS

D


Documents

No.232, Yung- Chang Street, Ying-Ko, Taipei, Taiwan, R.O.C. Tel :886-2-2678-7966 Fax:886-2-2678-0160 程式发展流程 Tonyluo