Upload
santi-navarro-moral
View
220
Download
0
Embed Size (px)
Citation preview
8/3/2019 Notas Explicativas-Temas 3 y 4
1/20
Section 1.1 - Switched-Capacitor Basics 1
1 Discrete-Time Applications
This chapter presents the basic principles and some practical aspects regarding the design of
switched-capacitor (henceforth SC) circuits, with special emphasis on their filtering applications.
1.1 Switched-Capacitor Basics
Switched capacitor (SC) circuits are sampled-data or discrete-time systems for analog signal pro-
cessing successfully constructed using integrated circuit MOS technologies [Mosc84, Alle84,
Greg86, Tsiv85]. They emerged from active RC networks as a solution for two main problems that
these present for monolithic implementation: inaccurate RC products and large R and C values
requiring prohibitive chip area. SC techniques achieve integrated circuits with accurate simulated
resistors in a small area, with programmability and tuning capabilities, and are compatible with dig-
ital circuits.
Generally speaking, there are three important factors to take into account when designing SCcircuits:
a) Design methodology to be adopted,
b) Restrictions imposed by the technology, and
c) Method used to derive discrete-time systems from the continuous-time domain.
Some of these aspects have been treated in previous chapters; the remainder, in particular those
relating to filters, will be considered here.
Practical SC circuits are composed of switches, capacitors, and op-amps. Switches are the on-
off type, controlled by periodic signals called clocks. Typically, clocks in a system are assigned to
phases of a principal clock with a period T. That is, a time interval Tis divided into n subintervals,
known as clock phases. A clock with period Tand four phases (1-4) is shown in Fig.1.
A switch will be closed when the clock phase controlling it assumes the high value; otherwise
it is open. In circuits using several phases, part of the switches are closed and part are open during
an interval T, thus a distinct equivalent circuit is obtained during each clock phase. The ideal opera-tion of the network may be analyzed by replacing closed (open) switches with short (open) circuits.
1 2 3 4 1 2 3 4
T
(nT-T) nT (n+ T (n+ )T1 )
3
Figure 5-1. Four phases clock signal
t
4 4
1
2
3
4
Fig. 1 : Four phase clock signal
8/3/2019 Notas Explicativas-Temas 3 y 4
2/20
2 Chapter 1 - Discrete-Time Applications
To understand the basic principles of SC circuit operation, let us consider the simple circuit
in Fig.2a. There, capacitor Cis periodically switched between two voltage sources: v1 and v2. Con-
sidering ideal switches, the circuit operates as follows: during 1 (i.e., 1 high, nT t ((n + 1/2)T), S1 (S2) is closed (open) and capacitor Cis charged to v1; hence the charge stored in Cvaries
accordingly during this interval:
(1)
where vC(nT--) represents the initial voltage in Cbefore closing S1. This charge flows from the
voltage source v1 as a sharp current pulse, i1(t), shown schematically in Fig.2b.
Next, during 2[(n + 1/2)Tt(n + 1)T)] the capacitor is charged to v2; thus the chargevariations in Care:
(2)
where vC((n + 1/2)T) is the voltage in Cbefore S2 is closed, and thus equals the final value
achieved during the previous phase; that is, vC((n + 1/2)T-)=v1.
Hence, a charge q2 = C(v2 - v1) now flows from the source v2 as a sharp current pulse i2(t).IfCis alternately charged to v1 and v2, an average equivalent current can be defined as the charge
flowing in each clock period Tdivided by T. Assuming the polarities indicated in Fig.2a and that
v1 and v2 do not change with time, the average currents will be:
(3)
It can be deduced from (3) that the SC structure in Fig.2 usually behaves as a continuous resis-
torR = T/Cconnected between sources v1 and v2 (Fig.2c).
Table 1 presents a summary of other SC structures available for resistor simulation. All of
these structures can be analyzed as previously explained. The equivalentR value for each case isincluded in this Table.
T
(n )T nT (n+)Ti1 1 2 i2
(S1) (S2)
V1 V2
I1 aver. R=T/C I2aver.
V2
1
2
i1(f)
i2(f)
C
V1
1 1
2 2
(b)
(c)
(a)
Fig. 2. SC realization of a two terminal resistor. a) Parallel capacitor SC structure. b) Clocks and
current waveforms. c) Equivalent average circuit
q1 C v1 vC nT
( )[ ]=
q2 C v2 vC n1
2---+
T
=
I1aver I2aver
q1
T---------
q2
T------------
C v1 v2( )
T-------------------------= = = =
8/3/2019 Notas Explicativas-Temas 3 y 4
3/20
Section 1.1 - Switched-Capacitor Basics 3
It must be pointed out that whenever v1 and v2 change with time,I1aver I2aver and the SC inTable 1 will generally not be equivalent to a two terminal resistor. However, when Tis small enough
so that v1(t +T) and v2(t + T) do not differ significantly from v1(t) and v2(t) respectively, the resistor
equivalence holds. In other words, the SC structures in Table 1 simulate linear resistors ifv1(t) and
v2(t) have a frequency much smaller than the clock frequency (f
8/3/2019 Notas Explicativas-Temas 3 y 4
4/20
4 Chapter 1 - Discrete-Time Applications
in active implementation:
a) Largeresistors can be obtained with small capacitors by using the appropriate clock fre-
quencyfc = 1/T. For instance, for C = 1pFandfc = 100 kHz, an equivalent resistor of 10Mcan be implemented.
b) Time constant accuracy now depends on the clock frequency accuracy (very precise when
crystal generators are used) and on the capacitor ratio accuracy (0,1%).
In spite of these advantages, one of the most important drawbacks of SC circuits is the exist-
ence of stray capacitances related to capacitors, switches, and op-amps in MOS technology. Gen-
erally the success or failure of an integrated SC circuit depends on the influence of these stray
parasitics. As an example of stray effects, let us once again consider the circuit in Fig.2a. In mono-
lithic MOS capacitors there are two unavoidable nonlinearparasitic capacitances associated with
C: the capacitance of the top plate, Ct, and of the bottom plate, Cb. The value ofCb depends on
the area ofC, and may be as much as 10% ofC; however, Ct is smaller and independent of the C
value. If the bottom plate ofCin Fig.2a is connected to both switches at its top plate to ground,
the actual equivalent resistor will be T/(C + Cb) instead ofT/C. Thus, the parasitics affect both the
accuracy and the linearity of the circuit.
[Hasl81] showed that SC circuits can be made insensitive to stray capacitances if they meet
the following topological constraints:
a) The resulting equivalent circuit in each clock phase contains no nodes other than input volt-
age source, op-amps input and output, and ground nodes.
b) A capacitor terminal is never switched from a low impedance node in a phase to a virtual
ground (high impedance node) in another phase and viceversa.
Bearing this in mind it is easy to realize that if any v1 or v2terminals of the circuits in Table
1 are connected to the virtual ground in an opamp, only the last two structures lead to stray-insen-
sitive resistor simulation.
In addition to parasitic capacitors, other nonidealities must be taken into account in SC cir-
cuits, mainly those related to real MOS switches and nonideal op-amps. Since the analysis of SC
circuits considering these effects is quite complicated, we will assume only ideal elements in this
chapter. Some general considerations for practical SC realizations with nonideal components will
be made at the end of the chapter.
As shown, for time variants v1 and v2, the simplest approach to design SC circuits using one-
by-one resistor replacement in a continuous-time active prototype requires high ratio between
clock and input signal frequencies. We will see how this ratio effects the accuracy of the simula-
tion depending on the realization chosen and the circuit in which it is included. In any case, this
approach always leads to approximate filter design. Hence, we will introduce alternative design
methodologies which allow exact sampled-data realizations of filtering functions.
1.2 Description of SC Circuits in the Time and Frequency
Domains
An important aspect to bear in mind when analyzing SC circuits is that they are time-variant sys-
tems that process continuous time signals, which are usually of the sample-and-hold type. The
time-variant nature of SC circuits is the result of the switching action of clock signals which alter-
nately change the circuit topology as the switches open and close. The resulting circuits are inter-
related, where the state of one determines the initial conditions for another.
The analysis of SC networks is mathematically complex when no restrictions are imposed onthe switching pattern or the form of the input signals. [Tsi83] introduced analysis techniques to
derive general input-output difference equations, as well as the frequency-domain descriptions of
SC networks. In this section we will not go into the detail of such analysis techniques, but rather
8/3/2019 Notas Explicativas-Temas 3 y 4
5/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 5
remark on those aspects that are important for correct interpretation of the circuits described herein.
The fundamental point in deriving SC circuit functions is the nature of their input and output
signals.
For the time domain description of SC circuits, branch voltages and injected charges in capac-
itors are used as variables. Injected charge refers to charge variation q(t) in a capacitor during aspecified period of time, which satisfies the charge conservation principle expressed as:
or
(4)
where v is the voltage between both terminals of the capacitor C.
Since charge variations are used instead of currents, Kirchhoffs Current Law must be written
in terms ofq as:
(5)
A simplified representation of an SC circuit is as a discrete-time system whose input and output
are sampled during the same sampling period. The samples are viewed as simple discrete sequences,
regardless of the exact point within each period they appear. Thus, the general difference equation
describing the network is expressed as:
(6)
wherexD(.) andyD(.) represent the input and output digital sequences, respectively. Applying thez-
transform to the above equation results in the following transfer functionH(z):
(7)
where the equalityz = esT can be used to mathematically relate the z-transform for discrete-time sys-
tems to the Laplace transform for continuous-time systems. Thus, the discrete-frequency response
may be evaluated usingz= ejwT, which implies evaluation ofz-plane in the unit circle.
When the exact sampling instants are considered for either input or output, the general equation
describing the network is:
(8)
where only one sample per periodx(nT +1) andy(nT + 2) is considered. Now, thez-transformis not directly applicable to (8). However, analysis using phasor concepts and defining the symbolz
= es associated to time delay , obtains the following transfer function [Tsiv83]:
charges injected
in time slotIk(nT +k, t)
=
charges stored
in the C at
charges stored in
C at the instantnT + kthe instant t
-
q( ) k( ) t( ) C v t( ) v nT k+( )[ ]=
q t( )( )j 1=
n
0=
ai yD n i( ) T
i 0=
bi xD n i( ) Ti 0=
=
H z( )YD z( )
XD z( )--------------
bi zi
i 0=
M
ai zi
i 0=
N
-------------------------= =
a1
i 0=
N
y nT iT 2+( ) b1i 0=
M
x nT iT 1+( )=
8/3/2019 Notas Explicativas-Temas 3 y 4
6/20
6 Chapter 1 - Discrete-Time Applications
(9)
which evaluated in s = jw gives the frequency responseH(jw) of the circuit.
A complete description of any system response almost always requires knowing the wave-
form between sampling instants. In this sense, the two transfer functions (8) and (9) are not com-
plete descriptions.
However, in most practical SC applications the samples at instants nT+ of the output remainconstant during a whole switching period T. In these cases, the low-pass filtering effect of the zero-
order holder must be introduced at the output. The transfer function should then be modified by
the product of the sinc function. Thus, when there is no continuous path between input and output,
the generic response description is obtained from (9) as:
(10)
Note that if the input is also a sampled-and-held signal for the same switching period T, the
low-pass filtering effect also appears at the input spectrum. The transfer function in thez-domain,
H(z) is then enough to describe the circuit.
More complex descriptions are required if continuous paths exist between input and output.Details regarding these cases are available in [Tsiv83].
1.2.1 Switched-Capacitor Integrators
It is well known that integrators are basic components in active RC filters. These circuits also
serve as building blocks for higher-order SC filters. SC integrators are derived from continuous-
time active integrators by replacing resistors with SC structures. Figure 3 shows the standard par-
asitic-free lossless inverting and noninverting integrators (Fig.3b and c, respectively) derived
from the Miller integrator (Fig.3a).
As the transfer function describing SC circuits depends on the sampling patterns, two output
are drawn as dashed lines, indicating that the output can be sampled at the end of1
(labelled vo
(1))
or at the end of2 (labelled vo(2)).
To analyze these circuits let us assume that:
a) Switches are controlled by two nonoverlapping clock signals 1 and2 with approximately50% duty cycle.
b) Input voltage vi is instantaneously sampled at the beginning of phase 2 and remains con-stant during the next phase: vi[(n +1/2)T] = vi(nT). (For simplicity, in the following we will
use v(n) instead ofv(nT) to indicate the value of the sample at instant t=nT.)
First consider the integrator in Fig.3b. The equivalent circuits for both phases are presented in
Fig.4. During 1 both terminals ofC1 are grounded; thus C1 is discharged. Since C2 and the opampare isolated, the output vo does not change. During 2, the current flows through C1 connecting viand virtual ground, and through C2. Thus, the charges of both capacitors C1 and C2 change. The
charges injected into C1 and C2 during 2 can be obtained applying the charge conservation prin-
H s( ) z
1 2( )T
--------------------
b1
i 0=
M
zi
a1
i 0=
N
zi
--------------------------=
H jw( ) H jw( )HSHjw( ) H jw( )e
jwT
2---------
wT
2-------sin
wT
2-------
---------------= =
8/3/2019 Notas Explicativas-Temas 3 y 4
7/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 7
ciple:
(11)
(12)
where vC1(n - 1/2) and vo(n - 1/2) are the voltage in C1 and at the output node, respectively, during
the previous 1 phase. Analysis of the equivalent circuit in Fig.4a results in:
(13)
q1 n( ) C1 vi n( ) vC1 n1
2
---
=
q2 n( ) C2 v o n( ) vo n1
2---
+ =
vC1n
1
2---
0=
_
+
_
+
t
H(s)= =V1(s) sRC2
Vo(s) 1
R
v0
C2
(a)
(b)
vi
2 C1 2
C2
1 1
v0
v0
v0
(1)
(2)
1
2
vi
_
+
(c)
2 C1 1
C2
1 2
v0
v0
v0
(1)
(2)
1
2
vi
V0(1)
(z)= Vi(2)
(z)c1 z
-1/2
c2 1-z-1
V0(2)
(z)= Vi(2)
(z)c
11
c2 1-z-1
V0(1)
(z)= Vi(2)
(z)c1 z
-1/2
c2 1-z-1
V0(2)
(z)= Vi(2)
(z)c1 z
-1
c2 1-z-1
nT(n-1)T (n )12
1
2
Fig. 3. a) Continuous-time Miller integrator.,b) Parasitic-free inverting BE (Vo(2)) or LDI (Vo
(1)) integra-
tor.c) Parasitc-free noninverting FE (Vo(2)) or LDI (Vo
(1)) integrator.
8/3/2019 Notas Explicativas-Temas 3 y 4
8/20
8 Chapter 1 - Discrete-Time Applications
(14)
Substituting (13) and (14) into (11) and (12), and using the equivalent Kirchhoffs Current
Law at the virtual ground node, q1 - q2= 0, we obtain
(15)
Equation (15) is the first-order difference equation describing the circuits operation. Apply-
ing thez-transform to Eq. (15), results in the following transfer function:
(16)
where the superscript (2,2) means that both input and output signals are sampled at the same clock
phase 2.
Note that the same vo is available during the next 1 phase; thus, sampling vo in this phaseintroduces a half period delay, resulting in the following transfer function:
(17)
which confirms that transfer functions of SC circuits depend on the switching pattern.
The noninverting integrator in Fig.3c can be analyzed in a similar manner. There, at the end
of2, capacitor C1 is charged to vi(n) and capacitor C2 does not change the charge acquired in theprevious phase 1. Thus, during2,
(18)
(19)
Applying the charge conservation principle at the virtual ground node of the opamp during
the next 1 we have,
(20)
(21)
Thus q1 - q2 = 0 gives:
vo n1
2---
vo n 1( )=
_+
_+
(a) (b)
C1
C2
v0
vi
C1
C2
v0
q2q1
Fig. 4.Equivalent circuits for the inverting integrator during a) 1 and b) 2
vo n( ) vo n 1( ) C1C2------vi n( )=
H2 2,( )
z( )Vo
2( )z( )
Vi2( )
z( )-----------------
C1
C2------
1
1 z1
----------------= =
HI2 1,( )
z( )Vo
1( )z( )
Vi2( )
z( )-----------------
C1
C2------
z
1
2---
1 z1
----------------= =
vC1 n( ) vi n( )=
vo n( ) vo n1
2---
=
q1 n1
2---+
C 1 vi n( )=
q2 n1
2
---+ C2 vo n
1
2
---+ vo n( )+=
8/3/2019 Notas Explicativas-Temas 3 y 4
9/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 9
(22)
Considering (19) andz-k for a k-time delay operator, the following transfer function in the z-
domain is obtained from (22):
(23)
which can be written as
(24)
Once again, note that vo remains constant during the next 2 phase, vo(n+1) = vo(n+1/2), andthus,
(25)
At this point, we can confirm that both SC integrators in Fig.3b and c, implement discrete trans-
fer functions in thez-domain, but now the question arises of how closely these transfer functions
resemble their continuous time counterpartsH(s) = 1/sRC2, derived from the circuit shown in Fig.3a.
Comparing H(s) and the differentH(z), shows that eachH(z) can be obtained fromH(s) through
a particular transformation from the s-domain to thez-domain. Thus, consideringR = T/C1, the fol-
lowing transformations result:
(26)
(27)
(28)
The above s-z relations are known respectively as Euler Forward, Euler Backward and Lossless
difference transformations. They are derived by considering numerical approximations of the deriv-
ative operator. For this reason, the discrete time integrator withH(z) in Eq.(26) is known as a For-
ward Euler integrator (FE); withH(z) in Eq.(27) is known as a Backward Euler integrator (BE); and
Eq.(28) refers to theH(z) of a Lossless Discrete Integrator (LDI).
These results lead to the following conclusions:
a) The circuits in Fig.3b and c can both serve independently as parasitic-free inverting and non-
invertingLDI integrators, respectively Eq.(17) and (24).
vo n1
2---+
vo n( )C1
C2------ vi n( )+=
H2 1,( )
z( )Vo
1( )z( )
Vi2( )
z( )-----------------
C1
C2------
1
z
1
2---
z
1
2---
------------------= =
H2 1,( )
z( )C1
C2------
z
1
2---
1 z
1
----------------=
H2 2,( ) C1
C2------
z1
1 z1
----------------=
H s( )s
1
T--- z 1( )
H z( )C1
C2------
z1
1 z1
----------------=
H s( )s
1
T---z 1
z-----------
H z( )C1
C2------
1
1 z1
----------------=
H z( )s
1
T---z 1
z
1
2---
-----------H z( )
C1
C2------
z
1
2---
1 z1
----------------=
8/3/2019 Notas Explicativas-Temas 3 y 4
10/20
10 Chapter 1 - Discrete-Time Applications
b) Owing to the phasing requirements, the inverting integrators can be BE or LDI, and the non-
inverting will be FE and LDI.
c) The cascade of a BE integrator and a FE integrator is equivalent to the cascade of two LDI
integrators. Note that to properly connect two LDI integrators, they must be switched in
opposite phases.
In addition to the Euler and LDI integrators, Bilinear SC integrators may be realized. They
correspond to the s-z mapping,
(29)
The circuit in Fig.5 is a stray-insensitive bilinear SC integrator. It requires a sample-and-held
circuit at the input and thus, two op-amps are necessary. Other simpler realizations are possible
but they are sensitive to parasitics. However, as we will see later, transfer functions obtained using
the bilinear transformation can be easily implemented with the simpler LDI integrators.
To know the degree of approximation achieved when using a particular type of integrator, it
is important to understand the difference in the frequency characteristics of the continuous-time
integrator and its discrete-time counterpart. For sinusoidal inputs, the continuous-time character-
istic results,
(30)
which means that the integrator has a phase shift of/2 for all frequencies and a magnitude equalto 1/wR1C2.
Makingz=ejwT (Tbeing the clock period) in the z-domain transfer functions of the previous
s2
T---z 1
z 1+-----------
_
+
2 2 (1)
1 1 (2)C1
C12
2 ( 1)
1 1 (2)
C2
11
CH
Vi Vi1
Fig. 5. Stray-insensitive inverting bilinear integrator (noninverting when clock phases in
parenthesis are used).
H jw( ) 1RC2----------
1
jw------=
8/3/2019 Notas Explicativas-Temas 3 y 4
11/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 11
integrators obtains the results summarized in Table 2. These results show that all SC integrators only
approximately simulate the continuous-time integrator. Both Euler and LDI integrators introduce a
magnitude error equal to |(wT/2)|sin(wT/2)|, while the deviation provoked by the bilinear integrator
is equal to|(wT/2)|tan(wT/2)|.
On the other hand, the integrator phase shift equals /2 (like the continuous time) in both theLDI and bilinear integrators, while an extra phase shift ofwT/2 exists for the Euler integrators. For-tunately this phase error is cancelled in some applications where a two integrator loop is used. How-
ever, maintaining a minimal magnitude error requires clocking the circuit with sufficiently high
frequency so that wT
8/3/2019 Notas Explicativas-Temas 3 y 4
12/20
12 Chapter 1 - Discrete-Time Applications
tinuous time integrator forR = T/C1, except for the excess of phase. This excess of phase is the
main cause of error in SC approximations where integrators are used to simulate reactive elements
from a passive prototype. Concretely, the integrator phase error is reflected in the Q of the element
being simulated. To illustrate this effect, let us consider the general continuous integrator transfer
function,
(33)
wherexi represents a generic element. Assuming
8/3/2019 Notas Explicativas-Temas 3 y 4
13/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 13
(39)
Thus, the damping term in the denominator is a function of frequency and the capacitor C3 also
contributes to alter the imaginary part. A constant damping factor results only for (wT/2)
8/3/2019 Notas Explicativas-Temas 3 y 4
14/20
14 Chapter 1 - Discrete-Time Applications
Use of this general block enables realization of different forms of integrator-summators for
special cases. For instance, if all input are connected to the same voltage source Vi, the following
transfer function results:
(41)
1.2.4 Synthesis and Design of SC FiltersDue to the sampled data nature of SC filters, their frequency response characteristics are described
in the discretez-domain. Consequently, the first step in the synthesis of SC filters is to find an
appropriate transfer function in the complex variablez, which meets certain frequency specifica-
tions. Direct approximation methods are seldom used to obtain this transfer function; instead, one
resorts to the experience and information (programs and tables) related to continuous filters. Thus,
in many practical applications the frequency requirements are specified in the continuous domain,
although they must be implemented using a sampled-data system. Methods to convert continuous
filters to sampled-data filters are commonly based on a mathematical s-z transformation. Given a
continuous transfer functionHA(s), a transfer functionHD(z) of the sampled-data system counter-
part is obtained by simply replacing s inHA(s) by some function
(42)
It is well known that to carry outHD(z), in addition to transferring the essential properties of
continuous systems to discrete systems, the following conditions must be imposed onf(z):
a)f(z) must be a rational function ofz. Hence, a rational functionHA(s) can be transformed into
a rational functionHD(z). Note that since HD(z) andHA(s) are basically different functions,
we use the subindexesD (discrete) andA (continuous) to distinguish them.
Vo z( )C1
C------
1
1 z1
----------------V1 z( )
C2
C------
z1
1 z1
----------------V2 z( )
C3
C------V3 z( )
C4
C------
1
1 z1
----------------V0 z( )+=
_
+
2 C4 2
1 1
2
V0
C3
V3
V1
2 1
1 1
C1
2 C2 1
V2
1 2
C
Fig. 7
Vo z( )
Vi z( )-------------
C1 C2z1
C3 1 z1
( )+
C 1 z1
( ) C4+-------------------------------------------------------------=
s f z( )=
8/3/2019 Notas Explicativas-Temas 3 y 4
15/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 15
b) The imaginary axis of the s-plane should be mapped onto the unit circle in thez-plane.
c) For |z|
8/3/2019 Notas Explicativas-Temas 3 y 4
16/20
16 Chapter 1 - Discrete-Time Applications
(45)
where Wa and Wddenote frequencies in the continuous and discrete domains, respectively.
Fig.8 shows the warping effects for a low-pass filter; we can see how the frequency axis is
altered. Consequently, the reference continuous filter corresponding to an LDI filter is more selec-
tive than that corresponding to a Bilinear realization. Thus, LDI realizations could require higher
order topologies than Bilinear realizations.
b)Impedance scaling.
In addition to the common use of scaling to increase the dynamic range and reduce element
spreads, the impedance scaling step must be included in some integrator-based topologies
to obtain realizable SC implementations. Detailed coverage of this point will be presented
when dealing with the design of LC ladder-based implementations.
Fig. 9 presents the two procedures for synthesizing SC filters. Details are given in the follow-
ing subsections.
1.2.5 Cascade realizationsSimilar to the case of an active RC filter, in the cascade approach the high order functionHD(z) is
factored into the product of first- and second-order functions.
(46)
Second-order functions, known as biquads, have the generic form
(47)
Wa2
T---
WdT
2-----------
tan=
a /T
3/T
2/T
2/T 3/T /T d
Bilinear.
L.D.I.
a=d
a2
T---
d2
------ tan=
a2
T---sin
d2
------ =
H(ja)For L.D.I. For BILINEAR.
2/T
sp p
d
p s
a
Fig. 8. Warping effects
HD z( ) Hi i( )
i 1=
N
=
Hi z( ) Kia
2 iz
2a
1iz a
0 i+ +
z2
b1iz b0 i+ +------------------------------------------=
8/3/2019 Notas Explicativas-Temas 3 y 4
17/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 17
The resulting functions are realized using integrators as building blocks, and are connected in
cascade in such a way that their product is the wastedHD(z).
The cascade design is very popular mainly due to the following:
- Any low-pass, band-pass, and high-pass filter function can be realized by the cascade method.
- Different and easy-to-design SC biquad topologies can be efficiently used.- It results in easy-to-tune filters because their critical frequencies are performed individually by
each biquad.
Frequency specifications.
Choose s-z transform. Prewarping.
Obtain HA(s).
HA s( )
Nj s( )j
Dj s( )j
---------------------= Obtain LC prototype.
* Pole-zero pairing.* Cascading sequence.* Gain distribution.
HA s( ) Hi s( )i
=
Generate signed flowGraph (SFG)
Convert SFG to a SCnetwork.
Hi s( ) Hi z( )
Use of universal SC biquadtopology to implement eachHi(z).
Evaluate capacitor ratios.
Scaling for maximumdynamic range.
- Scaling the first design.- Choose capacitance values.
Connect all biquads.Adjust capacitance value
for minimum total area.
SC filter SC filter
Cascade approach. LC ladder simulation
Fig. 9.
8/3/2019 Notas Explicativas-Temas 3 y 4
18/20
18 Chapter 1 - Discrete-Time Applications
The main drawback of the cascade approach is that the resulting implementations are more
sensitive to component variations than the ladder simulation approach.
The systematic procedure for the design of cascaded SC filters is fundamentally the same as
that for RC filters, and hence it is sufficiently well known so as not to be included in this section.
As shown in Fig.9, after prewarping the frequency specifications, all the synthesis is carried out
in the continuous domain; thus, the pole-zero pair assignment, cascading sequence, and gain dis-
tribution for the biquads used are handled in the variable s. All we require for the SC design is the
way the function Hi(s) are transformed into Hi(z), and how these z-domain biquads are imple-
mented.
The building blocks for cascade realizations are biquads implementing the biquadratic func-
tions.
(48)
which are obtained from biquadraticH(s) functions by an s-z transformation. We will assume in
the following that this transformation is the exact bilinear mapping.
For the SC realization ofH(z) a family of SC biquad building blocks has been proposed [Flus79]
whose transfer function resembles (49). The schematic of this general topology is shown in Fig.11.
It consists of a loop of two general first-order building blocks like that shown in Fig.7. Sampling
Vi in 1 and maintaining it for the full period T, results in the following twoz-domain transfer func-tions,
(49)
(50)
The main features of this topology are:
a) Two output available, V1 and V2.
b) Provide the capability of realizing all stablez-biquadratic functions. The denominator is
determined by the capacitors in the loop (A, B, C, D, E, F) and the numerator, by the feed-in capacitors (G, H, I, J, K, L).
c) Provide enough flexibility for dynamic range optimization and scaling for minimum total
capacitance. To this respect, note that capacitors A and D can be replaced by nA and nD,
respectively, reducing the signal level ofV1 by the factor n while not altering the level of
V2. On the other hand, replacing capacitors B, C, F, and E by capacitors B/n, C/n, F/n, and
E/n respectively, an increase ofV2 in a factor ofn results without changing V1.
d) Capacitor E and F in the feedback paths are redundant both providing a means for clamping
the poles. This redundancy is eliminated in practical cases where one E or F is set to zero.
Hence, two cases of circuits are available, the so-called E-circuit where F = 0, and the F-
circuit where E = 0.
In sum, the general circuit in Fig.10 with 12 capacitors (or 11) gives the designer sufficientfreedom to realize any set of 6 parameters (a2, a1, a0, b1, b0, k) in (49), achieving an acceptable
compromise between minimum total capacitance and sensitivity.
H z( ) ka2z
2a1z a0+ +
z2
b1z b0+ +
-------------------------------------=
H1 z( )V1 z( )
Vi z( )
-------------zC E z 1( )+[ ] zI J k z 1( )+[ ] zF B z 1( )+[ ] zG H L z 1( )+[ ]
A zC E z 1( )+[ ] D z 1( ) zF B z 1( )+[ ]+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= =
H2 z( )V2 z( )
Vi z( )-------------
zC E z 1( )+[ ] zI J k z 1( )+[ ] zF B z 1( )+[ ] zG H L z 1( )+[ ]A zC E z 1( )+[ ] D z 1( ) zF B z 1( )+[ ]+
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -== =
8/3/2019 Notas Explicativas-Temas 3 y 4
19/20
Section 1.2 - Description of SC Circuits in the Time and Frequency Domains 19
Some guidelines for simple and good designs are given in [Flus79]. For instance, setting K = L
= 0 reduces the number of switches through switch sharing; this schematic is shown in Fig.11. In
addition, for a first design B, D, and A can be normalized to unity, resulting in the two functions,
(51)
(52)
Now, an evident salient feature ofH2 is that poles and zeros can be adjusted independently. This
fact is not determinant for the choice ofH2 instead ofH1, and other features like sensitivity and min-
imum area ..... do preferable the functionH1.
Once the initial design is complete, the stages may be properly scaled for both appropriate sig-nal level and minimum total capacitances. This later scaling is realized in the groups of capacitors
connected to the virtual ground of each op-amp. First, the smallest capacitancex1 of a group is made
equal to the smallest value allowed by the technology (Cmin); then, all the capacitors in the group are
multiplied by k= Cmin/xi.
The advantages for usingH1 orH2, as well as E or F circuits are not clear. Designers usually
prefer to useH2 in (53). However, choosing E-circuits (F = 0) for high-Q designs and F-circuits (E
= 0) for low-Q designs yields less capacitance spread (ratio of maximum to minimum capacitances).
_
+
_+
L 1 C 1
2 2
E
1 G 1
2 2
2 H 1
1 2
K
D
1 F 1
2 2
B
1
v2vi
1 I 1
2 2
2 J 1
1 2
2 A 1
1 2v1
Fig. 10. Stray-insensitive generic SC biquad circuit
H1
V1
Vin-------
IC IE FG G+( )z2
FH H JC JE IE+( )z EJ H ( )+ +
1 F+( )z2
C E F 2+( )z 1 E( )+ +--------------------------------------------------------------------------------------------------------------------------------------------------------= =
H2
V2
Vin-------
Jz2
G I J( )z J H ( )+ +
1 F+( )z2
C E F 2+( )z 1 E( )+ +---------------------------------------------------------------------------------------------= =
8/3/2019 Notas Explicativas-Temas 3 y 4
20/20
20 Chapter 1 - Discrete-Time Applications
_
+
_
+
C
E
D
2 A
1v1
F 1
B
2
2
v2
I
F
1 G
2
2 H
1
vi
1
2
1
Fig. 11.Alternative generic SC biquad circuit.
Note: Choose F = 0 for high-Q biquads: E = 0 for low-Q biquads.