Novel High-Q MEMS Curled-Plate Variable Capacitors Fabricated in 0.35-μm CMOS Technology

530 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 2, FEBRUARY 2008

Novel High-Q MEMS Curled-Plate VariableCapacitors Fabricated in 0.35-�m CMOS TechnologyMaher Bakri-Kassem, Member, IEEE, Siamak Fouladi, Student Member, IEEE, and Raafat R. Mansour, Fellow, IEEE

Abstract—Two microelectromechanical systems (MEMS)curled-plate variable capacitors, built in 0.35- m CMOS tech-nology, are presented. The plates of the presented capacitors areintentionally curled upward to control the tuning performance.A newly developed maskless post-processing technique that isappropriate for MEMS/CMOS circuits is also presented. Thistechnique consists of dry- and wet-etching steps and is developedto implement the proposed MEMS variable capacitors in CMOStechnology. The capacitors are simulated mechanically by usingthe finite-element method in ANSYS, and the results are comparedwith the measured results. Two novel structures are presented.The first capacitor is a tri-state structure that exhibits a measuredtuning range of 460% at 1 GHz with a flat capacitance responsethat is superior to that of conventional digital capacitors. Theproposed capacitor is simulated in Ansoft’s High FrequencyStructure Simulator (HFSS) and the capacitance extracted is com-pared with the measured capacitance over a frequency range of1–5 GHz. The second capacitor is an analog continuous structurethat demonstrates a measured continuous tuning range of 115%at 1 GHz with no pull-in. The measured quality factor is betterthan 300 at 1.5 GHz. The proposed curled-plate capacitors have asmall area and can be realized to build a system-on-chip.

Index Terms—CMOS microelectromechanical systems (MEMS)integration, MEMS, MEMS varactor, post-processing, RF inte-grated circuits (RFICs), variable capacitor.

I. INTRODUCTION

THE fabrication of microelectromechanical systems(MEMS) devices in commercially available CMOS

technology, with a minimum feature size of a few hundrednanometers, can push MEMS technology to higher integration.It improves performance of RF integrated circuits (RFICs) andresults in the elimination of bulky off-chip components.

MEMS variable capacitors can be used as tuning elementsin several RF systems, such as voltage-controlled oscillators(VCOs), tunable filters, and impedance-matching networks.Their size and RF response significantly affect the performance

Manuscript received April 12, 2007; revised September 7, 2007. This workwas supported in part by the Natural Science and Engineering Research Council(NSERC) of Canada and by COM DEV.

M. Bakri-Kassem was with the Center for Integrated RF Engineering(CIRFE), Department of Electrical and Computer Engineering, University ofWaterloo, Waterloo, ON, Canada N2L 3G1. He is now with the Research andDevelopment Department, Custom Products Business Unit, MEMSCAP Inc.,Durham, NC 27703 USA (e-mail: [email protected]).

S. Fouladi and R. R. Mansour are with the Center for Integrated RF Engi-neering (CIRFE), Electrical and Computer Engineering Department, Universityof Waterloo, Waterloo, ON, Canada N2L 3G1 (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2007.914657

of the system. Recently, several MEMS variable capacitors havebeen reported with different structures and fabrication tech-nologies [1]–[9]. These capacitors are classified as either lateralinterdigital or parallel-plate capacitors. Lateral interdigitalMEMS capacitors demonstrate a better linear tuning charac-teristic than parallel-plate capacitors, whereas parallel-platecapacitors exhibit a higher quality factor and lower parasiticinductance.

Lateral MEMS variable capacitors, fabricated of single crys-talline silicon in silicon-on-insulator (SOI) technology and in-terconnect layers in CMOS technology, have been described in[2] and [8], respectively. These capacitors exhibit a low qualityfactor and a low self-resonance frequency and occupy a rela-tively large area.

Parallel-plate capacitors are simple to fabricate and can bedesigned for higher capacitance values with a smaller area [7],[10]. In this paper, novel MEMS/CMOS curled-plate variablecapacitors for RF and microwave applications are presented.These capacitors are manufactured in 0.35- m CMOS tech-nology from the Taiwan Semiconductor Manufacturing Com-pany (TSMC), Taipei, Taiwan, R.O.C., and then post-processedby optimizing the technique presented in [11]. The advantageof choosing CMOS is that MEMS capacitors can be monolith-ically integrated with active CMOS devices on the same chipto exploit their higher quality factor, smaller area, and higherself-resonance frequency to create highly integrated RFICs. Thetwo novel structures proposed in this paper have the potential toreplace conventional digital and analog continuous capacitors,especially for circuits designed in CMOS technology.

II. DESIGNED CAPACITORS

The new curled-plate MEMS variable capacitors are fab-ricated in 0.35- m CMOS technology. The capacitors arebuilt by using metal interconnect layers shown in Fig. 1.Four metal layers and two polysilicon layers are availablethrough this CMOS technology. The top metal layer, metal #4,serves as a mask in the first dry-etching stage in the proposedpost-processing technique. The top and bottom plates of theparallel-plate capacitors consists of metal #3 and metal #1layers, respectively. Metal #2 is offered as a sacrificial layerto create an air gap between the capacitor’s plates. With thisapproach, the total distance between the top and bottom platesis typically 2.64 m, including 1 m of oxide on both platesand a 0.64- m air gap. The oxide dielectric layers prevent thecapacitor from short circuiting when the two plates touch eachother.

In this paper, two structures of capacitors, based on a newlydesigned spring system and curl action due to residual stress, are

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BAKRI-KASSEM et al.: NOVEL HIGH- MEMS CURLED-PLATE VARIABLE CAPACITORS 531

Fig. 1. Cross-sectional view of the layer stack in 0.35-�m CMOS technologyfrom TSMC.

Fig. 2. 2-D layout of the tri-state type capacitor built in L-edit.

proposed. The top plate of the capacitor consists of two layers,one on top of the other. The oxide layer of the top plate is foundto be 0.65- m thick and reveals compressive stress, whereas thetop layer of the top plate is aluminum and has a tensile stress[12]. Both the top and bottom plates of the capacitors are mov-able. However, unlike the two movable plate capacitors in [3],the proposed capacitors are integrated monolithically in a com-mercially available CMOS technology, and their plates are in-tentionally curled upward to control the capacitors’ tuning per-formance.

A. Tri-State Curled-Plate Capacitor Design

The first capacitor is a tri-state-type capacitor, composed ofan eight-beam spring system with four beams for the top plateand four beams for the bottom plate. These are called the mainbeams. Fig. 2 denotes a top view of the tri-state capacitor. Thesemain beams function not only as electrical paths for the RFsignal, but also as mechanical supports that control the curl up ofthe plates (see Fig. 2). The beams force both plates to adopt dif-ferent curvatures because the beams pull the plates down at thecontact points opposing the moment induced from the residualstress. As a result, both plates display nonuniform curvaturesthat are divided into four top sections and four bottom sections,as depicted in Fig. 3. The schematic diagram of the tri-state ca-pacitor can be understood by looking at the cross sectionin Fig. 2. In Fig. 3, the top sections and exhibit dif-ferent curvatures than those of and . The bottom sec-tions and show different curvatures than the bottom

Fig. 3. Schematic diagram of the novel tri-state capacitor.

Fig. 4. Schematic diagram of the proposed tri-state capacitor showing the threemain states. (a) Capacitor at zero dc-bias voltage. (b) Capacitor after the firstcollapse point. (c) Capacitor after the second collapse point.

sections and . The bottom plate curvatures are rela-tively smaller than the top plate curvatures due to the thickeroxide layer.

As illustrated in Fig. 3, each top plate and each bottom plateconsists of four sections with two different curvatures. Bothplates of the capacitor touch each other at the initial state, wherethe dc-bias voltage is zero (first capacitance level). After thefirst collapse voltage, the second state, and that dis-play a radius of curvature of , collapse on their overlappingsections, and , which have a radius of curvature of

(second capacitance level). At the third state, and ,which have a radius of curvature of , collapse on and

of the bottom plate, which have a radius of curvature of, when the second collapse voltage is attained (third capaci-

tance level). Fig. 4 is a schematic diagram for the three previousstates of the proposed tri-state capacitor. Fig. 4(a) is a schematicdiagram of the new capacitor at the initial state at zero dc-biasvoltage. Fig. 4(b) depicts the capacitor after and col-lapse on and , and Fig. 4(c) shows the capacitor after

and collapse on and . The fact that the mainbeams prevent the top and bottom plates from curling up andhaving a uniform curvature causes the capacitor to collapse intwo steps. This occurs because and overlaps and


Fig. 5. 2-D layout of the proposed curled continuous MEMS/CMOS variablecapacitor built in L-edit.

Fig. 6. Schematic diagram of the proposed curled continuous MEMS/CMOSvariable capacitor.

undergo a higher restoring force than that of andthat overlaps and . The difference in the restoring forceprevents top sections, and , from collapsing on bottomsections, and , until a dc-bias voltage is increased anda second collapse voltage point is achieved.

B. Analog Continuous Curled-Plate Capacitor Design

The second proposed capacitor, a continuous capacitor, haseight main beams and eight additional corner beams that me-chanically connect the top and bottom plates of the capacitor tothe silicon substrate. These long and narrow corner beams do notcontribute a meaningful spring constant in the transverse direc-tion; however, they do portray the high restoring forces in plane,where the corner beams attempt to prevent the top and bottomplates from curling up as high as the ones in the novel tri-statecapacitor. Fig. 5 illustrates the layout of the continuous capac-itor. The 16-beam spring system that is connected to both platesof the continuous capacitor is shown in this figure. A schematicdiagram of the second proposed capacitor is illustrated in Fig. 6.For this capacitor, the corner beams can control the curl of bothplates from deflecting too far from one another. The equiva-lent restoring force of these deflected beams, caused by the mo-ment induced from the residual stresses, results in a nonlinearrestoring force that opposes the nonlinear electrostatic force,generated by the dc-bias voltage in parallel-plate capacitors.

III. POST-PROCESSING AND FABRICATION

OF THE PROPOSED CAPACITORS

A maskless post-processing technique is used to releasethe MEMS curled-plate capacitors. This technique consists ofthree stages, i.e.: 1) dry etching; 2) wet etching; and lastly; 3)dry etching. The first stage is the same as that in the dry etchingin [13] for a lateral interdigitated capacitor. In this paper, theaddition of a wet-etching stage and a final dry-etching stageare proposed to realize the curled-plate capacitors. In thistechnique, the objective is to etch the sacrificial layer, whichis metal #2, create a deep trench in the substrate, decreasethe thickness of each oxide layer, etch away the mask layer,metal #4, and finally, expose the RF pads and the top capacitorplate metal layer #3.

The process is developed to integrate the novel MEMScurled-plate capacitors with RFICs that can be implemented inCMOS technology. A schematic view of the post-processingstages is presented in Fig. 7. The first dry-etching stage consistsof three steps, which are as follows.

Step 1) Anisotropic etching of the silicon oxide by using re-active ion etching (RIE) with CHF and O plasma.

Step 2) Anisotropic etching of the silicon substrate by em-ploying deep reactive ion etching (DRIE) with SFand O .

Step 3) Isotropic etching of the silicon substrate by usingSF and O [13].

The first dry-etching stage that involves the removal of the sil-icon oxide and silicon substrate, around the MEMS structure,is signified in Fig. 7(b). Since the wet etchants are not selec-tive regarding silicon and aluminum, it is critical to keep anoxide layer around the structural metal layers (metal #1 andmetal #3) to protect the aluminum from being etched by the wetetchants. This is accomplished by extending metal #4 over thetop of the structural metal layers. Therefore, metal #2, whichmust be exposed after the RIE step, should be extended beyondmetal #4 layer. As shown in the cross-sectional view of the newcapacitor in Fig. 7, metal #4 extends over metal #1 and metal#3 by 2 m, an extension sufficient to protect the capacitor’stwo plates from being exposed to nonideal anisotropic etching.Table I lists the parameters and etch recipe for the first and thirddry-etching stages. The measured anisotropic etch rate of oxideis 670 Å/min. Fig. 8(a) reflects an SEM image of the capacitorafter the anisotropic dry-etching step of oxide. The substrateis then etched by using anisotropic dry etching, isotropic dryetching, and wet etching. Fig. 8(b) displays the chip after the wetetching of the aluminum and silicon substrate. The wet etchingachieves the following six objectives simultaneously:

1) releases the top plate of the variable capacitor from thebottom plate;

2) etching away the mask layer (metal #4);3) etching away the lossy silicon substrate underneath the ca-

pacitor, which releases the bottom plate;4) cleans the trench underneath the released structure by

etching away the remaining piles of silicon, left after theisotropic dry etching, as shown in Fig. 9 and resulting,of course, in a deeper trench in the silicon substrate,compared with using dry etching alone;


Fig. 7. Post-processing steps for the new technique of RF MEMS/CMOS inte-grated circuits. (a) Chip after being fabricated and delivered. (b) After the firstdry etching (stage #1) that includes the anisotropic etching of oxide, anisotropic,and isotropic on the silicon substrate. (c) After the wet etching (stage #2) thatconsists of isotropic etching of aluminum and anisotropic etching of silicon.(d) After the second dry etching (stage #3).

TABLE IDRY-ETCHING STEPS

5) eliminates the under-etching of the silicon substrate under-neath the electronic circuits for the same trench depth;

6) decreases the thickness of the oxide layers, resulting inlower equivalent stiffness, in order to reduce the actuationvoltage between the top and bottom plates and enhance thecurl up.

Fig. 8. SEM image of the capacitor. (a) After dry etching of oxide, before wetetching, and (b) after wet etching of aluminum.

Fig. 9. Capacitor after the first dry-etching stage.

The combination of wet and dry etching of the silicon sub-strate in the proposed post-processing technique is more desir-able than dry etching alone [13] or wet etching alone [11]. Thecombination requires the same safety distance the dry etchingneeds from the electronics, and creates a deeper trench causedby the wet etching, at least 2.5 times deeper than previouslypublished techniques [11], [13], improving RF performance.Fig. 7(c) is a schematic diagram of the released capacitor afterthe first dry- and wet-etching stages. The top plate of the variablecapacitor is released by etching the exposed sacrificial metallayer, which, in this case, is metal #2, as signified in Fig. 7(c).The lossy silicon substrate is etched to improve the quality factorand, in turn, enhancing the RF performance.

Etching away the mask layer (metal #4) is a vital step forthe new technique because the etching eliminates the huge par-asitic capacitance that might be induced in the other three in-terconnect metal layers and metal #4. The wet-etching stage isconducted by a phosphoric-acetic-nitric (PAN) acids etch for40 min at 60 C to etch the aluminum. To etch the adhesionlayer, a sulfuric acid H SO H O etch for 30 min at 60 Cis sufficient. Finally, potassium hydroxide (KOH) is applied for10 min at 80 C at a silicon etching rate of 8.33 m/min [14]and an oxide etching rate of 38 nm/min [15]. The new technique


TABLE IIWET-ETCHING RECIPES

allows a slight etching of the oxide layer that protects the metallayer. Tetra methyl ammonium hydroxide (TMAH) is then usedfor 85 min at 90 C to continue etching the silicon substrate.The wet-etching stage is summarized in Table II.

Etching away the encapsulating oxide layers results in thinneroxide layers, enhancing the curl up of the top and bottom plates,decreasing the total equivalent stiffness, and lowering the actu-ation voltage. The measured oxide layer after the KOH etchingis 0.65 m, indicating that the KOH etched away 0.45 m fromthe oxide. TMAH etches the and silicon planes andstops at the plane. The concentration of TMAH used at90 C leads to an etch rate of 0.25 m/min.

After 95 min of wet etching in KOH and TMAH, the totalmeasured depth of the trench is more than 125 m. Releaseholes are required to etch the sacrificial metal layer and etchthrough the silicon substrate so that the lossy silicon substrateunderneath can be etched in a shorter period of time. These re-lease holes are created in the metal #4 and metal #2 mask layers,shrinking metal #3 and metal #1, and extending metal #2 fartheroutward, as shown in Fig. 7. Now, the top and bottom platesare readily released without affecting the buffer distance for theelectronics on the chip. Moreover, the wet-etching stage allowsus to release the proposed capacitors with fewer release holes.The size of the hole in metal #2 is 5 m, and the spacing be-tween two adjacent holes is 20 m.

IV. SIMULATIONS AND MEASURED RESULTS

OF THE CURLED-PLATE CAPACITORS

In the proposed process, the maximum curl up of the MEMS/CMOS capacitors is controlled as follows:

1) location and number of springs in the design of capacitorsthat control the curling of the aluminum and oxide layers;

2) temperature these devices are exposed to during the post-processing stages;

3) combination of the different layers of materials used tobuild the plates of the capacitor.

For example, the bottom plate consists of an oxide–alu-minum–oxide tri-layer that demonstrates less curling than thetop plate, which is a bi-layer of aluminum–oxide.

A. Tri-State Curled-Plate Variable Capacitor Analysis

For the proposed tri-state capacitor, both plates touch eachother at zero dc-bias voltage. After the dc-bias voltage is ap-plied, the plates begin to relax on each other without any sig-nificant change in capacitance despite their minimal overlap-ping areas. Fig. 10 shows a schematic diagram of half of the

Fig. 10. Schematic diagram of half of the proposed tri-state capacitor with theapplied symmetry line.

Fig. 11. Quarter of the tri-state capacitor for both the top and bottom platesafter applying the two symmetry lines.

tri-state capacitor after the symmetrical boundary is applied.The new tri-state capacitor is simulated in ANSYS. The ca-pacitor’s model is simplified by applying two symmetries onone-quarter of the capacitor, as depicted in Fig. 11. The nota-tions and dimensions of the curled sections are also reflected inFig. 11. The curled sections collapse down step by step at thecenter of their curvatures, and because of their warpedshapes, as illustrated in Figs. 10 and 11. This is due to the stiff-ness of the main beams that causes the difference in curvature inthe different curled sections. These beams are tilted 45 in-planeto impose a force in the direction of the beam , as conveyedin Fig. 11, at the contact points with the plates when the platescurl up due to the induced moment by the residual stress. Thesebeams also create bending moments as a reaction at the contactpoints with the plates that oppose the direction of the moment inthe top and bottom plates. The main equivalent force from thisbending moment is a vertical force that is applied at the contactpoints with the plates. As a result of this vertical force, nonuni-form curvature is created in the top and bottom plates.

Fig. 12 represents the SEM photography of the tri-state capac-itor. The capacitor is analyzed by surface optical profilometer(Veeco) software, and its measured -axis profile is obtained.The measured maximum curl up of the top plate for the tri-state


Fig. 12. SEM photograph of the fabricated tri-state capacitor.

Fig. 13. Measured profile of the curl up in the capacitor. (a) Top view of thetri-state capacitor. (b) 2-D profile of the tri-state capacitor.

capacitor is almost 42.7 m, as illustrated in Fig. 13. The max-imum simulated curl up at zero dc-bias voltage, obtained usingfit to measured curl-up data in ANSYS, is 42 m. From the di-rection of the measured curl up, the net stress is a tensile stress,caused by the aluminum layer [16].

To verify the measured results, the tri-state capacitor is thensimulated in ANSYS using a dc-bias voltage range from 0to 60 V. The used Young’s modulus for aluminum and oxideare 49 and 56 GPa, respectively [17]. Both plates, the top andthe bottom, attract each other due to the applied electrostaticforce. Fig. 14 denotes the simulated displacement for thetri-state capacitor at four voltages. The simulated displacementresults for the tri-state capacitor demonstrate that the firstcollapse occurs between 42–44 V, and the second collapseoccurs between 54–56 V. The extracted displacement and the

Fig. 14. Simulated displacement results of the 3-D structure of the proposedtri-state capacitor obtained in ANSYS, showing the four main positions.(a) Capacitor at 42 V before the first collapse point. (b) Capacitor at 44 V afterthe first collapse point. (c) Capacitor at 54 V before the second collapse point.(d) Capacitor at 56 V after the second collapse point.

dc-bias voltages for the locations and in the top andbottom plates (see Fig. 11) are illustrated in Fig. 15(a) and (b)in a range of 28–70 V, respectively. Fig. 15(a) illustrates themaximum displacement before collapse on at thelocation . Fig. 15(b) reveals that the location on bothplates exhibits two different points of collapse. To model thetri-state curled-plate capacitor, a technique, derived from themethod of moments, is developed to theoretically simulate thecapacitance between the two plates of the capacitor [17]. InFig. 16, it is assumed that the top and bottom plate areas aredivided into subareas where the top and bottom plates havesubareas. The capacitance is then calculated by implementingthe simulated displacement results obtained in ANSYS, asshown in Fig. 15(a) and (b) in the newly developed method ofmoments model. Due to the oxide layers, the equivalent dielec-tric constant [18] at each subarea is used to obtain the simulatedcapacitance. This capacitance and capacitance extracted fromthe measurement results, after deembedding the RF testingpads at 1 GHz, are plotted in Fig. 17. The measurement andsimulated capacitance are in good agreement. The differencebetween the extracted simulated and measured capacitance isdue to the nonideal collapse at the edges of the plates, and thefact that the method of moments does not include the RF effectand release holes. The extracted measured self-resonance ofthe tri-state capacitor is better than 20 GHz at a dc-bias voltageof 70 V.

After the post-processing technique and the release process,the capacitors are placed in a CO critical point drying systemto avoid surface stiction. The residual stress forces the top andthe bottom plates to curl upward because of the net tensilestress [12], [19], [20], while the main beams attempt to opposethis moment at the contact points. This action increases theradius of curvature and compared with that of and

, respectively, for the top and bottom plates of the tri-statecapacitor.


Fig. 15. Extracted simulated displacement response of the proposed tri-statecapacitor in ANSYS model. (a) Extracted simulated results at location P .(b) Extracted simulated results at location P .

Fig. 16. Schematic diagram of the MEMS variable capacitor being divided intosubareas for both plates.

The advantage of using curled-plate sections that collapse atdifferent voltages is that the sections provide a compact struc-ture that has a higher self-resonance, higher quality factor, and

Fig. 17. Simulated capacitance of the proposed tri-state capacitor using themethod of moments based on the displacement results obtained in ANSYS andthe measured tuning response of the fabricated tri-state type curled plate capac-itor at 1 GHz.

less capacitance variation than those of conventional digital ca-pacitors. This occurs because no narrow beams are needed forthe arrays of capacitors.

The conventional digital capacitor, reported in [9] and [21],yields a continuous performance. The modified version of [21],as described in [4], includes larger plates. However, the beamsare narrow for their arrays of capacitors [2], [4], [21]. The 50%maximum tuning range of these plates of the conventional dig-ital capacitor in [4] leads to a measured capacitance variationof 28%, 36%, and 20% for the first, second, and third capaci-tance levels, respectively. This is due to the effect of the dc-biasvoltage on the other capacitors that should not deform.

The proposed tri-state capacitor exhibits three stable capac-itance ranges based on the novel integrated mechanical tuningsystem that functions according to the applied dc-bias voltages.As illustrated in Fig. 17, a measured maximum capacitance vari-ation of 9% is obtained at the second capacitance level. The firstcapacitance level has a variation of 7% over a dc-bias voltagerange of 0–42 V, the second capacitance level has a variationof 9% over a dc-bias voltage of 46–58 V, and the third capaci-tance level has a variation of 5% over a dc-bias voltage range of60–70 V. The tri-state capacitor exhibits a flatter response andbetter variation than conventional digital capacitors, as shown inFig. 17. The capacitor’s hysteresis is not measured at this stage,but, it might slightly shift the measured response in the voltageaxis. This should not affect the maximum variation. The tri-statecapacitor is compact with an area of only 500 m 500 m.

The maximum deflection of the tip of a curled cantilever be-fore collapse with a fixed bottom electrode is reported to be 33%[22] of the total distance between the free end tip and bottomelectrode. The maximum reported capacitance change at thepull-in voltage for a conventional curled cantilever beam is also20% [23]. In conclusion, the curled beams have fewer capaci-tive variations compared with unstressed beams. However, thetri-state capacitor has capacitive variations that are at least 50%less than those of conventional curled beams. This value resultsin 75% less variation than that of conventional digital capacitors[4].


Fig. 18. Proposed capacitor simulated in HFSS. (a) Capacitor after being de-flected due to the residual stress before applying dc-bias (first state). (b) Simu-lated capacitor after the first collapse point (second state).

The analytical model for the conventional curled structure in[24] assumes a curled cantilever on top of a fixed electrode. Theanalyses in [22]–[24] are not applicable to the proposed structuresince each plate curls up with two different curvatures and theplatesattracteachothersuchthat thetopplatedeformsdownward,while the bottom plate deforms upward. Moreover, the sectionsof both plates that touch result in vertical movement, whereas theconventional cantilever is anchored at the corresponding end.

To study the capacitance extracted at high frequencies, thetri-state capacitor is built in Ansoft’s High Frequency StructureSimulator (HFSS), as reflected in Fig. 18. Three HFSS simula-tions are carried out. The first simulation is for the first state ofthe tri-state capacitor in which the two plates slightly touch eachother in the initial position at zero dc-bias voltage. In the secondsimulation, and collapse on and due to theapplied dc-bias voltage that exceeds the first collapse point. Inthe third simulation, the entire top plate collapses on the bottomplate.

Fig. 18 shows the 3-D structures of the proposed tri-state ca-pacitor for the zero dc-bias voltage and after the first collapsevoltage. In all the HFSS simulations, the RF pads are excluded,and the trench in the silicon substrate is included. The one-portnetwork topology is adapted to extract the capacitance from the

-parameters simulated in HFSS. Fig. 19 provides a comparisonbetween the extracted capacitance from HFSS and the extractedcapacitance from the measurements. The results of the extractedcapacitances from HFSS are in good agreement with the mea-surements for the zero dc-bias voltage and the 46-V dc-biasvoltage. The error is 34% at 5 GHz for a dc-bias voltage of70 V. This error is due to the remaining oxide in the release holesunder the mask layer metal #4 and the sacrificial layer metal #2.This oxide causes higher fringing field at higher frequency dueto the higher dielectric constant of the oxide in comparison withair.

Fig. 19. Comparison between the simulated capacitances in HFSS and the mea-sured capacitance from 1 GHz up to 5 GHz for the tri-state capacitor.

B. Analog Continuous Curled-Plate VariableCapacitor Analysis

The analog continuous capacitor in Fig. 5 has corner beams,which are relatively low in their spring constants in the trans-verse direction, connecting the corners of the capacitor to thesubstrate. The existence of these corner beams prevents the topand bottom plates from curling up too high and moving awayfrom each other.

The capability of these corner beams to limit the plates of theanalog continuous capacitor from curling upward to the sameheight as that of the tri-state capacitor induces high stress in thecorner beams’ axial directions. However, the corner beams arethinner than the main beams to allow the corners of the capac-itor to curl upward relatively more than the curl up at the con-tact points of the main beams. This facilitates the creation of anonlinear equivalent spring constant in both the top and bottomplates that results in a nonlinear restoring force. This force op-poses the induced nonlinear electrostatic force from the applieddc-bias voltage, and as a result, deforms both plates without dis-continuities from collapsing.

Fig. 20 presents a top view of the schematic diagram ofone-quarter of the analog continuous capacitor. The in-planerestoring force from the corner beam axial direction is decom-posed to two forces in the guided beams [25]. and arethe projections of the force caused by the corner narrow beam,whereas and are the projections of the force caused bythe main wide beam. To measure the initial curl up of the analogcontinuous capacitor, an optical surface profilometer (Veeco) isused. Fig. 21 shows an SEM photograph of the analog contin-uous capacitor. Fig. 22 provides the 2-D profile. The maximumcurl up between the edges of the top plate and the center of thecapacitor is measured by the surface profilometer and found tobe 15.8 m, as depicted in Fig. 22.

In addition, the proposed analog continuous capacitor is sim-ulated in ANSYS. The portion of the capacitor in Fig. 20 is usedafter two symmetry lines are applied. The maximum simulatedcurl up uses a fit to measured curl-up data in ANSYS, which oc-curs at the location , is found to be 14.51 m at zero dc-biasvoltage. The maximum simulated curl up of the hidden bottomplate of the capacitor is then obtained from ANSYS and found


Fig. 20. Top view of a schematic diagram of one-quarter of the curled analogcontinuous capacitor for both plates, top and bottom, illustrating the inducedtensile force.

Fig. 21. SEM photograph of the fabricated curled analog continuous capacitor.

to be 5.8 m at the location as well. Due to the oxide–alu-minum–oxide tri-layer, there is less curl up in the bottom plate.The capacitor is simulated over a dc-bias range from 0 to 70 V.Fig. 23 illustrates the 3-D results at four different dc-bias volt-ages. The simulated results of the displacement in ANSYS, inrelation to the dc-bias voltage of the location for the area(see Fig. 20) are shown in Fig. 24(a). A small area of the analogcontinuous capacitor on Fig. 20 indicates a jump in displace-ment at 46 V, as shown in Fig. 24(b). This jump occurs becauseof and its symmetrical force from the vertical symmetry line,causing these sections of the capacitor to collapse, as a cause ofbuckling, on each other and cause a capacitance jump [16]. It isclear from the simulated results for the displacement versus dcbias that both plates move toward each other.

The extracted measured capacitance at 1 GHz and the theoret-ically simulated capacitance of the method of moments modelover a dc-bias voltage from 0 up to 70 V is illustrated in Fig. 25.The measurement indicates that the capacitor changes its slopeat 44 V, due to the small jump in area for both plates. Thecapacitance extracted from the measurement over a frequency

Fig. 22. Measured profile of the curl up in the capacitor. (a) Top view of thecurled analog continuous capacitor. (b) 2-D profile of the of the Y - andX-axisof the capacitor.

Fig. 23. 3-D displacement results of the proposed curled analog continuouscapacitor showing four obtained results. (a) Capacitor at zero dc-bias voltage.(b) Capacitor at a 36 dc-bias voltage. (c) Capacitor at 52 dc-bias voltage.(d) Capacitor at 70 dc-bias voltage.

range of 1–5 GHz is plotted in Fig. 26. The proposed analog con-tinuous capacitor demonstrates a continuous tuning response fortwo ranges of the measurements; the first is from 18 to 42 V andthe second range is from 42 to 52 V.

Unlike the conventional capacitor that is reported in [11],which has a 50% tuning range before the pull-in, the proposedanalog continuous capacitor is not prone to the pull-in voltagebecause of the following two reason. The top plate is alreadytouching the bottom plate with an area (see Fig. 20). Thecontact is due to the initial curling upward, initiated by the


Fig. 24. Simulated displacement versus dc-bias voltage of the curled analogcontinuous capacitor obtained in ANSYS. (a) Displacement results for bothplates of location P that is shown in Fig. 20. (b) Displacement results for bothplates at location P shown in Fig. 20.

Fig. 25. Measured tuning response of the fabricated analog continuous curled-plate capacitor at 1 GHz and the simulated tuning response using the method ofmoments model.

residual stress on both plates, and the equivalent restoring forcefor the spring constant system is nonlinear due to the existenceof the residual stress, corner beams, and main beams.

Fig. 26. Measured extracted capacitance of the curled-plate analog continuousMEMS/CMOS variable capacitor from zero dc-bias voltage up to 52 dc-biasvoltage for a frequency from 1 up to 5 GHz.

Fig. 27. Measured S of the tri-state and the analog continuous MEMS var-actors before deembedding the RF pads.

Fig. 28. Measured quality factor of the proposed analog continuous and tri-state MEMS/CMOS variable capacitors at zero dc-bias voltage and 52 dc-biasvoltage, respectively.

The measured quality factor of the capacitors is extractedfrom the -parameters that are illustrated in Fig. 27 for


both capacitors after the RF pads are deembedded. Fig. 28 il-lustrates the measured quality factor for both capacitors. Thequality factor of the analog continuous capacitor is better than300 at 1.5 GHz at zero dc-bias voltage, which is at least 4.6 timesbetter than the quality factor of the conventional parallel-platecapacitor, reported in [11], due to the deeper trench obtained bythe combination of the dry and wet etching of the silicon sub-strate.

V. CONCLUSIONS

A maskless MEMS CMOS-compatible post-processing tech-nique that enables the fabrication of a parallel-plate capacitorstype for RF and microwave circuits has been introduced. Twostructures of curled-plate MEMS variable capacitors have beenproposed: a tri-state curled-plate capacitor and a analog con-tinuous curled-plate capacitor. Both capacitors have been fab-ricated by using commercially available 0.35- m CMOS tech-nology. The residual stress of the CMOS fabrication process hasbeen adopted as a feature to tailor the tuning performance of thecapacitors.

The tri-state curled-plate capacitor exhibits three levels ofmeasured capacitance whose values can be controlled by a setof beams. The proposed analog continuous capacitor exhibitedan almost linear measured tuning range of 115% with aneliminated pull-in voltage. These MEMS capacitors exhibit thehighest quality factor of MEMS variable capacitors built inCMOS.

The finite-element method software ANSYS was chosen tosimulate the mechanical behavior of the curled-plate capacitorsversus the applied voltage. A fit to measured curl-up data hasbeen implemented to simulate the curl up at zero-bias voltage.The ANSYS mechanical solution has been coupled to an anal-ysis based on the method of moments to determine the capaci-tance value versus the voltage for the proposed curled-plate ca-pacitors. The approach has provided theoretical results that arein good agreement with the measured data.

The thermal stability issue and reliability issue due to the di-electric charging effect are beyond the scope of this paper andwill be addressed in the future.

The post-processing technique is maskless and involves dry-and wet-etching stages. The proposed integrated MEMS/CMOSvariable capacitors have the potential to be useful as tuning el-ements in compact RF subsystems such as impedance tuners,VCOs, and miniaturized integrated tunable filters for silicon-on-chip (SoC).

REFERENCES

[1] G. Rebeiz, RF MEMS: Theory, Design, and Technology, 1st ed. NewYork: Wiley, 2003.

[2] I. Borwick, R. L. P. Stupar, J. DeNatale, R. Anderson, and R. Er-landson, “Variable MEMS capacitors implemented into RF filter sys-tems,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 1, pp. 315–319,Jan. 2003.

[3] M. Bakri-Kassem and R. Mansour, “Two movable-plate nitride-loadedMEMS variable capacitor,” IEEE Trans. Microw. Theory Tech., vol. 52,no. 3, pp. 831–837, Mar. 2004.

[4] F. Faheem, K. Gupta, and Y.-C. Lee, “Flip-chip assembly and liquidcrystal polymer encapsulation for variable MEMS capacitors,” IEEETrans. Microw. Theory Tech., vol. 51, no. 12, pp. 2562–2567, Dec.2003.

[5] M. Bakri-Kassem and R. Mansour, “A high-tuning-range MEMS vari-able capacitor using carrier beams,” Can. J. Elect. Comput. Eng., vol.31, no. 2, pp. 89–95, Spring, 2006.

[6] C. Tsai, P. Stupar, I. Borwick, R. L. M. Pai, and J. DeNatale, “Anisolated tunable capacitor with a linear capacitance–voltage behavior,”in 12th Int. Solid-State Sens., Actuators, Microsyst. Conf., Jun. 8–12,2003, vol. 1, pp. 833–836.

[7] M. Bakri-Kassem and R. Mansour, “High tuning range parallel plateMEMS variable capacitors with arrays of supporting beams,” in19th IEEE Int. MEMS Conf., Istanbul, Turkey, Jan. 22–26, 2006, pp.666–669.

[8] A. Oz and G. Fedder, “CMOS-compatible RF-MEMS tunable capac-itors,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 8–13, 2003, vol.1, pp. A97–A100.

[9] J. Muldavin, C. Bozler, S. Rabe, and C. Keast, “Largetuning range analog and multi-bit MEMS varactors,” in IEEEMTT-S Int. Microw. Symp. Dig., Jun. 6–11, 2004, vol. 3,pp. 1919–1922.

[10] T. Rijks, J. van Beek, P. Steeneken, M. Ulenaers, J. De Coster, and R.Puers, “RF MEMS tunable capacitors with large tuning ratio,” in 17thIEEE Int. MEMS Conf., 2004, pp. 777–780.

[11] S. Fouladi, M. Bakri-Kassem, and R. R. Mansour, “An integrated tun-able bandpass filter using MEMS parallel-plate variable capacitors im-plemented with 0.35 �m CMOS technology,” in IEEE MTT-S Int. Mi-crow. Symp. Dig., Jun. 3–8, 2007, pp. 505–508.

[12] H. Xie, Y. Pan, and G. Fedder, “A CMOS-MEMS mirror withcurled-hinge comb drives,” J. Microelectromech. Syst., vol. 12, no. 4,pp. 450–457, Aug. 2003.

[13] G. Fedder, S. Santhanam, M. Reed, S. Eagle, D. Guillou, M.-C. Lu, andL. Carley, “Laminated high-aspect-ratio microstructures in a conven-tional CMOS process,” in Proc. 9th Annu. Int. IEEE MEMS Workshop,Feb. 11–15, 1996, pp. 13–18.

[14] C.-T. Ko, J.-P. Wu, W.-C. Wang, C.-H. Huang, S.-H. Tseng, Y.-L.Chen, and M.-C. Lu, “A highly sensitive CMOS-MEMS capacitive tac-tile sensor,” in Proc. 19th Int. IEEE MEMS Conf., Istanbul, Turkey, Jan.22–26, 2006, pp. 642–645.

[15] K. Williams, K. Gupta, and M. Wasilik, “Etch rates for micromachiningprocessing—Part II,” J. Microelectromech. Syst., vol. 12, no. 6, pp.761–778, Dec. 2003.

[16] S. D. Senturia, Microsystem Design, F. Printing, Ed. Norwell, MA:Kluwer, 2002.

[17] R. F. Harrington, Field Computation by Moment Methods Book, 1sted. New York: Wiley, 2001.

[18] Y. Yoon and B. Kim, “A new formula for effective dielectricconstant in multi-dielectric layer microstrip structure,” in IEEEElect. Perform. Electron. Packag. Conf., Oct. 23–25, 2000,pp. 163–167.

[19] G. Zhang, H. Xie, L. de Rosset, and G. Fedder, “A lateralcapacitive CMOS accelerometer with structural curl compensation,”in Proc. 12th IEEE Int. MEMS Conf., Jan. 17–21, 1999,pp. 606–611.

[20] M.-A. Eyoum, N. Hoivik, C. Jahnes, J. Cotte, and X.-H. Liu,“Analysis and modeling of curvature in copper-based structuresfabricated using CMOS interconnect technology,” in 13th Int.Solid-State Sens., Actuators, Microsyst. Conf. Tech. Dig., Jun.5–9, 2005, vol. 1, pp. 764–767.

[21] N. Hoivik, M. Michalicek, Y. Lee, K. Gupta, and V. Bright, “Digitallycontrollable variable high-QMEMS capacitor for RF applications,” inIEEE MTT-S Int. Microw. Symp. Dig., May 20–25, 2001, vol. 3, pp.2115–2118.

[22] R. Legtenberg, J. Gilbert, S. Senturia, and M. Elwenspoek, “Electro-static curved electrode actuators,” J. Microelectromech. Syst., vol. 6,no. 3, pp. 257–265, Sep. 1997.

[23] L. C. Wei, A. Mohammad, and N. Kassim, “Analytical modeling fordetermination of pull-in voltage for an electrostatic actuated MEMScantilever beam,” in Proc. Int. IEEE Semiconduct. Electron. Conf., Dec.19–21, 2002, pp. 233–238.

[24] Y.-C. Hu, “Closed form solutions for the pull-in voltage of micro curledbeams subjected to electrostatic loads to electrostatic loads,” J. Mi-cromech. Microeng., vol. 16, pp. 648–655, Mar. 2006.

[25] G. K. Fedder, “Simulation of microelectromechanical systems,” Ph.D.dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California atBerkeley, Berkeley, CA, 1994.


Maher Bakri-Kassem (S’01–M’06) was born inKuwait City, Kuwait, on December 19, 1972. Hereceived the B.Sc. degree in electrical engineeringfrom Damascus University, Damascus, Syria, in1996, and the M.A.Sc. and Ph.D. degrees in electricalengineering from the University of Waterloo, Wa-terloo, ON, Canada, in 2002 and 2007, respectively.

In 2001, he joined the Center for IntegratedRF Engineering (CIRFE), where he was involvedwith the design, optimization, and fabrication ofRF/microwave circuits, RF MEMS devices, and RF

MEMS/CMOS integrated circuits. He was also a Research and Teaching As-sistant with the Electrical and Computer Engineering Department, Universityof Waterloo. He is currently with the Research and Development Department,Custom Products Business Unit, MEMSCAP Inc., Durham, NC. His researchinterests are MEMS devices for biomedical applications, MEMS/CMOSintegration for intelligent systems-on-chip for biomedical and wireless appli-cations, MEMS linear sensors and MEMS linear large stroke actuators, andMEMS technology for millimeter-wave, RF, and microwave applications.

Siamak Fouladi (S’05) received the B.Sc. degreein electrical engineering from the University ofTehran, Tehran, Iran, in 2002, the M.Sc. degree inelectrical engineering from Concordia University,Montreal, QC, Canada, in 2005, and is currentlyworking toward the Ph.D. degree at the Universityof Waterloo, Waterloo, ON, Canada.

He is currently with the Center for Integrated RFEngineering (CIRFE), University of Waterloo, wherehe is involved with the fabrication and characteriza-tion of RF MEMS and CMOS RFICs and devices.

Raafat R. Mansour (S’84–M’86–SM’90–F’01) wasborn in Cairo, Egypt, on March 31, 1955. He receivedthe B.Sc. (with honors) and M.Sc. degrees from AinShams University, Cairo, Egypt, in 1977 and 1981,respectively, and the Ph.D. degree from the Univer-sity of Waterloo, Waterloo, ON, Canada, in 1986, allin electrical engineering.

In 1981, he was a Research Fellow with the Labo-ratoire d’Electromagnetisme, Institut National Poly-technique, Grenoble, Grenoble, France. From 1983 to1986, he was a Research and Teaching Assistant with

the Department of Electrical Engineering, University of Waterloo. In 1986, hejoined COM DEV Ltd., Cambridge, ON, Canada, where he held several tech-nical and management positions with the Corporate Research and DevelopmentDepartment. In 1998, he became a Scientist. In January 2000, he joined the Uni-versity of Waterloo, as a Professor with the Electrical and Computer EngineeringDepartment. He holds a Natural Sciences and Engineering Research Council ofCanada (NSERC) Industrial Research Chair in RF Engineering with the Uni-versity of Waterloo. He has authored or coauthored numerous publications inthe areas of filters and multiplexers and high-temperature superconductivity.He holds several patents related to microwave filter design for satellite applica-tions. His current research interests include superconductive technology, MEMStechnology, and computer-aided design (CAD) of RF circuits for wireless andsatellite applications.

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Novel High-Q MEMS Curled-Plate Variable Capacitors Fabricated in 0.35-μm CMOS Technology