Parallel IP Lookup using Multiple SRAM-based

Pipelines Authors: Weirong Jiang and Viktor K. Prasanna Presenter: Yi-Sheng, Lin (林意勝 ) Date: 2008.12.10 Publisher/Conf. : Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on

Dept. of Computer Science and Information Engineering National Cheng Kung University,

Taiwan R.O.C.

Outline

1. Introduction

2. Related Work

3. Architecture Overview

4. Memory Balancing

5. Traffic Balancing

6. Performance Evaluation

7. Conclusion

Introduction

Multiple pipelines can be utilized in parallel to improve the throughput further.

The memory distribution over different pipelines as well as across different stages of each pipeline must be balanced.

The traffic among these pipelines should be balanced. IP/prefix caching to utilize the locality of Internet traffic. [1, 14]

[1] M. J. Akhbarizadeh, M. Nourani, R. Panigrahy, and S. Sharma. A TCAM-based parallel architecture for highspeed packet forwarding. IEEE Trans. Comput.,56(1): 58–72, 2007.

[14] D. Lin, Y. Zhang, C. Hu, B. Liu, X. Zhang, and D. Pao. Route table partitioning and load balancing for parallel searching with TCAMs. In Proc. IPDPS ’07, pages 1–10.

Introduction

The caching may fail to capture the traffic locality due to the long pipeline delay.

A flow pre-caching scheme benefits from deep pipelining since it utilizes the inherent caching in the architecture.

The intra-flow packets may go out of order.

An approach called payload exchange, which exploits the pipeline delay, is used to maintain the intra-flow packet order.

Related Work

Related Work

Most published parallel IP lookup engines are TCAM-based. They partition the full routing table into several blocks, and make the search process parallel on different blocks.

Ex : Trie-based approaches Splits the trie by carving subtries.

[24] F. Zane, G. J. Narlikar, and A. Basu. CoolCAMs: Powerefficient TCAMs for forwarding engines. In Proc. INFOCOM’03, pages 42–52.

Architecture Overview

Architecture Overview

Lookup Engines : 1. The routing table is constructed as a leaf-pushed uni-bit trie.

2. To store the mapping function between subtries and pipelines, several small memories called Destination Index Tables (DITs) are used.

3. By searching the DIT, the packet also retrieves the address of the subtrie’s root in the first stage of the pipeline.

4. Each pipeline employs a multi-port queue to handle the access conflicts when multiple incoming packets are directed to the same pipeline.

Architecture Overview

Load Balancer : 1. Caching is an efficient way to exploit Internet traffic locality for par

allel IP lookup.2. Define a sequence of packets with the same destination IP addres

s as a flow.

3. We propose a scheme called flow pre-caching, which allows the destination IP address of a flow to be cached before its next-hop information is retrieved.

4. If the intra-flow out-oforder packet is detected, a task to exchange the payload between out-of-order packets is initiated.

Memory Balancing

Memory Balancing

Experimental results

Memory Balancing

Memory Balancing

Experimental results

Traffic Balancing

Flow Pre-Caching

Traffic Balancing

Detecting out-of-order packets

Performance Evaluation

Performance Evaluation

Performance Evaluation

Performance Evaluation

Performance Evaluation

Conclusion

This paper proposed a parallel SRAM-based multipipeline architecture for terabit trie-based IP lookup.

Memory and traffic balancing, and intra-flow packet ordering were identified as three major problems.

Our future work includes applying the SRAM-based pipeline architectures to multidimensional packet classification and deep packet inspection.